forked from OSchip/llvm-project
Move addPassesToEmitAssembly from TargetMachine to UltraSparc because it
really is sparc specific. llvm-svn: 4308
This commit is contained in:
parent
f9df48d34c
commit
e94db67c4f
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@ -8,7 +8,19 @@
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#include "SparcInternals.h"
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#include "SparcInternals.h"
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#include "llvm/Target/Sparc.h"
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#include "llvm/Target/Sparc.h"
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#include "llvm/Function.h"
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#include "llvm/Function.h"
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#include "llvm/PassManager.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/PreSelection.h"
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#include "llvm/CodeGen/StackSlots.h"
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#include "llvm/CodeGen/PeepholeOpts.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "llvm/CodeGen/RegisterAllocation.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/Reoptimizer/Mapping/MappingInfo.h"
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#include "llvm/Reoptimizer/Mapping/FInfo.h"
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#include "Support/CommandLine.h"
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using std::cerr;
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using std::cerr;
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// Build the MachineInstruction Description Array...
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// Build the MachineInstruction Description Array...
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@ -20,6 +32,19 @@ const MachineInstrDescriptor SparcMachineInstrDesc[] = {
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#include "SparcInstr.def"
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#include "SparcInstr.def"
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};
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};
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//---------------------------------------------------------------------------
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// Command line options to control choice of code generation passes.
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//---------------------------------------------------------------------------
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static cl::opt<bool> DisablePreSelect("nopreselect",
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cl::desc("Disable preselection pass"));
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static cl::opt<bool> DisableSched("nosched",
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cl::desc("Disable local scheduling pass"));
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static cl::opt<bool> DisablePeephole("nopeephole",
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cl::desc("Disable peephole optimization pass"));
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
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// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
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// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
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// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
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@ -88,6 +113,47 @@ UltraSparcFrameInfo::getDynamicAreaOffset(MachineFunction& mcInfo,
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return offset;
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return offset;
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}
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}
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//===---------------------------------------------------------------------===//
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// Default code generation passes.
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//
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// Native code generation for a specified target.
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//===---------------------------------------------------------------------===//
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class ConstructMachineCodeForFunction : public FunctionPass {
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TargetMachine &Target;
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public:
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ConstructMachineCodeForFunction(TargetMachine &T) : Target(T) {}
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const char *getPassName() const {
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return "ConstructMachineCodeForFunction";
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}
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bool runOnFunction(Function &F) {
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MachineFunction::construct(&F, Target);
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return false;
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}
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};
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struct FreeMachineCodeForFunction : public FunctionPass {
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const char *getPassName() const { return "FreeMachineCodeForFunction"; }
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static void freeMachineCode(Instruction &I) {
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MachineCodeForInstruction::destroy(&I);
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}
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bool runOnFunction(Function &F) {
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for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
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for (BasicBlock::iterator I = FI->begin(), E = FI->end(); I != E; ++I)
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MachineCodeForInstruction::get(I).dropAllReferences();
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for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
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for_each(FI->begin(), FI->end(), freeMachineCode);
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return false;
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}
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};
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// class UltraSparcMachine
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// class UltraSparcMachine
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@ -114,3 +180,56 @@ UltraSparc::UltraSparc()
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maxAtomicMemOpWordSize = 8;
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maxAtomicMemOpWordSize = 8;
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}
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}
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// addPassesToEmitAssembly - This method controls the entire code generation
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// process for the ultra sparc.
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//
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void UltraSparc::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
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{
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// Construct and initialize the MachineFunction object for this fn.
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PM.add(new ConstructMachineCodeForFunction(*this));
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//Insert empty stackslots in the stack frame of each function
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//so %fp+offset-8 and %fp+offset-16 are empty slots now!
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PM.add(createStackSlotsPass(*this));
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// Specialize LLVM code for this target machine and then
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// run basic dataflow optimizations on LLVM code.
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if (!DisablePreSelect)
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{
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PM.add(createPreSelectionPass(*this));
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/* PM.add(createReassociatePass()); */
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PM.add(createLICMPass());
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PM.add(createGCSEPass());
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}
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PM.add(createInstructionSelectionPass(*this));
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if (!DisableSched)
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PM.add(createInstructionSchedulingWithSSAPass(*this));
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PM.add(getRegisterAllocator(*this));
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PM.add(getPrologEpilogInsertionPass());
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if (!DisablePeephole)
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PM.add(createPeepholeOptsPass(*this));
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PM.add(MappingInfoForFunction(Out));
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// Output assembly language to the .s file. Assembly emission is split into
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// two parts: Function output and Global value output. This is because
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// function output is pipelined with all of the rest of code generation stuff,
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// allowing machine code representations for functions to be free'd after the
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// function has been emitted.
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//
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PM.add(getFunctionAsmPrinterPass(Out));
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PM.add(new FreeMachineCodeForFunction()); // Free stuff no longer needed
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// Emit Module level assembly after all of the functions have been processed.
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PM.add(getModuleAsmPrinterPass(Out));
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// Emit bytecode to the assembly file into its special section next
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PM.add(getEmitBytecodeToAsmPass(Out));
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PM.add(getFunctionInfo(Out));
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}
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@ -709,7 +709,6 @@ public:
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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class UltraSparc : public TargetMachine {
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class UltraSparc : public TargetMachine {
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private:
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UltraSparcInstrInfo instrInfo;
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UltraSparcInstrInfo instrInfo;
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UltraSparcSchedInfo schedInfo;
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UltraSparcSchedInfo schedInfo;
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UltraSparcRegInfo regInfo;
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UltraSparcRegInfo regInfo;
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@ -726,6 +725,8 @@ public:
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virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
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virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
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virtual const MachineOptInfo &getOptInfo() const { return optInfo; }
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virtual const MachineOptInfo &getOptInfo() const { return optInfo; }
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virtual void addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
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// getPrologEpilogCodeInserter - Inserts prolog/epilog code.
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// getPrologEpilogCodeInserter - Inserts prolog/epilog code.
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virtual Pass* getPrologEpilogInsertionPass();
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virtual Pass* getPrologEpilogInsertionPass();
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@ -8,34 +8,7 @@
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineInstrInfo.h"
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#include "llvm/Target/MachineInstrInfo.h"
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#include "llvm/Target/MachineCacheInfo.h"
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#include "llvm/Target/MachineCacheInfo.h"
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#include "llvm/CodeGen/PreSelection.h"
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#include "llvm/CodeGen/StackSlots.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "llvm/CodeGen/RegisterAllocation.h"
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#include "llvm/CodeGen/PeepholeOpts.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/Reoptimizer/Mapping/MappingInfo.h"
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#include "llvm/Reoptimizer/Mapping/FInfo.h"
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#include "llvm/Transforms/Scalar.h"
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#include "Support/CommandLine.h"
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#include "llvm/PassManager.h"
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#include "llvm/Function.h"
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#include "llvm/Function.h"
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#include "llvm/DerivedTypes.h"
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//---------------------------------------------------------------------------
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// Command line options to control choice of code generation passes.
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//---------------------------------------------------------------------------
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static cl::opt<bool> DisablePreSelect("nopreselect",
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cl::desc("Disable preselection pass"));
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static cl::opt<bool> DisableSched("nosched",
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cl::desc("Disable local scheduling pass"));
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static cl::opt<bool> DisablePeephole("nopeephole",
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cl::desc("Disable peephole optimization pass"));
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// class TargetMachine
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// class TargetMachine
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@ -71,101 +44,6 @@ TargetMachine::findOptimalStorageSize(const Type* ty) const
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}
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}
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//===---------------------------------------------------------------------===//
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// Default code generation passes.
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//
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// Native code generation for a specified target.
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//===---------------------------------------------------------------------===//
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class ConstructMachineCodeForFunction : public FunctionPass {
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TargetMachine &Target;
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public:
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inline ConstructMachineCodeForFunction(TargetMachine &T) : Target(T) {}
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const char *getPassName() const {
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return "ConstructMachineCodeForFunction";
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}
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bool runOnFunction(Function &F) {
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MachineFunction::construct(&F, Target);
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return false;
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}
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};
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struct FreeMachineCodeForFunction : public FunctionPass {
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const char *getPassName() const { return "FreeMachineCodeForFunction"; }
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static void freeMachineCode(Instruction &I) {
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MachineCodeForInstruction::destroy(&I);
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}
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bool runOnFunction(Function &F) {
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for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
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for (BasicBlock::iterator I = FI->begin(), E = FI->end(); I != E; ++I)
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MachineCodeForInstruction::get(I).dropAllReferences();
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for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
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for_each(FI->begin(), FI->end(), freeMachineCode);
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return false;
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}
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};
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// addPassesToEmitAssembly - This method controls the entire code generation
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// process for the ultra sparc.
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//
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void
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TargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
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{
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// Construct and initialize the MachineFunction object for this fn.
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PM.add(new ConstructMachineCodeForFunction(*this));
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//Insert empty stackslots in the stack frame of each function
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//so %fp+offset-8 and %fp+offset-16 are empty slots now!
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PM.add(createStackSlotsPass(*this));
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// Specialize LLVM code for this target machine and then
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// run basic dataflow optimizations on LLVM code.
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if (!DisablePreSelect)
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{
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PM.add(createPreSelectionPass(*this));
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/* PM.add(createReassociatePass()); */
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PM.add(createLICMPass());
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PM.add(createGCSEPass());
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}
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PM.add(createInstructionSelectionPass(*this));
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if (!DisableSched)
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PM.add(createInstructionSchedulingWithSSAPass(*this));
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PM.add(getRegisterAllocator(*this));
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PM.add(getPrologEpilogInsertionPass());
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if (!DisablePeephole)
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PM.add(createPeepholeOptsPass(*this));
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PM.add(MappingInfoForFunction(Out));
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// Output assembly language to the .s file. Assembly emission is split into
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// two parts: Function output and Global value output. This is because
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// function output is pipelined with all of the rest of code generation stuff,
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// allowing machine code representations for functions to be free'd after the
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// function has been emitted.
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//
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PM.add(getFunctionAsmPrinterPass(Out));
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PM.add(new FreeMachineCodeForFunction()); // Free stuff no longer needed
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// Emit Module level assembly after all of the functions have been processed.
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PM.add(getModuleAsmPrinterPass(Out));
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// Emit bytecode to the assembly file into its special section next
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PM.add(getEmitBytecodeToAsmPass(Out));
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PM.add(getFunctionInfo(Out));
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}
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// class MachineInstructionInfo
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// class MachineInstructionInfo
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// Interface to description of machine instructions
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// Interface to description of machine instructions
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