From e93e0d413f3afa1df5c5f88df546bebcd1183155 Mon Sep 17 00:00:00 2001 From: Sam Parker Date: Thu, 9 Jan 2020 08:33:47 +0000 Subject: [PATCH] [ARM][LowOverheadLoops] Update liveness info After expanding the pseudo instructions, update the liveness info. We do this in a post-order traversal of the loop, including its exit blocks and preheader(s). Differential Revision: https://reviews.llvm.org/D72131 --- llvm/lib/CodeGen/LivePhysRegs.cpp | 13 +++ llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 64 ++++++++++++ .../Thumb2/LowOverheadLoops/disjoint-vcmp.mir | 99 +++++++++---------- .../dont-remove-loop-update.mir | 2 +- .../dont-remove-loop-update2.mir | 4 +- .../dont-remove-loop-update3.mir | 2 +- .../Thumb2/LowOverheadLoops/loop-guards.ll | 22 ++--- .../LowOverheadLoops/mov-lr-terminator.mir | 6 +- .../move-def-before-start.mir | 6 +- .../LowOverheadLoops/move-start-after-def.mir | 6 +- .../LowOverheadLoops/unsafe-cpsr-loop-use.mir | 11 ++- .../Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir | 10 +- .../Thumb2/LowOverheadLoops/vctp-in-vpt.mir | 10 +- .../CodeGen/Thumb2/LowOverheadLoops/while.mir | 9 +- .../CodeGen/Thumb2/LowOverheadLoops/wlstp.mir | 24 ++--- 15 files changed, 180 insertions(+), 108 deletions(-) diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp b/llvm/lib/CodeGen/LivePhysRegs.cpp index 7a5cffca3470..547970e7ab5d 100644 --- a/llvm/lib/CodeGen/LivePhysRegs.cpp +++ b/llvm/lib/CodeGen/LivePhysRegs.cpp @@ -276,6 +276,7 @@ void llvm::recomputeLivenessFlags(MachineBasicBlock &MBB) { const MachineFunction &MF = *MBB.getParent(); const MachineRegisterInfo &MRI = MF.getRegInfo(); const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); // We walk through the block backwards and start with the live outs. LivePhysRegs LiveRegs; @@ -294,6 +295,18 @@ void llvm::recomputeLivenessFlags(MachineBasicBlock &MBB) { assert(Register::isPhysicalRegister(Reg)); bool IsNotLive = LiveRegs.available(MRI, Reg); + + // Special-case return instructions for cases when a return is not + // the last instruction in the block. + if (MI.isReturn() && MFI.isCalleeSavedInfoValid()) { + for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) { + if (Info.getReg() == Reg) { + IsNotLive = !Info.isRestored(); + break; + } + } + } + MO->setIsDead(IsNotLive); } diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp index 31a98d86a54d..d8b6a0e47d04 100644 --- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -43,6 +43,61 @@ using namespace llvm; namespace { + class PostOrderLoopTraversal { + MachineLoop &ML; + MachineLoopInfo &MLI; + SmallPtrSet Visited; + SmallVector Order; + + public: + PostOrderLoopTraversal(MachineLoop &ML, MachineLoopInfo &MLI) + : ML(ML), MLI(MLI) { } + + const SmallVectorImpl &getOrder() const { + return Order; + } + + // Visit all the blocks within the loop, as well as exit blocks and any + // blocks properly dominating the header. + void ProcessLoop() { + std::function Search = [this, &Search] + (MachineBasicBlock *MBB) -> void { + if (Visited.count(MBB)) + return; + + Visited.insert(MBB); + for (auto *Succ : MBB->successors()) { + if (!ML.contains(Succ)) + continue; + Search(Succ); + } + Order.push_back(MBB); + }; + + // Insert exit blocks. + SmallVector ExitBlocks; + ML.getExitBlocks(ExitBlocks); + for (auto *MBB : ExitBlocks) + Order.push_back(MBB); + + // Then add the loop body. + Search(ML.getHeader()); + + // Then try the preheader and its predecessors. + std::function GetPredecessor = + [this, &GetPredecessor] (MachineBasicBlock *MBB) -> void { + Order.push_back(MBB); + if (MBB->pred_size() == 1) + GetPredecessor(*MBB->pred_begin()); + }; + + if (auto *Preheader = ML.getLoopPreheader()) + GetPredecessor(Preheader); + else if (auto *Preheader = MLI.findLoopPreheader(&ML, true)) + GetPredecessor(Preheader); + } + }; + struct PredicatedMI { MachineInstr *MI = nullptr; SetVector Predicates; @@ -976,6 +1031,15 @@ void ARMLowOverheadLoops::Expand(LowOverheadLoop &LoLoop) { ConvertVPTBlocks(LoLoop); } } + + PostOrderLoopTraversal DFS(*LoLoop.ML, *MLI); + DFS.ProcessLoop(); + const SmallVectorImpl &PostOrder = DFS.getOrder(); + for (auto *MBB : PostOrder) + recomputeLiveIns(*MBB); + + for (auto *MBB : reverse(PostOrder)) + recomputeLivenessFlags(*MBB); } bool ARMLowOverheadLoops::RevertNonLoops() { diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir index cafd1317c57c..aa8954df1c59 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s +# --- | @mask = external global i16 - ; Function Attrs: nofree norecurse nounwind define dso_local void @test(i32* noalias nocapture %arg, i32* noalias nocapture readonly %arg1, i32 %arg2, i32* noalias nocapture readonly %arg3) local_unnamed_addr #0 { bb: %tmp = icmp eq i32 %arg2, 0 @@ -16,8 +16,6 @@ %mask.load = load i16, i16* %mask.gep9 %conv.mask = zext i16 %mask.load to i32 %invariant.mask = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %conv.mask) - %mask.insert = insertelement <4 x i32> undef, i32 %conv.mask, i32 0 - %invariant.limits = shufflevector <4 x i32> %mask.insert, <4 x i32> undef, <4 x i32> zeroinitializer br i1 %tmp, label %bb27, label %bb3 bb3: ; preds = %bb @@ -31,18 +29,20 @@ %lsr.iv = phi i32* [ %scevgep, %bb9 ], [ %arg, %bb3 ] %tmp7 = phi i32 [ %tmp6, %bb3 ], [ %tmp12, %bb9 ] %tmp8 = phi i32 [ %arg2, %bb3 ], [ %tmp11, %bb9 ] - %lsr.iv47 = bitcast i32* %lsr.iv4 to <4 x i32>* %lsr.iv1 = bitcast i32* %lsr.iv to <4 x i32>* %lsr.iv24 = bitcast i32* %lsr.iv2 to <4 x i32>* + %lsr.iv47 = bitcast i32* %lsr.iv4 to <4 x i32>* %vctp = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp8) %and = and <4 x i1> %vctp, %invariant.mask %tmp11 = sub i32 %tmp8, 4 %tmp17 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv24, i32 4, <4 x i1> %and, <4 x i32> undef) %tmp22 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1, i32 4, <4 x i1> %and, <4 x i32> undef) %tmp23 = mul nsw <4 x i32> %tmp22, %tmp17 - %scevgep8 = getelementptr <4 x i32>, <4 x i32>* %lsr.iv47, i32 1 - %load.limits = load <4 x i32>, <4 x i32>* %scevgep8 - %bad.icmp = icmp ule <4 x i32> %load.limits, %invariant.limits + %scevgep2 = getelementptr <4 x i32>, <4 x i32>* %lsr.iv47, i32 1 + %load.limits = load <4 x i32>, <4 x i32>* %scevgep2 + %0 = insertelement <4 x i32> undef, i32 %conv.mask, i32 0 + %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer + %bad.icmp = icmp ule <4 x i32> %load.limits, %1 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %tmp23, <4 x i32>* %lsr.iv1, i32 4, <4 x i1> %bad.icmp) %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp7, i32 1) %tmp13 = icmp ne i32 %tmp12, 0 @@ -54,13 +54,12 @@ bb27: ; preds = %bb9, %bb ret void } - declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #1 - declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #2 - declare void @llvm.set.loop.iterations.i32(i32) #3 - declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3 - declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4 - declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #4 - declare void @llvm.stackprotector(i8*, i8**) #5 + declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) + declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) + declare void @llvm.set.loop.iterations.i32(i32) + declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) + declare <4 x i1> @llvm.arm.mve.vctp32(i32) + declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) ... --- @@ -85,7 +84,7 @@ frameInfo: hasStackMap: false hasPatchPoint: false stackSize: 20 - offsetAdjustment: -12 + offsetAdjustment: 0 maxAlignment: 4 adjustsStack: false hasCalls: false @@ -110,7 +109,7 @@ stack: stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 3, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, + stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 4, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, @@ -122,37 +121,36 @@ body: | ; CHECK-LABEL: name: test ; CHECK: bb.0.bb: ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r6, $lr - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: liveins: $r3, $r2, $r0, $r1, $r4, $r5, $r7, $lr + ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: $r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: tCBZ $r2, %bb.3 ; CHECK: bb.1.bb3: ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 + ; CHECK: liveins: $r3, $r2, $r0, $r1 ; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14, $noreg - ; CHECK: renamable $lr = t2ADDri renamable $r2, 3, 14, $noreg, $noreg + ; CHECK: renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg ; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14, $noreg - ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2LDRHi12 killed renamable $r12, 0, 14, $noreg :: (dereferenceable load 2 from %ir.mask.gep9) - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg + ; CHECK: renamable $r4 = t2BICri killed renamable $r4, 3, 14, $noreg, $noreg + ; CHECK: renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14, $noreg :: (dereferenceable load 2 from %ir.mask.gep9) + ; CHECK: renamable $r12 = t2SUBri killed renamable $r4, 4, 14, $noreg, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: $vpr = VMSR_P0 $r12, 14, $noreg - ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, undef renamable $q0 + ; CHECK: $vpr = VMSR_P0 $r5, 14, $noreg + ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) + ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 ; CHECK: $r3 = tMOVr $r0, 14, $noreg - ; CHECK: $lr = t2DLS renamable $lr + ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.bb9: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12 + ; CHECK: liveins: $lr, $r2, $r12, $r0, $q0, $r1, $r3 ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0) ; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr @@ -160,28 +158,26 @@ body: | ; CHECK: renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4) ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 - ; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep8, align 8) - ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q0, killed renamable $q2, 2, 0, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr + ; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep2, align 8) + ; CHECK: MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr ; CHECK: MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4) ; CHECK: $r0 = tMOVr $r3, 14, $noreg - ; CHECK: $lr = t2LEUpdate renamable $lr, %bb.2 + ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.bb27: ; CHECK: $sp = tADDspi $sp, 1, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc + ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc bb.0.bb: successors: %bb.3(0x30000000), %bb.1(0x50000000) - liveins: $r0, $r1, $r2, $r3, $r4, $r6, $lr + liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr - frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp + frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 16 frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 - frame-setup CFI_INSTRUCTION offset $r6, -12 + frame-setup CFI_INSTRUCTION offset $r5, -12 frame-setup CFI_INSTRUCTION offset $r4, -16 - $r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg - frame-setup CFI_INSTRUCTION def_cfa $r7, 8 $sp = frame-setup tSUBspi $sp, 1, 14, $noreg + frame-setup CFI_INSTRUCTION def_cfa_offset 20 tCBZ $r2, %bb.3 bb.1.bb3: @@ -189,17 +185,17 @@ body: | liveins: $r0, $r1, $r2, $r3 $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14, $noreg - renamable $lr = t2ADDri renamable $r2, 3, 14, $noreg, $noreg + renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14, $noreg - renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg - renamable $r12 = t2LDRHi12 killed renamable $r12, 0, 14, $noreg :: (dereferenceable load 2 from %ir.mask.gep9) - renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg + renamable $r4 = t2BICri killed renamable $r4, 3, 14, $noreg, $noreg + renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14, $noreg :: (dereferenceable load 2 from %ir.mask.gep9) + renamable $r12 = t2SUBri killed renamable $r4, 4, 14, $noreg, $noreg renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg - $vpr = VMSR_P0 $r12, 14, $noreg - renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, undef renamable $q0 + $vpr = VMSR_P0 $r5, 14, $noreg + renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg - renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) + renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 $r3 = tMOVr $r0, 14, $noreg t2DoLoopStart renamable $lr @@ -214,9 +210,8 @@ body: | renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4) renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 - renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep8, align 8) - renamable $vpr = MVE_VCMPu32 renamable $q0, killed renamable $q2, 2, 0, $noreg - MVE_VPST 8, implicit $vpr + renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep2, align 8) + MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4) renamable $lr = t2LoopDec killed renamable $lr, 1 $r0 = tMOVr $r3, 14, $noreg @@ -225,6 +220,6 @@ body: | bb.3.bb27: $sp = tADDspi $sp, 1, 14, $noreg - tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc + tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc ... diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir index 976c5f5d7ba3..414ccd94804b 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir @@ -6,7 +6,7 @@ # CHECK: bb.1.vector.body: # CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg # CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg -# CHECK: $lr = MVE_LETP renamable $lr, %bb.1 +# CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir index 9e429040db4f..68f245f2ed91 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir @@ -7,8 +7,8 @@ # We shouldn't optimise away the SUB. # CHECK: bb.1.vector.body: -# CHECK: renamable $r3, $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg -# CHECK: $lr = MVE_LETP renamable $lr, %bb.1 +# CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg +# CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update3.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update3.mir index ab7fcf843d7d..e99cf7ad631e 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update3.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update3.mir @@ -8,7 +8,7 @@ # CHECK: bb.1.vector.body: # CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg -# CHECK: $lr = MVE_LETP renamable $lr, %bb.1 +# CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll index fd8cc9b92f2f..f23b64013c35 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll @@ -18,9 +18,9 @@ ; CHECK: t2CMPri renamable $lr, 0 ; CHECK: tBcc %bb.3 ; CHECK: bb.1.while.body.preheader: -; CHECK: $lr = t2DLS renamable $lr +; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.while.body: -; CHECK: $lr = t2LEUpdate renamable $lr, %bb.2 +; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 define void @ne_and_guard(i1 zeroext %t1, i1 zeroext %t2, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) { entry: %brmerge.demorgan = and i1 %t1, %t2 @@ -51,9 +51,9 @@ if.end: ; preds = %while.body, %entry ; CHECK: t2CMPri renamable $lr, 0 ; CHECK: tBcc %bb.3 ; CHECK: bb.1.while.body.preheader: -; CHECK: $lr = t2DLS renamable $lr +; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.while.body: -; CHECK: $lr = t2LEUpdate renamable $lr, %bb.2 +; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 define void @ne_preheader(i1 zeroext %t1, i1 zeroext %t2, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) { entry: %brmerge.demorgan = and i1 %t1, %t2 @@ -86,9 +86,9 @@ if.end: ; preds = %while.body, %while. ; CHECK: t2CMPri renamable $lr, 0 ; CHECK: tBcc %bb.3 ; CHECK: bb.1.while.body.preheader: -; CHECK: $lr = t2DLS renamable $lr +; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.while.body: -; CHECK: $lr = t2LEUpdate renamable $lr, %bb.2 +; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 define void @eq_preheader(i1 zeroext %t1, i1 zeroext %t2, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) { entry: %brmerge.demorgan = and i1 %t1, %t2 @@ -121,9 +121,9 @@ if.end: ; preds = %while.body, %while. ; CHECK: t2CMPri renamable $lr, 0 ; CHECK: tBcc %bb.3 ; CHECK: bb.1.while.body.preheader: -; CHECK: $lr = t2DLS renamable $lr +; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.while.body: -; CHECK: $lr = t2LEUpdate renamable $lr, %bb.2 +; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 define void @ne_prepreheader(i1 zeroext %t1, i1 zeroext %t2, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) { entry: %cmp = icmp ne i32 %N, 0 @@ -152,9 +152,9 @@ if.end: ; preds = %while.body, %while. ; CHECK: be_ne ; CHECK: body: ; CHECK: bb.0.entry: -; CHECK: $lr = t2DLS renamable $lr +; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.1.do.body: -; CHECK: $lr = t2LEUpdate renamable $lr, %bb.1 +; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 define void @be_ne(i32* nocapture %a, i32* nocapture readonly %b, i32 %N) { entry: %cmp = icmp ne i32 %N, 0 @@ -187,7 +187,7 @@ if.end: ; preds = %do.body, %entry ; CHECK: bb.1.do.body.preheader: ; CHECK: $lr = tMOVr ; CHECK: bb.2.do.body: -; CHECK: $lr = t2LEUpdate renamable $lr, %bb.2 +; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 define void @ne_trip_count(i1 zeroext %t1, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) { entry: br label %do.body.preheader diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir index 57fe0492f1eb..ef8e726eeaed 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir @@ -100,7 +100,7 @@ body: | ; CHECK-LABEL: name: start_before_elems ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $lr + ; CHECK: liveins: $r1, $r0, $r2, $r3, $r4, $lr ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -114,7 +114,7 @@ body: | ; CHECK: $lr = MVE_DLSTP_32 renamable $r12 ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 + ; CHECK: liveins: $lr, $r0, $r12, $r2, $r3, $r1 ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1) ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg @@ -123,7 +123,7 @@ body: | ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1) ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4) - ; CHECK: $lr = MVE_LETP renamable $lr, %bb.1 + ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: ; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc bb.0.entry: diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir index ff49bb0770ee..a4fceb6f54ae 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir @@ -107,7 +107,7 @@ body: | ; CHECK-LABEL: name: start_before_elems ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $lr + ; CHECK: liveins: $r1, $r0, $r2, $r3, $r4, $lr ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -122,7 +122,7 @@ body: | ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 + ; CHECK: liveins: $lr, $r0, $r12, $r2, $r3, $r1 ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1) ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg @@ -131,7 +131,7 @@ body: | ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1) ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4) - ; CHECK: $lr = MVE_LETP renamable $lr, %bb.1 + ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: ; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc bb.0.entry: diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir index 3fb203ee1938..77c70ab4d22b 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir @@ -105,7 +105,7 @@ body: | ; CHECK-LABEL: name: start_before_elems ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $lr + ; CHECK: liveins: $r1, $r0, $r2, $r3, $r4, $lr ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -120,7 +120,7 @@ body: | ; CHECK: $lr = MVE_DLSTP_32 renamable $r12 ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 + ; CHECK: liveins: $lr, $r0, $r12, $r2, $r3, $r1 ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1) ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg @@ -129,7 +129,7 @@ body: | ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1) ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4) - ; CHECK: $lr = MVE_LETP renamable $lr, %bb.1 + ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: ; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc bb.0.entry: diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir index 5f4a10249684..f8e5351d4e6c 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir @@ -94,7 +94,7 @@ body: | ; CHECK-LABEL: name: do_copy ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r7, $lr + ; CHECK: liveins: $r2, $r1, $r7, $lr ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -102,18 +102,19 @@ body: | ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg ; CHECK: renamable $r2 = t2LSRri renamable $r0, 1, 14, $noreg, $noreg - ; CHECK: $lr = tMOVr killed $r0, 14, $noreg + ; CHECK: $lr = tMOVr $r0, 14, $noreg ; CHECK: bb.1.while.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 + ; CHECK: liveins: $lr, $r0, $r2, $r1 ; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7) ; CHECK: tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, $noreg ; CHECK: t2IT 2, 8, implicit-def $itstate - ; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate + ; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4) + ; CHECK: renamable $lr = tMOVr killed $lr, 14, $noreg ; CHECK: t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.1, 1, $cpsr + ; CHECK: tBcc %bb.1, 1, killed $cpsr ; CHECK: tB %bb.2, 14, $noreg ; CHECK: bb.2.while.end: ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir index 83dc8731f654..a8d0b500af1e 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir @@ -134,7 +134,7 @@ body: | ; CHECK-LABEL: name: test ; CHECK: bb.0.bb: ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $lr + ; CHECK: liveins: $r1, $r2, $r0, $r3, $lr ; CHECK: frame-setup tPUSH 14, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -145,7 +145,7 @@ body: | ; CHECK: tCBZ $r2, %bb.3 ; CHECK: bb.1.bb3: ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 + ; CHECK: liveins: $r1, $r2, $r0, $r3 ; CHECK: renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg @@ -154,10 +154,10 @@ body: | ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) ; CHECK: $r3 = tMOVr $r0, 14, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg - ; CHECK: $lr = t2DLS renamable $lr + ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.bb9: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK: liveins: $lr, $r2, $r3, $r0, $r1 ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0) ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr @@ -171,7 +171,7 @@ body: | ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4, !tbaa !3) ; CHECK: $r0 = tMOVr $r3, 14, $noreg - ; CHECK: $lr = t2LEUpdate renamable $lr, %bb.2 + ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.bb27: ; CHECK: $sp = tADDspi $sp, 1, 14, $noreg ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir index fd6345693e83..00bb972580a1 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir @@ -131,7 +131,7 @@ body: | ; CHECK-LABEL: name: test ; CHECK: bb.0.bb: ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $lr + ; CHECK: liveins: $r0, $r2, $r1, $r3, $lr ; CHECK: frame-setup tPUSH 14, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -142,14 +142,14 @@ body: | ; CHECK: tCBZ $r2, %bb.3 ; CHECK: bb.1.bb3: ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 + ; CHECK: liveins: $r0, $r2, $r1, $r3 ; CHECK: $vpr = VMSR_P0 killed $r3, 14, $noreg ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) ; CHECK: $r3 = tMOVr $r0, 14, $noreg - ; CHECK: $lr = MVE_DLSTP_32 renamable $r2 + ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: bb.2.bb9: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK: liveins: $lr, $r3, $r1, $r0 ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0) ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4, !tbaa !3) @@ -158,7 +158,7 @@ body: | ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4, !tbaa !3) ; CHECK: $r0 = tMOVr $r3, 14, $noreg - ; CHECK: $lr = MVE_LETP renamable $lr, %bb.2 + ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: bb.3.bb27: ; CHECK: $sp = tADDspi $sp, 1, 14, $noreg ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir index 1ed9339a9f62..78ec447c37c1 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir @@ -1,6 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s - # TODO: Remove the lr = tMOVr --- | @@ -91,15 +90,15 @@ body: | ; CHECK-LABEL: name: copy ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) - ; CHECK: liveins: $r0, $r1, $r2, $r7, $lr + ; CHECK: liveins: $r0, $r2, $r1, $r7, $lr ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: $lr = t2WLS $r2, %bb.3 + ; CHECK: dead $lr = t2WLS $r2, %bb.3 ; CHECK: bb.1.while.body.preheader: ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 + ; CHECK: liveins: $r0, $r2, $r1 ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg ; CHECK: $lr = tMOVr killed $r2, 14, $noreg @@ -108,7 +107,7 @@ body: | ; CHECK: liveins: $lr, $r0, $r1 ; CHECK: renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep4) ; CHECK: early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep7) - ; CHECK: $lr = t2LEUpdate renamable $lr, %bb.2 + ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.while.end: ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc bb.0.entry: diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir index 33389f4c2941..44a072ac291b 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir @@ -199,11 +199,11 @@ body: | ; CHECK: tB %bb.3, 14, $noreg ; CHECK: bb.1.vector.ph: ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK: liveins: $lr, $r1, $r2, $r3, $r0 ; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 + ; CHECK: liveins: $lr, $r12, $r2, $r3, $r0, $r1 ; CHECK: renamable $r4 = t2ADDrr renamable $r1, renamable $r12, 14, $noreg, $noreg ; CHECK: renamable $q0 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg :: (load 16 from %ir.scevgep45, align 1) ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r12, 14, $noreg, $noreg @@ -213,7 +213,7 @@ body: | ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg ; CHECK: renamable $q0 = MVE_VMULi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: MVE_VSTRBU8 killed renamable $q0, killed renamable $r4, 0, 0, killed $noreg :: (store 16 into %ir.scevgep1, align 1) - ; CHECK: $lr = MVE_LETP renamable $lr, %bb.2 + ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: bb.3.for.cond.cleanup: ; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc bb.0.entry: @@ -313,7 +313,7 @@ body: | ; CHECK-LABEL: name: test_wlstp16 ; CHECK: bb.0.entry: ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r7, $lr + ; CHECK: liveins: $r1, $r3, $r0, $r2, $r7, $lr ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -322,7 +322,7 @@ body: | ; CHECK: tB %bb.2, 14, $noreg ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.2(0x04000000), %bb.1(0x7c000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK: liveins: $lr, $r3, $r0, $r2, $r1 ; CHECK: renamable $q0 = MVE_VLDRHU16 renamable $r1, 0, 0, $noreg :: (load 16 from %ir.lsr.iv57, align 2) ; CHECK: renamable $q1 = MVE_VLDRHU16 renamable $r2, 0, 0, $noreg :: (load 16 from %ir.lsr.iv24, align 2) ; CHECK: renamable $q0 = MVE_VMULi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 @@ -331,7 +331,7 @@ body: | ; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14, $noreg ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14, $noreg - ; CHECK: $lr = MVE_LETP renamable $lr, %bb.1 + ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc bb.0.entry: @@ -422,7 +422,7 @@ body: | ; CHECK-LABEL: name: test_wlstp32 ; CHECK: bb.0.entry: ; CHECK: successors: %bb.4(0x40000000), %bb.1(0x40000000) - ; CHECK: liveins: $r0, $r1, $r2, $r7, $lr + ; CHECK: liveins: $r1, $r2, $r0, $r7, $lr ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -432,12 +432,12 @@ body: | ; CHECK: tB %bb.4, 14, $noreg ; CHECK: bb.1.vector.ph: ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 + ; CHECK: liveins: $r2, $r0, $lr, $r1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000) - ; CHECK: liveins: $lr, $q1, $r0, $r1, $r2 - ; CHECK: $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0 + ; CHECK: liveins: $r2, $r0, $lr, $r1, $q1 + ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, $noreg :: (load 16 from %ir.lsr.iv24, align 4) ; CHECK: renamable $q2 = MVE_VLDRWU32 renamable $r1, 0, 0, killed $noreg :: (load 16 from %ir.lsr.iv1, align 4) ; CHECK: $r3 = tMOVr $r2, 14, $noreg @@ -446,10 +446,10 @@ body: | ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14, $noreg ; CHECK: renamable $q1 = nsw MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 - ; CHECK: $lr = MVE_LETP renamable $lr, %bb.2 + ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: bb.3.middle.block: ; CHECK: successors: %bb.4(0x80000000) - ; CHECK: liveins: $q0, $q1, $r3 + ; CHECK: liveins: $q1, $q0, $r3 ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg