forked from OSchip/llvm-project
[X86] Support fp128 and/or/xor/load/store with VEX and EVEX encoded instructions.
Move all the patterns to X86InstrVecCompiler.td so we can keep SSE/AVX/AVX512 all in one place. To save some patterns we'll use an existing DAG combine to convert f128 fand/for/fxor to integer when sse2 is enabled. This allows use to reuse all the existing patterns for v2i64. I believe this now makes SHA instructions the only case where VEX/EVEX and legacy encoded instructions could be generated simultaneously. llvm-svn: 338821
This commit is contained in:
Craig Topper
parent
58d837d347
commit
e902b7d0b0
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@ -613,7 +613,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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// Long double always uses X87, except f128 in MMX.
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if (UseX87) {
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if (Subtarget.is64Bit() && Subtarget.hasMMX()) {
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addRegisterClass(MVT::f128, &X86::VR128RegClass);
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addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
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: &X86::VR128RegClass);
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ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
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setOperationAction(ISD::FABS , MVT::f128, Custom);
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setOperationAction(ISD::FNEG , MVT::f128, Custom);
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@ -36981,7 +36982,7 @@ static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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MVT VT = N->getSimpleValueType(0);
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// If we have integer vector types available, use the integer opcodes.
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if (VT.isVector() && Subtarget.hasSSE2()) {
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if ((VT.isVector() || VT == MVT::f128) && Subtarget.hasSSE2()) {
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SDLoc dl(N);
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MVT IntVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
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@ -8131,51 +8131,6 @@ let Predicates = [UseAVX2] in {
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}
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}
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//===----------------------------------------------------------------------===//
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// Extra selection patterns for f128, f128mem
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// movaps is shorter than movdqa. movaps is in SSE and movdqa is in SSE2.
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def : Pat<(alignedstore (f128 VR128:$src), addr:$dst),
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(MOVAPSmr addr:$dst, (COPY_TO_REGCLASS (f128 VR128:$src), VR128))>;
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def : Pat<(store (f128 VR128:$src), addr:$dst),
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(MOVUPSmr addr:$dst, (COPY_TO_REGCLASS (f128 VR128:$src), VR128))>;
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def : Pat<(alignedloadf128 addr:$src),
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(COPY_TO_REGCLASS (MOVAPSrm addr:$src), VR128)>;
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def : Pat<(loadf128 addr:$src),
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(COPY_TO_REGCLASS (MOVUPSrm addr:$src), VR128)>;
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// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
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def : Pat<(f128 (X86fand VR128:$src1, (memopf128 addr:$src2))),
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(COPY_TO_REGCLASS
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(ANDPSrm (COPY_TO_REGCLASS VR128:$src1, VR128), f128mem:$src2),
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VR128)>;
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def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)),
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(COPY_TO_REGCLASS
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(ANDPSrr (COPY_TO_REGCLASS VR128:$src1, VR128),
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(COPY_TO_REGCLASS VR128:$src2, VR128)), VR128)>;
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def : Pat<(f128 (X86for VR128:$src1, (memopf128 addr:$src2))),
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(COPY_TO_REGCLASS
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(ORPSrm (COPY_TO_REGCLASS VR128:$src1, VR128), f128mem:$src2),
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VR128)>;
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def : Pat<(f128 (X86for VR128:$src1, VR128:$src2)),
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(COPY_TO_REGCLASS
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(ORPSrr (COPY_TO_REGCLASS VR128:$src1, VR128),
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(COPY_TO_REGCLASS VR128:$src2, VR128)), VR128)>;
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def : Pat<(f128 (X86fxor VR128:$src1, (memopf128 addr:$src2))),
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(COPY_TO_REGCLASS
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(XORPSrm (COPY_TO_REGCLASS VR128:$src1, VR128), f128mem:$src2),
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VR128)>;
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def : Pat<(f128 (X86fxor VR128:$src1, VR128:$src2)),
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(COPY_TO_REGCLASS
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(XORPSrr (COPY_TO_REGCLASS VR128:$src1, VR128),
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(COPY_TO_REGCLASS VR128:$src2, VR128)), VR128)>;
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//===----------------------------------------------------------------------===//
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// GFNI instructions
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//===----------------------------------------------------------------------===//
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@ -49,6 +49,19 @@ def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
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def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
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def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
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def : Pat<(f128 (bitconvert (v2i64 VR128:$src))), (f128 VR128:$src)>;
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def : Pat<(f128 (bitconvert (v4i32 VR128:$src))), (f128 VR128:$src)>;
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def : Pat<(f128 (bitconvert (v8i16 VR128:$src))), (f128 VR128:$src)>;
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def : Pat<(f128 (bitconvert (v16i8 VR128:$src))), (f128 VR128:$src)>;
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def : Pat<(f128 (bitconvert (v2f64 VR128:$src))), (f128 VR128:$src)>;
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def : Pat<(f128 (bitconvert (v4f32 VR128:$src))), (f128 VR128:$src)>;
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def : Pat<(v2i64 (bitconvert (f128 VR128:$src))), (v2i64 VR128:$src)>;
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def : Pat<(v4i32 (bitconvert (f128 VR128:$src))), (v4i32 VR128:$src)>;
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def : Pat<(v8i16 (bitconvert (f128 VR128:$src))), (v8i16 VR128:$src)>;
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def : Pat<(v16i8 (bitconvert (f128 VR128:$src))), (v16i8 VR128:$src)>;
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def : Pat<(v2f64 (bitconvert (f128 VR128:$src))), (v2f64 VR128:$src)>;
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def : Pat<(v4f32 (bitconvert (f128 VR128:$src))), (v4f32 VR128:$src)>;
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// Bitcasts between 256-bit vector types. Return the original type since
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// no instruction is needed for the conversion
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def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
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@ -509,3 +522,68 @@ let Predicates = [HasBWI, HasVLX] in {
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(KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK4:$mask, VK64),
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(i8 60)), (i8 60))>;
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}
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//===----------------------------------------------------------------------===//
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// Extra selection patterns for f128, f128mem
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// movaps is shorter than movdqa. movaps is in SSE and movdqa is in SSE2.
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let Predicates = [NoAVX] in {
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def : Pat<(alignedstore (f128 VR128:$src), addr:$dst),
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(MOVAPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (f128 VR128:$src), addr:$dst),
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(MOVUPSmr addr:$dst, VR128:$src)>;
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def : Pat<(alignedloadf128 addr:$src),
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(MOVAPSrm addr:$src)>;
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def : Pat<(loadf128 addr:$src),
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(MOVUPSrm addr:$src)>;
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}
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let Predicates = [HasAVX, NoVLX] in {
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def : Pat<(alignedstore (f128 VR128:$src), addr:$dst),
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(VMOVAPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (f128 VR128:$src), addr:$dst),
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(VMOVUPSmr addr:$dst, VR128:$src)>;
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def : Pat<(alignedloadf128 addr:$src),
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(VMOVAPSrm addr:$src)>;
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def : Pat<(loadf128 addr:$src),
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(VMOVUPSrm addr:$src)>;
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}
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let Predicates = [HasVLX] in {
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def : Pat<(alignedstore (f128 VR128X:$src), addr:$dst),
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(VMOVAPSZ128mr addr:$dst, VR128X:$src)>;
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def : Pat<(store (f128 VR128X:$src), addr:$dst),
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(VMOVUPSZ128mr addr:$dst, VR128X:$src)>;
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def : Pat<(alignedloadf128 addr:$src),
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(VMOVAPSZ128rm addr:$src)>;
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def : Pat<(loadf128 addr:$src),
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(VMOVUPSZ128rm addr:$src)>;
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}
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// With SSE2 the DAG combiner converts fp logic ops to integer logic ops to
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// reduce patterns.
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let Predicates = [UseSSE1] in {
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// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
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def : Pat<(f128 (X86fand VR128:$src1, (memopf128 addr:$src2))),
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(ANDPSrm VR128:$src1, f128mem:$src2)>;
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def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)),
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(ANDPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(f128 (X86for VR128:$src1, (memopf128 addr:$src2))),
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(ORPSrm VR128:$src1, f128mem:$src2)>;
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def : Pat<(f128 (X86for VR128:$src1, VR128:$src2)),
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(ORPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(f128 (X86fxor VR128:$src1, (memopf128 addr:$src2))),
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(XORPSrm VR128:$src1, f128mem:$src2)>;
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def : Pat<(f128 (X86fxor VR128:$src1, VR128:$src2)),
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(XORPSrr VR128:$src1, VR128:$src2)>;
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}
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@ -1,6 +1,10 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx -enable-legalize-types-checking | FileCheck %s
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; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx -enable-legalize-types-checking | FileCheck %s
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; RUN: llc < %s -O2 -verify-machineinstrs -mtriple=x86_64-linux-android -mattr=+mmx -enable-legalize-types-checking | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -O2 -verify-machineinstrs -mtriple=x86_64-linux-gnu -mattr=+mmx -enable-legalize-types-checking | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -O2 -verify-machineinstrs -mtriple=x86_64-linux-android -mattr=+mmx,avx2 -enable-legalize-types-checking | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -O2 -verify-machineinstrs -mtriple=x86_64-linux-gnu -mattr=+mmx,avx2 -enable-legalize-types-checking | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -O2 -verify-machineinstrs -mtriple=x86_64-linux-android -mattr=+mmx,avx512vl -enable-legalize-types-checking | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -O2 -verify-machineinstrs -mtriple=x86_64-linux-gnu -mattr=+mmx,avx512vl -enable-legalize-types-checking | FileCheck %s --check-prefixes=CHECK,AVX
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; These tests were generated from simplified libm C code.
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; When compiled for the x86_64-linux-android target,
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@ -42,19 +46,33 @@
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; foo(w);
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; }
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define void @TestUnionLD1(fp128 %s, i64 %n) #0 {
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; CHECK-LABEL: TestUnionLD1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
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; CHECK-NEXT: movabsq $281474976710655, %rcx # imm = 0xFFFFFFFFFFFF
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; CHECK-NEXT: andq %rdi, %rcx
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; CHECK-NEXT: movabsq $-281474976710656, %rdx # imm = 0xFFFF000000000000
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; CHECK-NEXT: andq -{{[0-9]+}}(%rsp), %rdx
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; CHECK-NEXT: orq %rcx, %rdx
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; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0
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; CHECK-NEXT: jmp foo # TAILCALL
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; SSE-LABEL: TestUnionLD1:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
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; SSE-NEXT: movq -{{[0-9]+}}(%rsp), %rax
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; SSE-NEXT: movabsq $281474976710655, %rcx # imm = 0xFFFFFFFFFFFF
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; SSE-NEXT: andq %rdi, %rcx
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; SSE-NEXT: movabsq $-281474976710656, %rdx # imm = 0xFFFF000000000000
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; SSE-NEXT: andq -{{[0-9]+}}(%rsp), %rdx
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; SSE-NEXT: orq %rcx, %rdx
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; SSE-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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; SSE-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
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; SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0
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; SSE-NEXT: jmp foo # TAILCALL
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;
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; AVX-LABEL: TestUnionLD1:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
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; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rax
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; AVX-NEXT: movabsq $281474976710655, %rcx # imm = 0xFFFFFFFFFFFF
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; AVX-NEXT: andq %rdi, %rcx
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; AVX-NEXT: movabsq $-281474976710656, %rdx # imm = 0xFFFF000000000000
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; AVX-NEXT: andq -{{[0-9]+}}(%rsp), %rdx
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; AVX-NEXT: orq %rcx, %rdx
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; AVX-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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; AVX-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
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; AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0
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; AVX-NEXT: jmp foo # TAILCALL
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entry:
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%0 = bitcast fp128 %s to i128
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%1 = zext i64 %n to i128
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@ -77,14 +95,23 @@ entry:
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; return w;
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; }
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define fp128 @TestUnionLD2(fp128 %s) #0 {
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; CHECK-LABEL: TestUnionLD2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
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; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq $0, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0
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; CHECK-NEXT: retq
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; SSE-LABEL: TestUnionLD2:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
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; SSE-NEXT: movq -{{[0-9]+}}(%rsp), %rax
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; SSE-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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; SSE-NEXT: movq $0, -{{[0-9]+}}(%rsp)
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; SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: TestUnionLD2:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
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; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rax
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; AVX-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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; AVX-NEXT: movq $0, -{{[0-9]+}}(%rsp)
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; AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = bitcast fp128 %s to i128
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%bf.clear = and i128 %0, -18446744073709551616
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@ -101,25 +128,45 @@ entry:
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; return (z.e < 0.1L) ? 1.0L : 2.0L;
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; }
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define fp128 @TestI128_1(fp128 %x) #0 {
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; CHECK-LABEL: TestI128_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: subq $40, %rsp
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; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
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; CHECK-NEXT: andq {{[0-9]+}}(%rsp), %rax
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; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
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; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq %rcx, (%rsp)
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; CHECK-NEXT: movaps (%rsp), %xmm0
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; CHECK-NEXT: movaps {{.*}}(%rip), %xmm1
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; CHECK-NEXT: callq __lttf2
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: sets %cl
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; CHECK-NEXT: shlq $4, %rcx
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; CHECK-NEXT: movaps {{\.LCPI.*}}(%rcx), %xmm0
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; CHECK-NEXT: addq $40, %rsp
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; CHECK-NEXT: retq
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; SSE-LABEL: TestI128_1:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: subq $40, %rsp
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; SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
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; SSE-NEXT: andq {{[0-9]+}}(%rsp), %rax
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; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx
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; SSE-NEXT: movq %rax, {{[0-9]+}}(%rsp)
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; SSE-NEXT: movq %rcx, (%rsp)
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; SSE-NEXT: movaps (%rsp), %xmm0
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; SSE-NEXT: movaps {{.*}}(%rip), %xmm1
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; SSE-NEXT: callq __lttf2
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; SSE-NEXT: xorl %ecx, %ecx
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; SSE-NEXT: testl %eax, %eax
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; SSE-NEXT: sets %cl
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; SSE-NEXT: shlq $4, %rcx
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; SSE-NEXT: movaps {{\.LCPI.*}}(%rcx), %xmm0
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; SSE-NEXT: addq $40, %rsp
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; SSE-NEXT: retq
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;
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; AVX-LABEL: TestI128_1:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: subq $40, %rsp
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; AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp)
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; AVX-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
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; AVX-NEXT: andq {{[0-9]+}}(%rsp), %rax
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; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rcx
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; AVX-NEXT: movq %rax, {{[0-9]+}}(%rsp)
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; AVX-NEXT: movq %rcx, (%rsp)
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; AVX-NEXT: vmovaps (%rsp), %xmm0
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; AVX-NEXT: vmovaps {{.*}}(%rip), %xmm1
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; AVX-NEXT: callq __lttf2
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; AVX-NEXT: xorl %ecx, %ecx
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; AVX-NEXT: testl %eax, %eax
|
||||
; AVX-NEXT: sets %cl
|
||||
; AVX-NEXT: shlq $4, %rcx
|
||||
; AVX-NEXT: vmovaps {{\.LCPI.*}}(%rcx), %xmm0
|
||||
; AVX-NEXT: addq $40, %rsp
|
||||
; AVX-NEXT: retq
|
||||
entry:
|
||||
%0 = bitcast fp128 %x to i128
|
||||
%bf.clear = and i128 %0, 170141183460469231731687303715884105727
|
||||
|
|
@ -139,15 +186,25 @@ entry:
|
|||
; return (hx & 0x8000) == 0 ? x : y;
|
||||
; }
|
||||
define fp128 @TestI128_2(fp128 %x, fp128 %y) #0 {
|
||||
; CHECK-LABEL: TestI128_2:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: cmpq $0, -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: jns .LBB3_2
|
||||
; CHECK-NEXT: # %bb.1: # %entry
|
||||
; CHECK-NEXT: movaps %xmm1, %xmm0
|
||||
; CHECK-NEXT: .LBB3_2: # %entry
|
||||
; CHECK-NEXT: retq
|
||||
; SSE-LABEL: TestI128_2:
|
||||
; SSE: # %bb.0: # %entry
|
||||
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSE-NEXT: cmpq $0, -{{[0-9]+}}(%rsp)
|
||||
; SSE-NEXT: jns .LBB3_2
|
||||
; SSE-NEXT: # %bb.1: # %entry
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: .LBB3_2: # %entry
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: TestI128_2:
|
||||
; AVX: # %bb.0: # %entry
|
||||
; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: cmpq $0, -{{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: jns .LBB3_2
|
||||
; AVX-NEXT: # %bb.1: # %entry
|
||||
; AVX-NEXT: vmovaps %xmm1, %xmm0
|
||||
; AVX-NEXT: .LBB3_2: # %entry
|
||||
; AVX-NEXT: retq
|
||||
entry:
|
||||
%0 = bitcast fp128 %x to i128
|
||||
%cmp = icmp sgt i128 %0, -1
|
||||
|
|
@ -167,32 +224,59 @@ entry:
|
|||
; return (u.e);
|
||||
; }
|
||||
define fp128 @TestI128_3(fp128 %x, i32* nocapture readnone %ex) #0 {
|
||||
; CHECK-LABEL: TestI128_3:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: subq $56, %rsp
|
||||
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
|
||||
; CHECK-NEXT: movabsq $9223090561878065152, %rcx # imm = 0x7FFF000000000000
|
||||
; CHECK-NEXT: testq %rcx, %rax
|
||||
; CHECK-NEXT: je .LBB4_2
|
||||
; CHECK-NEXT: # %bb.1:
|
||||
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
|
||||
; CHECK-NEXT: jmp .LBB4_3
|
||||
; CHECK-NEXT: .LBB4_2: # %if.then
|
||||
; CHECK-NEXT: movaps {{.*}}(%rip), %xmm1
|
||||
; CHECK-NEXT: callq __multf3
|
||||
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
|
||||
; CHECK-NEXT: movabsq $-9223090561878065153, %rdx # imm = 0x8000FFFFFFFFFFFF
|
||||
; CHECK-NEXT: andq {{[0-9]+}}(%rsp), %rdx
|
||||
; CHECK-NEXT: movabsq $4611123068473966592, %rax # imm = 0x3FFE000000000000
|
||||
; CHECK-NEXT: orq %rdx, %rax
|
||||
; CHECK-NEXT: .LBB4_3: # %if.end
|
||||
; CHECK-NEXT: movq %rcx, (%rsp)
|
||||
; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movaps (%rsp), %xmm0
|
||||
; CHECK-NEXT: addq $56, %rsp
|
||||
; CHECK-NEXT: retq
|
||||
; SSE-LABEL: TestI128_3:
|
||||
; SSE: # %bb.0: # %entry
|
||||
; SSE-NEXT: subq $56, %rsp
|
||||
; SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
|
||||
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax
|
||||
; SSE-NEXT: movabsq $9223090561878065152, %rcx # imm = 0x7FFF000000000000
|
||||
; SSE-NEXT: testq %rcx, %rax
|
||||
; SSE-NEXT: je .LBB4_2
|
||||
; SSE-NEXT: # %bb.1:
|
||||
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx
|
||||
; SSE-NEXT: jmp .LBB4_3
|
||||
; SSE-NEXT: .LBB4_2: # %if.then
|
||||
; SSE-NEXT: movaps {{.*}}(%rip), %xmm1
|
||||
; SSE-NEXT: callq __multf3
|
||||
; SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
|
||||
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx
|
||||
; SSE-NEXT: movabsq $-9223090561878065153, %rdx # imm = 0x8000FFFFFFFFFFFF
|
||||
; SSE-NEXT: andq {{[0-9]+}}(%rsp), %rdx
|
||||
; SSE-NEXT: movabsq $4611123068473966592, %rax # imm = 0x3FFE000000000000
|
||||
; SSE-NEXT: orq %rdx, %rax
|
||||
; SSE-NEXT: .LBB4_3: # %if.end
|
||||
; SSE-NEXT: movq %rcx, (%rsp)
|
||||
; SSE-NEXT: movq %rax, {{[0-9]+}}(%rsp)
|
||||
; SSE-NEXT: movaps (%rsp), %xmm0
|
||||
; SSE-NEXT: addq $56, %rsp
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: TestI128_3:
|
||||
; AVX: # %bb.0: # %entry
|
||||
; AVX-NEXT: subq $56, %rsp
|
||||
; AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rax
|
||||
; AVX-NEXT: movabsq $9223090561878065152, %rcx # imm = 0x7FFF000000000000
|
||||
; AVX-NEXT: testq %rcx, %rax
|
||||
; AVX-NEXT: je .LBB4_2
|
||||
; AVX-NEXT: # %bb.1:
|
||||
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rcx
|
||||
; AVX-NEXT: jmp .LBB4_3
|
||||
; AVX-NEXT: .LBB4_2: # %if.then
|
||||
; AVX-NEXT: vmovaps {{.*}}(%rip), %xmm1
|
||||
; AVX-NEXT: callq __multf3
|
||||
; AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rcx
|
||||
; AVX-NEXT: movabsq $-9223090561878065153, %rdx # imm = 0x8000FFFFFFFFFFFF
|
||||
; AVX-NEXT: andq {{[0-9]+}}(%rsp), %rdx
|
||||
; AVX-NEXT: movabsq $4611123068473966592, %rax # imm = 0x3FFE000000000000
|
||||
; AVX-NEXT: orq %rdx, %rax
|
||||
; AVX-NEXT: .LBB4_3: # %if.end
|
||||
; AVX-NEXT: movq %rcx, (%rsp)
|
||||
; AVX-NEXT: movq %rax, {{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: vmovaps (%rsp), %xmm0
|
||||
; AVX-NEXT: addq $56, %rsp
|
||||
; AVX-NEXT: retq
|
||||
entry:
|
||||
%0 = bitcast fp128 %x to i128
|
||||
%bf.cast = and i128 %0, 170135991163610696904058773219554885632
|
||||
|
|
@ -223,18 +307,31 @@ if.end: ; preds = %if.then, %entry
|
|||
; return x + df;
|
||||
; }
|
||||
define fp128 @TestI128_4(fp128 %x) #0 {
|
||||
; CHECK-LABEL: TestI128_4:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: subq $40, %rsp
|
||||
; CHECK-NEXT: movaps %xmm0, %xmm1
|
||||
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
|
||||
; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movq $0, (%rsp)
|
||||
; CHECK-NEXT: movaps (%rsp), %xmm0
|
||||
; CHECK-NEXT: callq __addtf3
|
||||
; CHECK-NEXT: addq $40, %rsp
|
||||
; CHECK-NEXT: retq
|
||||
; SSE-LABEL: TestI128_4:
|
||||
; SSE: # %bb.0: # %entry
|
||||
; SSE-NEXT: subq $40, %rsp
|
||||
; SSE-NEXT: movaps %xmm0, %xmm1
|
||||
; SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
|
||||
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax
|
||||
; SSE-NEXT: movq %rax, {{[0-9]+}}(%rsp)
|
||||
; SSE-NEXT: movq $0, (%rsp)
|
||||
; SSE-NEXT: movaps (%rsp), %xmm0
|
||||
; SSE-NEXT: callq __addtf3
|
||||
; SSE-NEXT: addq $40, %rsp
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: TestI128_4:
|
||||
; AVX: # %bb.0: # %entry
|
||||
; AVX-NEXT: subq $40, %rsp
|
||||
; AVX-NEXT: vmovaps %xmm0, %xmm1
|
||||
; AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rax
|
||||
; AVX-NEXT: movq %rax, {{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: movq $0, (%rsp)
|
||||
; AVX-NEXT: vmovaps (%rsp), %xmm0
|
||||
; AVX-NEXT: callq __addtf3
|
||||
; AVX-NEXT: addq $40, %rsp
|
||||
; AVX-NEXT: retq
|
||||
entry:
|
||||
%0 = bitcast fp128 %x to i128
|
||||
%bf.clear = and i128 %0, -18446744073709551616
|
||||
|
|
@ -271,18 +368,31 @@ entry:
|
|||
}
|
||||
|
||||
define fp128 @acosl(fp128 %x) #0 {
|
||||
; CHECK-LABEL: acosl:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: subq $40, %rsp
|
||||
; CHECK-NEXT: movaps %xmm0, %xmm1
|
||||
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
|
||||
; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movq $0, (%rsp)
|
||||
; CHECK-NEXT: movaps (%rsp), %xmm0
|
||||
; CHECK-NEXT: callq __addtf3
|
||||
; CHECK-NEXT: addq $40, %rsp
|
||||
; CHECK-NEXT: retq
|
||||
; SSE-LABEL: acosl:
|
||||
; SSE: # %bb.0: # %entry
|
||||
; SSE-NEXT: subq $40, %rsp
|
||||
; SSE-NEXT: movaps %xmm0, %xmm1
|
||||
; SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
|
||||
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax
|
||||
; SSE-NEXT: movq %rax, {{[0-9]+}}(%rsp)
|
||||
; SSE-NEXT: movq $0, (%rsp)
|
||||
; SSE-NEXT: movaps (%rsp), %xmm0
|
||||
; SSE-NEXT: callq __addtf3
|
||||
; SSE-NEXT: addq $40, %rsp
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: acosl:
|
||||
; AVX: # %bb.0: # %entry
|
||||
; AVX-NEXT: subq $40, %rsp
|
||||
; AVX-NEXT: vmovaps %xmm0, %xmm1
|
||||
; AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rax
|
||||
; AVX-NEXT: movq %rax, {{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: movq $0, (%rsp)
|
||||
; AVX-NEXT: vmovaps (%rsp), %xmm0
|
||||
; AVX-NEXT: callq __addtf3
|
||||
; AVX-NEXT: addq $40, %rsp
|
||||
; AVX-NEXT: retq
|
||||
entry:
|
||||
%0 = bitcast fp128 %x to i128
|
||||
%bf.clear = and i128 %0, -18446744073709551616
|
||||
|
|
@ -293,15 +403,25 @@ entry:
|
|||
|
||||
; Compare i128 values and check i128 constants.
|
||||
define fp128 @TestComp(fp128 %x, fp128 %y) #0 {
|
||||
; CHECK-LABEL: TestComp:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: cmpq $0, -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: jns .LBB8_2
|
||||
; CHECK-NEXT: # %bb.1: # %entry
|
||||
; CHECK-NEXT: movaps %xmm1, %xmm0
|
||||
; CHECK-NEXT: .LBB8_2: # %entry
|
||||
; CHECK-NEXT: retq
|
||||
; SSE-LABEL: TestComp:
|
||||
; SSE: # %bb.0: # %entry
|
||||
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSE-NEXT: cmpq $0, -{{[0-9]+}}(%rsp)
|
||||
; SSE-NEXT: jns .LBB8_2
|
||||
; SSE-NEXT: # %bb.1: # %entry
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: .LBB8_2: # %entry
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: TestComp:
|
||||
; AVX: # %bb.0: # %entry
|
||||
; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: cmpq $0, -{{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: jns .LBB8_2
|
||||
; AVX-NEXT: # %bb.1: # %entry
|
||||
; AVX-NEXT: vmovaps %xmm1, %xmm0
|
||||
; AVX-NEXT: .LBB8_2: # %entry
|
||||
; AVX-NEXT: retq
|
||||
entry:
|
||||
%0 = bitcast fp128 %x to i128
|
||||
%cmp = icmp sgt i128 %0, -1
|
||||
|
|
@ -313,10 +433,15 @@ declare void @foo(fp128) #1
|
|||
|
||||
; Test logical operations on fp128 values.
|
||||
define fp128 @TestFABS_LD(fp128 %x) #0 {
|
||||
; CHECK-LABEL: TestFABS_LD:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
; SSE-LABEL: TestFABS_LD:
|
||||
; SSE: # %bb.0: # %entry
|
||||
; SSE-NEXT: andps {{.*}}(%rip), %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: TestFABS_LD:
|
||||
; AVX: # %bb.0: # %entry
|
||||
; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
entry:
|
||||
%call = tail call fp128 @fabsl(fp128 %x) #2
|
||||
ret fp128 %call
|
||||
|
|
@ -328,43 +453,79 @@ declare fp128 @copysignl(fp128, fp128) #1
|
|||
|
||||
; Test more complicated logical operations generated from copysignl.
|
||||
define void @TestCopySign({ fp128, fp128 }* noalias nocapture sret %agg.result, { fp128, fp128 }* byval nocapture readonly align 16 %z) #0 {
|
||||
; CHECK-LABEL: TestCopySign:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: pushq %rbp
|
||||
; CHECK-NEXT: pushq %rbx
|
||||
; CHECK-NEXT: subq $40, %rsp
|
||||
; CHECK-NEXT: movq %rdi, %rbx
|
||||
; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm0
|
||||
; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1
|
||||
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
|
||||
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
|
||||
; CHECK-NEXT: callq __gttf2
|
||||
; CHECK-NEXT: movl %eax, %ebp
|
||||
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
|
||||
; CHECK-NEXT: movaps %xmm0, %xmm1
|
||||
; CHECK-NEXT: callq __subtf3
|
||||
; CHECK-NEXT: testl %ebp, %ebp
|
||||
; CHECK-NEXT: jle .LBB10_1
|
||||
; CHECK-NEXT: # %bb.2: # %if.then
|
||||
; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
|
||||
; CHECK-NEXT: movaps %xmm0, %xmm1
|
||||
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
|
||||
; CHECK-NEXT: movaps %xmm1, %xmm2
|
||||
; CHECK-NEXT: jmp .LBB10_3
|
||||
; CHECK-NEXT: .LBB10_1:
|
||||
; CHECK-NEXT: movaps (%rsp), %xmm2 # 16-byte Reload
|
||||
; CHECK-NEXT: .LBB10_3: # %cleanup
|
||||
; CHECK-NEXT: movaps {{.*}}(%rip), %xmm1
|
||||
; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
|
||||
; CHECK-NEXT: andps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
|
||||
; CHECK-NEXT: orps %xmm1, %xmm0
|
||||
; CHECK-NEXT: movaps %xmm2, (%rbx)
|
||||
; CHECK-NEXT: movaps %xmm0, 16(%rbx)
|
||||
; CHECK-NEXT: movq %rbx, %rax
|
||||
; CHECK-NEXT: addq $40, %rsp
|
||||
; CHECK-NEXT: popq %rbx
|
||||
; CHECK-NEXT: popq %rbp
|
||||
; CHECK-NEXT: retq
|
||||
; SSE-LABEL: TestCopySign:
|
||||
; SSE: # %bb.0: # %entry
|
||||
; SSE-NEXT: pushq %rbp
|
||||
; SSE-NEXT: pushq %rbx
|
||||
; SSE-NEXT: subq $40, %rsp
|
||||
; SSE-NEXT: movq %rdi, %rbx
|
||||
; SSE-NEXT: movaps {{[0-9]+}}(%rsp), %xmm0
|
||||
; SSE-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1
|
||||
; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
|
||||
; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
|
||||
; SSE-NEXT: callq __gttf2
|
||||
; SSE-NEXT: movl %eax, %ebp
|
||||
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
|
||||
; SSE-NEXT: movaps %xmm0, %xmm1
|
||||
; SSE-NEXT: callq __subtf3
|
||||
; SSE-NEXT: testl %ebp, %ebp
|
||||
; SSE-NEXT: jle .LBB10_1
|
||||
; SSE-NEXT: # %bb.2: # %if.then
|
||||
; SSE-NEXT: movaps %xmm0, %xmm1
|
||||
; SSE-NEXT: andps {{.*}}(%rip), %xmm1
|
||||
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
|
||||
; SSE-NEXT: jmp .LBB10_3
|
||||
; SSE-NEXT: .LBB10_1:
|
||||
; SSE-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
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; SSE-NEXT: .LBB10_3: # %cleanup
|
||||
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
|
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; SSE-NEXT: andps {{.*}}(%rip), %xmm2
|
||||
; SSE-NEXT: andps {{.*}}(%rip), %xmm0
|
||||
; SSE-NEXT: orps %xmm2, %xmm0
|
||||
; SSE-NEXT: movaps %xmm1, (%rbx)
|
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; SSE-NEXT: movaps %xmm0, 16(%rbx)
|
||||
; SSE-NEXT: movq %rbx, %rax
|
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; SSE-NEXT: addq $40, %rsp
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; SSE-NEXT: popq %rbx
|
||||
; SSE-NEXT: popq %rbp
|
||||
; SSE-NEXT: retq
|
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;
|
||||
; AVX-LABEL: TestCopySign:
|
||||
; AVX: # %bb.0: # %entry
|
||||
; AVX-NEXT: pushq %rbp
|
||||
; AVX-NEXT: pushq %rbx
|
||||
; AVX-NEXT: subq $40, %rsp
|
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; AVX-NEXT: movq %rdi, %rbx
|
||||
; AVX-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0
|
||||
; AVX-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm1
|
||||
; AVX-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
|
||||
; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
|
||||
; AVX-NEXT: callq __gttf2
|
||||
; AVX-NEXT: movl %eax, %ebp
|
||||
; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
|
||||
; AVX-NEXT: vmovaps %xmm0, %xmm1
|
||||
; AVX-NEXT: callq __subtf3
|
||||
; AVX-NEXT: testl %ebp, %ebp
|
||||
; AVX-NEXT: jle .LBB10_1
|
||||
; AVX-NEXT: # %bb.2: # %if.then
|
||||
; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm1
|
||||
; AVX-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
|
||||
; AVX-NEXT: vmovaps %xmm1, %xmm2
|
||||
; AVX-NEXT: jmp .LBB10_3
|
||||
; AVX-NEXT: .LBB10_1:
|
||||
; AVX-NEXT: vmovaps (%rsp), %xmm2 # 16-byte Reload
|
||||
; AVX-NEXT: .LBB10_3: # %cleanup
|
||||
; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
|
||||
; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
|
||||
; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
|
||||
; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vmovaps %xmm2, (%rbx)
|
||||
; AVX-NEXT: vmovaps %xmm0, 16(%rbx)
|
||||
; AVX-NEXT: movq %rbx, %rax
|
||||
; AVX-NEXT: addq $40, %rsp
|
||||
; AVX-NEXT: popq %rbx
|
||||
; AVX-NEXT: popq %rbp
|
||||
; AVX-NEXT: retq
|
||||
entry:
|
||||
%z.realp = getelementptr inbounds { fp128, fp128 }, { fp128, fp128 }* %z, i64 0, i32 0
|
||||
%z.real = load fp128, fp128* %z.realp, align 16
|
||||
|
|
|
|||
Loading…
Reference in New Issue