forked from OSchip/llvm-project
[NFC][CodeGen] Use ArrayRef in TargetLowering functions
This patch is similar to D122557, adding an `ArrayRef` version for `setOperationAction`, `setLoadExtAction`, `setCondCodeAction`, `setLibcallName`. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D123467
This commit is contained in:
Shao-Ce SUN
parent
528aa09010
commit
e90110e696
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@ -2249,21 +2249,33 @@ protected:
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/// Indicate that the specified operation does not work with the specified
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/// type and indicate what to do about it. Note that VT may refer to either
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/// the type of a result or that of an operand of Op.
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void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action) {
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assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
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OpActions[(unsigned)VT.SimpleTy][Op] = Action;
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void setOperationAction(ArrayRef<unsigned> Ops, MVT VT,
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LegalizeAction Action) {
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for (auto Op : Ops) {
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assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
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OpActions[(unsigned)VT.SimpleTy][Op] = Action;
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}
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}
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void setOperationAction(ArrayRef<unsigned> Ops, ArrayRef<MVT> VTs,
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LegalizeAction Action) {
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for (auto VT : VTs)
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setOperationAction(Ops, VT, Action);
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}
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/// Indicate that the specified load with extension does not work with the
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/// specified type and indicate what to do about it.
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void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
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void setLoadExtAction(ArrayRef<unsigned> ExtTypes, MVT ValVT, MVT MemVT,
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LegalizeAction Action) {
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assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
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MemVT.isValid() && "Table isn't big enough!");
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assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
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unsigned Shift = 4 * ExtType;
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LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
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LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
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for (auto ExtType : ExtTypes) {
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assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
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MemVT.isValid() && "Table isn't big enough!");
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assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
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unsigned Shift = 4 * ExtType;
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LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &=
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~((uint16_t)0xF << Shift);
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LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action
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<< Shift;
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}
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}
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/// Indicate that the specified truncating store does not work with the
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@ -2313,17 +2325,24 @@ protected:
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/// Indicate that the specified condition code is or isn't supported on the
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/// target and indicate what to do about it.
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void setCondCodeAction(ISD::CondCode CC, MVT VT,
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void setCondCodeAction(ArrayRef<ISD::CondCode> CCs, MVT VT,
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LegalizeAction Action) {
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assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
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"Table isn't big enough!");
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assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
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/// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
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/// value and the upper 29 bits index into the second dimension of the array
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/// to select what 32-bit value to use.
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uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
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CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
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CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
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for (auto CC : CCs) {
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assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
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"Table isn't big enough!");
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assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
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/// The lower 3 bits of the SimpleTy index into Nth 4bit set from the
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/// 32-bit value and the upper 29 bits index into the second dimension of
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/// the array to select what 32-bit value to use.
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uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
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CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
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CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
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}
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}
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void setCondCodeAction(ArrayRef<ISD::CondCode> CCs, ArrayRef<MVT> VTs,
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LegalizeAction Action) {
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for (auto VT : VTs)
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setCondCodeAction(CCs, VT, Action);
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}
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/// If Opc/OrigVT is specified as being promoted, the promotion code defaults
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@ -2344,14 +2363,11 @@ protected:
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/// Targets should invoke this method for each target independent node that
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/// they want to provide a custom DAG combiner for by implementing the
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/// PerformDAGCombine virtual method.
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void setTargetDAGCombine(ISD::NodeType NT) {
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assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
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TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
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}
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void setTargetDAGCombine(ArrayRef<ISD::NodeType> NTs) {
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for (auto NT : NTs)
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setTargetDAGCombine(NT);
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for (auto NT : NTs) {
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assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
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TargetDAGCombineArray[NT >> 3] |= 1 << (NT & 7);
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}
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}
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/// Set the target's minimum function alignment.
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@ -2979,8 +2995,9 @@ public:
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//
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/// Rename the default libcall routine name for the specified libcall.
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void setLibcallName(RTLIB::Libcall Call, const char *Name) {
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LibcallRoutineNames[Call] = Name;
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void setLibcallName(ArrayRef<RTLIB::Libcall> Calls, const char *Name) {
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for (auto Call : Calls)
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LibcallRoutineNames[Call] = Name;
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}
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/// Get the libcall routine name for the specified libcall.
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@ -762,91 +762,62 @@ void TargetLoweringBase::initActions() {
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setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
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// These operations default to expand.
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setOperationAction(ISD::FGETSIGN, VT, Expand);
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setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
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setOperationAction(ISD::FMINNUM, VT, Expand);
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setOperationAction(ISD::FMAXNUM, VT, Expand);
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setOperationAction(ISD::FMINNUM_IEEE, VT, Expand);
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setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand);
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setOperationAction(ISD::FMINIMUM, VT, Expand);
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setOperationAction(ISD::FMAXIMUM, VT, Expand);
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setOperationAction(ISD::FMAD, VT, Expand);
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setOperationAction(ISD::SMIN, VT, Expand);
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setOperationAction(ISD::SMAX, VT, Expand);
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setOperationAction(ISD::UMIN, VT, Expand);
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setOperationAction(ISD::UMAX, VT, Expand);
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setOperationAction(ISD::ABS, VT, Expand);
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setOperationAction(ISD::FSHL, VT, Expand);
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setOperationAction(ISD::FSHR, VT, Expand);
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setOperationAction(ISD::SADDSAT, VT, Expand);
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setOperationAction(ISD::UADDSAT, VT, Expand);
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setOperationAction(ISD::SSUBSAT, VT, Expand);
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setOperationAction(ISD::USUBSAT, VT, Expand);
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setOperationAction(ISD::SSHLSAT, VT, Expand);
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setOperationAction(ISD::USHLSAT, VT, Expand);
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setOperationAction(ISD::SMULFIX, VT, Expand);
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setOperationAction(ISD::SMULFIXSAT, VT, Expand);
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setOperationAction(ISD::UMULFIX, VT, Expand);
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setOperationAction(ISD::UMULFIXSAT, VT, Expand);
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setOperationAction(ISD::SDIVFIX, VT, Expand);
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setOperationAction(ISD::SDIVFIXSAT, VT, Expand);
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setOperationAction(ISD::UDIVFIX, VT, Expand);
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setOperationAction(ISD::UDIVFIXSAT, VT, Expand);
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setOperationAction(ISD::FP_TO_SINT_SAT, VT, Expand);
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setOperationAction(ISD::FP_TO_UINT_SAT, VT, Expand);
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setOperationAction({ISD::FGETSIGN, ISD::CONCAT_VECTORS,
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ISD::FMINNUM, ISD::FMAXNUM,
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ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
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ISD::FMINIMUM, ISD::FMAXIMUM,
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ISD::FMAD, ISD::SMIN,
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ISD::SMAX, ISD::UMIN,
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ISD::UMAX, ISD::ABS,
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ISD::FSHL, ISD::FSHR,
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ISD::SADDSAT, ISD::UADDSAT,
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ISD::SSUBSAT, ISD::USUBSAT,
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ISD::SSHLSAT, ISD::USHLSAT,
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ISD::SMULFIX, ISD::SMULFIXSAT,
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ISD::UMULFIX, ISD::UMULFIXSAT,
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ISD::SDIVFIX, ISD::SDIVFIXSAT,
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ISD::UDIVFIX, ISD::UDIVFIXSAT,
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ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT},
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VT, Expand);
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// Overflow operations default to expand
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setOperationAction(ISD::SADDO, VT, Expand);
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setOperationAction(ISD::SSUBO, VT, Expand);
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setOperationAction(ISD::UADDO, VT, Expand);
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setOperationAction(ISD::USUBO, VT, Expand);
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setOperationAction(ISD::SMULO, VT, Expand);
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setOperationAction(ISD::UMULO, VT, Expand);
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setOperationAction({ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO,
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ISD::SMULO, ISD::UMULO},
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VT, Expand);
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// ADDCARRY operations default to expand
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setOperationAction(ISD::ADDCARRY, VT, Expand);
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setOperationAction(ISD::SUBCARRY, VT, Expand);
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setOperationAction(ISD::SETCCCARRY, VT, Expand);
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setOperationAction(ISD::SADDO_CARRY, VT, Expand);
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setOperationAction(ISD::SSUBO_CARRY, VT, Expand);
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setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY, ISD::SETCCCARRY,
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ISD::SADDO_CARRY, ISD::SSUBO_CARRY},
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VT, Expand);
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// ADDC/ADDE/SUBC/SUBE default to expand.
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setOperationAction(ISD::ADDC, VT, Expand);
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setOperationAction(ISD::ADDE, VT, Expand);
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setOperationAction(ISD::SUBC, VT, Expand);
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setOperationAction(ISD::SUBE, VT, Expand);
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setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT,
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Expand);
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// Halving adds
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setOperationAction(ISD::AVGFLOORS, VT, Expand);
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setOperationAction(ISD::AVGFLOORU, VT, Expand);
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setOperationAction(ISD::AVGCEILS, VT, Expand);
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setOperationAction(ISD::AVGCEILU, VT, Expand);
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setOperationAction(
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{ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT,
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Expand);
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// Absolute difference
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setOperationAction(ISD::ABDS, VT, Expand);
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setOperationAction(ISD::ABDU, VT, Expand);
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setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Expand);
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// These default to Expand so they will be expanded to CTLZ/CTTZ by default.
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setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
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setOperationAction({ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT,
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Expand);
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setOperationAction(ISD::BITREVERSE, VT, Expand);
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setOperationAction(ISD::PARITY, VT, Expand);
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setOperationAction({ISD::BITREVERSE, ISD::PARITY}, VT, Expand);
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// These library functions default to expand.
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setOperationAction(ISD::FROUND, VT, Expand);
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setOperationAction(ISD::FROUNDEVEN, VT, Expand);
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setOperationAction(ISD::FPOWI, VT, Expand);
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setOperationAction({ISD::FROUND, ISD::FROUNDEVEN, ISD::FPOWI}, VT, Expand);
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// These operations default to expand for vector types.
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if (VT.isVector()) {
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setOperationAction(ISD::FCOPYSIGN, VT, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
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setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
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setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
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setOperationAction(ISD::SPLAT_VECTOR, VT, Expand);
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}
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if (VT.isVector())
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setOperationAction({ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG,
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ISD::ANY_EXTEND_VECTOR_INREG,
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ISD::SIGN_EXTEND_VECTOR_INREG,
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ISD::ZERO_EXTEND_VECTOR_INREG, ISD::SPLAT_VECTOR},
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VT, Expand);
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// Constrained floating-point operations default to expand.
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#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
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@ -857,21 +828,13 @@ void TargetLoweringBase::initActions() {
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setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand);
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// Vector reduction default to expand.
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setOperationAction(ISD::VECREDUCE_FADD, VT, Expand);
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setOperationAction(ISD::VECREDUCE_FMUL, VT, Expand);
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setOperationAction(ISD::VECREDUCE_ADD, VT, Expand);
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setOperationAction(ISD::VECREDUCE_MUL, VT, Expand);
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setOperationAction(ISD::VECREDUCE_AND, VT, Expand);
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setOperationAction(ISD::VECREDUCE_OR, VT, Expand);
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setOperationAction(ISD::VECREDUCE_XOR, VT, Expand);
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setOperationAction(ISD::VECREDUCE_SMAX, VT, Expand);
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setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand);
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setOperationAction(ISD::VECREDUCE_UMAX, VT, Expand);
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setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand);
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setOperationAction(ISD::VECREDUCE_FMAX, VT, Expand);
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setOperationAction(ISD::VECREDUCE_FMIN, VT, Expand);
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setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Expand);
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setOperationAction(ISD::VECREDUCE_SEQ_FMUL, VT, Expand);
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setOperationAction(
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{ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD,
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ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR,
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ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN,
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ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX,
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ISD::VECREDUCE_FMIN, ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL},
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VT, Expand);
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// Named vector shuffles default to expand.
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setOperationAction(ISD::VECTOR_SPLICE, VT, Expand);
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@ -886,30 +849,16 @@ void TargetLoweringBase::initActions() {
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// ConstantFP nodes default to expand. Targets can either change this to
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// Legal, in which case all fp constants are legal, or use isFPImmLegal()
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// to optimize expansions for certain constants.
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setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
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setOperationAction(ISD::ConstantFP,
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{MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},
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Expand);
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// These library functions default to expand.
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for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
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setOperationAction(ISD::FCBRT, VT, Expand);
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setOperationAction(ISD::FLOG , VT, Expand);
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setOperationAction(ISD::FLOG2, VT, Expand);
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setOperationAction(ISD::FLOG10, VT, Expand);
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setOperationAction(ISD::FEXP , VT, Expand);
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setOperationAction(ISD::FEXP2, VT, Expand);
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setOperationAction(ISD::FFLOOR, VT, Expand);
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setOperationAction(ISD::FNEARBYINT, VT, Expand);
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setOperationAction(ISD::FCEIL, VT, Expand);
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setOperationAction(ISD::FRINT, VT, Expand);
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setOperationAction(ISD::FTRUNC, VT, Expand);
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setOperationAction(ISD::LROUND, VT, Expand);
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setOperationAction(ISD::LLROUND, VT, Expand);
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setOperationAction(ISD::LRINT, VT, Expand);
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setOperationAction(ISD::LLRINT, VT, Expand);
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}
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setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP,
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ISD::FEXP2, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL,
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ISD::FRINT, ISD::FTRUNC, ISD::LROUND, ISD::LLROUND,
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ISD::LRINT, ISD::LLRINT},
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{MVT::f32, MVT::f64, MVT::f128}, Expand);
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// Default ISD::TRAP to expand (which turns it into abort).
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setOperationAction(ISD::TRAP, MVT::Other, Expand);
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