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R600: Change operation action from Custom to Expand for SETCC 

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176697
This commit is contained in:
Tom Stellard 2013-03-08 15:37:05 +00:00
parent b852af5dc4
commit e8f9f2877b
3 changed files with 27 additions and 49 deletions
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47
llvm/lib/Target/R600/R600ISelLowering.cpp
View File

@ -65,8 +65,8 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
setOperationAction(ISD::SETCC, MVT::i32, Custom);
setOperationAction(ISD::SETCC, MVT::f32, Custom);
setOperationAction(ISD::SETCC, MVT::i32, Expand);
setOperationAction(ISD::SETCC, MVT::f32, Expand);
setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
setOperationAction(ISD::SELECT, MVT::i32, Custom);
@ -316,7 +316,6 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
case ISD::ROTL: return LowerROTL(Op, DAG);
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
case ISD::SELECT: return LowerSELECT(Op, DAG);
case ISD::SETCC: return LowerSETCC(Op, DAG);
case ISD::STORE: return LowerSTORE(Op, DAG);
case ISD::LOAD: return LowerLOAD(Op, DAG);
case ISD::FPOW: return LowerFPOW(Op, DAG);
@ -704,48 +703,6 @@ SDValue R600TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
DAG.getCondCode(ISD::SETNE));
}
SDValue R600TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
SDValue Cond;
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
SDValue CC = Op.getOperand(2);
DebugLoc DL = Op.getDebugLoc();
assert(Op.getValueType() == MVT::i32);
if (LHS.getValueType() == MVT::i32) {
Cond = DAG.getNode(
ISD::SELECT_CC,
Op.getDebugLoc(),
MVT::i32,
LHS, RHS,
DAG.getConstant(-1, MVT::i32),
DAG.getConstant(0, MVT::i32),
CC);
} else if (LHS.getValueType() == MVT::f32) {
Cond = DAG.getNode(
ISD::SELECT_CC,
Op.getDebugLoc(),
MVT::f32,
LHS, RHS,
DAG.getConstantFP(1.0f, MVT::f32),
DAG.getConstantFP(0.0f, MVT::f32),
CC);
Cond = DAG.getNode(
ISD::FP_TO_SINT,
DL,
MVT::i32,
Cond);
} else {
assert(0 && "Not valid type for set_cc");
}
Cond = DAG.getNode(
ISD::AND,
DL,
MVT::i32,
DAG.getConstant(1, MVT::i32),
Cond);
return Cond;
}
/// LLVM generates byte-addresed pointers. For indirect addressing, we need to
/// convert these pointers to a register index. Each register holds
/// 16 bytes, (4 x 32bit sub-register), but we need to take into account the

1
llvm/lib/Target/R600/R600ISelLowering.h
View File

@ -59,7 +59,6 @@ private:
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFPOW(SDValue Op, SelectionDAG &DAG) const;

28
llvm/test/CodeGen/R600/fcmp.ll
View File

@ -1,8 +1,9 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; CHECK: @fcmp_sext
; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @test(i32 addrspace(1)* %out, float addrspace(1)* %in) {
define void @fcmp_sext(i32 addrspace(1)* %out, float addrspace(1)* %in) {
entry:
%0 = load float addrspace(1)* %in
%arrayidx1 = getelementptr inbounds float addrspace(1)* %in, i32 1
@ -12,3 +13,24 @@ entry:
store i32 %sext, i32 addrspace(1)* %out
ret void
}
; This test checks that a setcc node with f32 operands is lowered to a
; SET* instruction.
; CHECK: @fcmp_br
; CHECK: SET{{[N]*}}E T{{[0-9]+\.[XYZW], [a-zA-Z0-9, .]+}}(5.0
define void @fcmp_br(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp oeq float %in, 5.0
br i1 %0, label %IF, label %ENDIF
IF:
%1 = getelementptr i32 addrspace(1)* %out, i32 1
store i32 0, i32 addrspace(1)* %1
br label %ENDIF
ENDIF:
store i32 0, i32 addrspace(1)* %out
ret void
}