forked from OSchip/llvm-project
[DAG] Promote ADDCARRY / SUBCARRY
Add missing case that was not implemented yet. Differential Revision: https://reviews.llvm.org/D38942 llvm-svn: 320567
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@ -772,7 +772,30 @@ SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
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SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo) {
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if (ResNo == 1)
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return PromoteIntRes_Overflow(N);
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llvm_unreachable("Not implemented");
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// We need to sign-extend the operands so the carry value computed by the
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// wide operation will be equivalent to the carry value computed by the
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// narrow operation.
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// An ADDCARRY can generate carry only if any of the operands has its
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// most significant bit set. Sign extension propagates the most significant
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// bit into the higher bits which means the extra bit that the narrow
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// addition would need (i.e. the carry) will be propagated through the higher
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// bits of the wide addition.
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// A SUBCARRY can generate borrow only if LHS < RHS and this property will be
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// preserved by sign extension.
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SDValue LHS = SExtPromotedInteger(N->getOperand(0));
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SDValue RHS = SExtPromotedInteger(N->getOperand(1));
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EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(1)};
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// Do the arithmetic in the wide type.
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SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N), DAG.getVTList(ValueVTs),
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LHS, RHS, N->getOperand(2));
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// Update the users of the original carry/borrow value.
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ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
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return SDValue(Res.getNode(), 0);
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
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@ -0,0 +1,60 @@
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; RUN: llc -O2 -mtriple armv7a < %s | FileCheck --check-prefix=ARM %s
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; RUN: llc -O2 -mtriple thumbv6m < %s | FileCheck --check-prefix=THUMB1 %s
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; RUN: llc -O2 -mtriple thumbv8m.base < %s | FileCheck --check-prefix=THUMB1 %s
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; RUN: llc -O2 -mtriple thumbv7a < %s | FileCheck --check-prefix=THUMB %s
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; RUN: llc -O2 -mtriple thumbv8m.main < %s | FileCheck --check-prefix=THUMB %s
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define void @fn1(i32 %a, i32 %b, i32 %c) local_unnamed_addr #0 {
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entry:
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; ARM: rsb r2, r2, #1
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; ARM: adds r0, r1, r0
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; ARM: movw r1, #65535
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; ARM: sxth r2, r2
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; ARM: adc r0, r2, #0
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; ARM: tst r0, r1
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; ARM: bxeq lr
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; ARM: .LBB0_1:
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; ARM: b .LBB0_1
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; THUMB1: movs r3, #1
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; THUMB1: subs r2, r3, r2
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; THUMB1: sxth r2, r2
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; THUMB1: movs r3, #0
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; THUMB1: adds r0, r1, r0
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; THUMB1: adcs r3, r2
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; THUMB1: lsls r0, r3, #16
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; THUMB1: beq .LBB0_2
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; THUMB1: .LBB0_1:
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; THUMB1: b .LBB0_1
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; THUMB: rsb.w r2, r2, #1
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; THUMB: adds r0, r0, r1
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; THUMB: sxth r2, r2
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; THUMB: adc r0, r2, #0
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; THUMB: lsls r0, r0, #16
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; THUMB: it eq
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; THUMB: bxeq lr
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; THUMB: .LBB0_1:
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; THUMB: b .LBB0_1
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%add = add i32 %b, %a
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%cmp = icmp ult i32 %add, %b
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%conv = zext i1 %cmp to i32
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%sub = sub i32 1, %c
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%add1 = add i32 %sub, %conv
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%conv2 = trunc i32 %add1 to i16
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%tobool = icmp eq i16 %conv2, 0
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br i1 %tobool, label %if.end, label %for.cond.preheader
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for.cond.preheader: ; preds = %entry
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br label %for.cond
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for.cond: ; preds = %for.cond.preheader, %for.cond
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br label %for.cond
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if.end: ; preds = %entry
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ret void
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}
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