forked from OSchip/llvm-project
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
llvm-svn: 27923
This commit is contained in:
Evan Cheng
parent
cc47ab3305
commit
e8b5180044
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@ -1687,11 +1687,12 @@ bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
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return true;
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}
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/// isMOVSMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVS{S|D}.
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static bool isMOVSMask(std::vector<SDOperand> &N) {
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/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSS,
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/// MOVSD, and MOVD, i.e. setting the lowest element.
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static bool isMOVLMask(std::vector<SDOperand> &N) {
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unsigned NumElems = N.size();
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if (NumElems != 2 && NumElems != 4)
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if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
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return false;
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if (!isUndefOrEqual(N[0], NumElems))
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@ -1706,18 +1707,18 @@ static bool isMOVSMask(std::vector<SDOperand> &N) {
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return true;
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}
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bool X86::isMOVSMask(SDNode *N) {
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bool X86::isMOVLMask(SDNode *N) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR);
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std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
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return ::isMOVSMask(Ops);
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return ::isMOVLMask(Ops);
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}
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/// isCommutedMOVS - Returns true if the shuffle mask is except the reverse
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/// of what x86 movs want. X86 movs requires the lowest element to be lowest
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/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
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/// of what x86 movss want. X86 movs requires the lowest element to be lowest
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/// element of vector 2 and the other elements to come from vector 1 in order.
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static bool isCommutedMOVS(std::vector<SDOperand> &Ops, bool V2IsSplat = false) {
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static bool isCommutedMOVL(std::vector<SDOperand> &Ops, bool V2IsSplat = false) {
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unsigned NumElems = Ops.size();
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if (NumElems != 2 && NumElems != 4)
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if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
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return false;
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if (!isUndefOrEqual(Ops[0], 0))
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@ -1737,10 +1738,10 @@ static bool isCommutedMOVS(std::vector<SDOperand> &Ops, bool V2IsSplat = false)
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return true;
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}
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static bool isCommutedMOVS(SDNode *N, bool V2IsSplat = false) {
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static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR);
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std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
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return isCommutedMOVS(Ops);
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return isCommutedMOVL(Ops, V2IsSplat);
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}
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/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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@ -2055,9 +2056,9 @@ static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
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return Mask;
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}
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/// getMOVSMask - Returns a vector_shuffle mask for an movs{s|d} operation
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/// of specified width.
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static SDOperand getMOVSMask(unsigned NumElems, SelectionDAG &DAG) {
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/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
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/// operation of specified width.
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static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
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MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
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MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
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@ -2095,30 +2096,63 @@ static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
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return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
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}
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/// getZeroVector - Returns a vector of specified type with all zero elements.
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///
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static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
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assert(MVT::isVector(VT) && "Expected a vector type");
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unsigned NumElems = getVectorNumElements(VT);
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MVT::ValueType EVT = MVT::getVectorBaseType(VT);
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bool isFP = MVT::isFloatingPoint(EVT);
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SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
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std::vector<SDOperand> ZeroVec(NumElems, Zero);
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return DAG.getNode(ISD::BUILD_VECTOR, VT, ZeroVec);
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}
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/// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
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///
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static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
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SDOperand V1 = Op.getOperand(0);
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SDOperand PermMask = Op.getOperand(2);
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SDOperand Mask = Op.getOperand(2);
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MVT::ValueType VT = Op.getValueType();
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unsigned NumElems = PermMask.getNumOperands();
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PermMask = getUnpacklMask(NumElems, DAG);
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unsigned NumElems = Mask.getNumOperands();
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Mask = getUnpacklMask(NumElems, DAG);
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while (NumElems != 4) {
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V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, PermMask);
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V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
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NumElems >>= 1;
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}
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V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
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MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
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SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
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std::vector<SDOperand> ZeroVec(4, Zero);
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SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec);
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Mask = getZeroVector(MaskVT, DAG);
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SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
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DAG.getNode(ISD::UNDEF, MVT::v4i32),
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SplatMask);
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DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
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return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
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}
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/// isZeroNode - Returns true if Elt is a constant zero or a floating point
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/// constant +0.0.
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static inline bool isZeroNode(SDOperand Elt) {
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return ((isa<ConstantSDNode>(Elt) &&
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cast<ConstantSDNode>(Elt)->getValue() == 0) ||
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(isa<ConstantFPSDNode>(Elt) &&
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cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
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}
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/// getShuffleVectorAgainstZero - Return a vector_shuffle of a zero vector and
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/// the specified vector.
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static SDOperand getShuffleVectorAgainstZero(SDOperand Vec, MVT::ValueType VT,
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unsigned NumElems, unsigned Idx,
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SelectionDAG &DAG) {
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SDOperand ZeroV = getZeroVector(VT, DAG);
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MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
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MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
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SDOperand Zero = DAG.getConstant(0, EVT);
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std::vector<SDOperand> MaskVec(NumElems, Zero);
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MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
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SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, ZeroV, Vec, Mask);
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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@ -2924,7 +2958,6 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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SDOperand PermMask = Op.getOperand(2);
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MVT::ValueType VT = Op.getValueType();
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unsigned NumElems = PermMask.getNumOperands();
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bool V2IsSplat = isSplatVector(V2.Val);
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if (isSplatMask(PermMask.Val)) {
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if (NumElems <= 4) return Op;
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@ -2932,7 +2965,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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return PromoteSplat(Op, DAG);
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}
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if (X86::isMOVSMask(PermMask.Val) ||
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if (X86::isMOVLMask(PermMask.Val) ||
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X86::isMOVSHDUPMask(PermMask.Val) ||
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X86::isMOVSLDUPMask(PermMask.Val) ||
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X86::isMOVHLPSMask(PermMask.Val) ||
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@ -2944,15 +2977,30 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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ShouldXformToMOVLP(V1.Val, PermMask.Val))
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return CommuteVectorShuffle(Op, DAG);
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if (isCommutedMOVS(PermMask.Val, V2IsSplat)) {
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bool V1IsSplat = isSplatVector(V1.Val);
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bool V2IsSplat = isSplatVector(V2.Val);
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if (V1IsSplat && !V2IsSplat) {
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Op = CommuteVectorShuffle(Op, DAG);
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V1 = Op.getOperand(0);
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V2 = Op.getOperand(1);
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PermMask = Op.getOperand(2);
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V2IsSplat = true;
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}
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if (isCommutedMOVL(PermMask.Val, V2IsSplat)) {
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Op = CommuteVectorShuffle(Op, DAG);
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V1 = Op.getOperand(0);
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V2 = Op.getOperand(1);
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PermMask = Op.getOperand(2);
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if (V2IsSplat) {
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// V2 is a splat, so the mask may be malformed. That is, it may point
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// to any V2 element. The instruction selectior won't like this. Get
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// a corrected mask and commute to form a proper MOVS{S|D}.
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SDOperand NewMask = getMOVSMask(NumElems, DAG);
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Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
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SDOperand NewMask = getMOVLMask(NumElems, DAG);
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if (NewMask.Val != PermMask.Val)
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Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
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}
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return CommuteVectorShuffle(Op, DAG);
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return Op;
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}
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if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
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@ -3088,48 +3136,60 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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if (ISD::isBuildVectorAllOnes(Op.Val))
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return Op;
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std::set<SDOperand> Values;
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SDOperand Elt0 = Op.getOperand(0);
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Values.insert(Elt0);
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bool Elt0IsZero = (isa<ConstantSDNode>(Elt0) &&
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cast<ConstantSDNode>(Elt0)->getValue() == 0) ||
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(isa<ConstantFPSDNode>(Elt0) &&
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cast<ConstantFPSDNode>(Elt0)->isExactlyValue(0.0));
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bool RestAreZero = true;
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unsigned NumElems = Op.getNumOperands();
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for (unsigned i = 1; i < NumElems; ++i) {
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SDOperand Elt = Op.getOperand(i);
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if (ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Elt)) {
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if (!FPC->isExactlyValue(+0.0))
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RestAreZero = false;
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} else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
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if (!C->isNullValue())
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RestAreZero = false;
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} else
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RestAreZero = false;
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MVT::ValueType VT = Op.getValueType();
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MVT::ValueType EVT = MVT::getVectorBaseType(VT);
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std::vector<unsigned> NonZeros;
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std::set<SDOperand> Values;
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for (unsigned i = 0; i < NumElems; ++i) {
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unsigned Idx = NumElems - i - 1;
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SDOperand Elt = Op.getOperand(Idx);
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Values.insert(Elt);
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if (!isZeroNode(Elt))
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NonZeros.push_back(Idx);
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}
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if (RestAreZero) {
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if (Elt0IsZero) return Op;
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if (NonZeros.size() == 0)
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return Op;
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// Zero extend a scalar to a vector.
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if (Elt0.getValueType() != MVT::i64)
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return DAG.getNode(X86ISD::ZEXT_S2VEC, Op.getValueType(), Elt0);
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if (NonZeros.size() == 1) {
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unsigned Idx = NonZeros[0];
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SDOperand Item = Op.getOperand(Idx);
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if (Idx == 0 || MVT::getSizeInBits(EVT) >= 32)
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Item = DAG.getNode(ISD::SCALAR_TO_VECTOR,VT, Item);
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if (Idx == 0)
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return getShuffleVectorAgainstZero(Item, VT, NumElems, Idx, DAG);
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// See if we can turn it into a f64 op.
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bool IsLegal = false;
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt0)) {
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Elt0 = DAG.getConstantFP(BitsToDouble(C->getValue()), MVT::f64);
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IsLegal = true;
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} else if (Elt0.getOpcode() == ISD::LOAD) {
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Elt0 = DAG.getLoad(MVT::f64, Elt0.getOperand(0), Elt0.getOperand(1),
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Elt0.getOperand(2));
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IsLegal = true;
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// If element VT is < 32, convert it to a insert into a zero vector.
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if (MVT::getSizeInBits(EVT) <= 16) {
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SDOperand ZeroV;
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if (EVT == MVT::i8) {
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Item = DAG.getNode(ISD::ANY_EXTEND, MVT::i16, Item);
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if ((Idx % 2) != 0)
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Item = DAG.getNode(ISD::SHL, MVT::i16,
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Item, DAG.getConstant(8, MVT::i8));
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Idx /= 2;
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ZeroV = getZeroVector(MVT::v8i16, DAG);
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return DAG.getNode(ISD::BIT_CONVERT, VT,
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DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, ZeroV, Item,
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DAG.getConstant(Idx, MVT::i32)));
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} else {
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ZeroV = getZeroVector(VT, DAG);
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return DAG.getNode(ISD::INSERT_VECTOR_ELT, VT, ZeroV, Item,
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DAG.getConstant(Idx, MVT::i32));
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}
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}
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if (IsLegal)
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return DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
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DAG.getNode(X86ISD::ZEXT_S2VEC, MVT::v2f64, Elt0));
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// Turn it into a shuffle of zero and zero-extended scalar to vector.
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Item = getShuffleVectorAgainstZero(Item, VT, NumElems, 0, DAG);
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MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
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MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
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std::vector<SDOperand> MaskVec;
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for (unsigned i = 0; i < NumElems; i++)
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MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
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SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
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DAG.getNode(ISD::UNDEF, VT), Mask);
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}
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if (Values.size() > 2) {
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@ -3138,7 +3198,6 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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// Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
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// : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
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// Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
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MVT::ValueType VT = Op.getValueType();
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SDOperand PermMask = getUnpacklMask(NumElems, DAG);
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std::vector<SDOperand> V(NumElems);
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for (unsigned i = 0; i < NumElems; ++i)
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@ -3406,7 +3465,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
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case X86ISD::Wrapper: return "X86ISD::Wrapper";
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case X86ISD::S2VEC: return "X86ISD::S2VEC";
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case X86ISD::ZEXT_S2VEC: return "X86ISD::ZEXT_S2VEC";
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case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
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case X86ISD::PINSRW: return "X86ISD::PINSRW";
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}
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@ -3514,7 +3572,7 @@ bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
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if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
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if (NumElts == 2) return true;
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if (NumElts == 4) {
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return (isMOVSMask(BVOps) || isCommutedMOVS(BVOps, true) ||
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return (isMOVLMask(BVOps) || isCommutedMOVL(BVOps, true) ||
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isSHUFPMask(BVOps) || isCommutedSHUFP(BVOps));
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}
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return false;
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@ -150,10 +150,6 @@ namespace llvm {
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/// have to match the operand type.
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S2VEC,
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/// ZEXT_S2VEC - SCALAR_TO_VECTOR with zero extension. The destination base
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/// does not have to match the operand type.
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ZEXT_S2VEC,
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/// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
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/// i32, corresponds to X86::PEXTRW.
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PEXTRW,
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@ -230,9 +226,10 @@ namespace llvm {
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/// <0, 0, 1, 1>
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bool isUNPCKL_v_undef_Mask(SDNode *N);
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/// isMOVSMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVS{S|D}.
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bool isMOVSMask(SDNode *N);
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/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSS,
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/// MOVSD, and MOVD, i.e. setting the lowest element.
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bool isMOVLMask(SDNode *N);
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/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
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@ -29,8 +29,6 @@ def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
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[SDNPOutFlag]>;
|
||||
def X86s2vec : SDNode<"X86ISD::S2VEC",
|
||||
SDTypeProfile<1, 1, []>, []>;
|
||||
def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
|
||||
SDTypeProfile<1, 1, []>, []>;
|
||||
def X86pextrw : SDNode<"X86ISD::PEXTRW",
|
||||
SDTypeProfile<1, 2, []>, []>;
|
||||
def X86pinsrw : SDNode<"X86ISD::PINSRW",
|
||||
|
|
@ -104,8 +102,8 @@ def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
|
|||
return X86::isMOVLPMask(N);
|
||||
}]>;
|
||||
|
||||
def MOVS_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isMOVSMask(N);
|
||||
def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isMOVLMask(N);
|
||||
}]>;
|
||||
|
||||
def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
|
|
@ -2194,20 +2192,18 @@ def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2)
|
|||
"movss {$src2, $dst|$dst, $src2}", []>;
|
||||
def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2),
|
||||
"movsd {$src2, $dst|$dst, $src2}", []>;
|
||||
def MOVLDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, R32:$src2),
|
||||
"movd {$src2, $dst|$dst, $src2}", []>;
|
||||
|
||||
let AddedComplexity = 20 in {
|
||||
def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"movss {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
MOVS_shuffle_mask)))]>;
|
||||
MOVL_shuffle_mask)))]>;
|
||||
def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
|
||||
"movsd {$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
MOVS_shuffle_mask)))]>;
|
||||
MOVL_shuffle_mask)))]>;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2223,23 +2219,36 @@ def MOVLQ128rr : PDI<0xD6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
|
|||
|
||||
// Move to lower bits of a VR128 and zeroing upper bits.
|
||||
// Loading from memory automatically zeroing upper bits.
|
||||
let AddedComplexity = 20 in {
|
||||
def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
|
||||
"movss {$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(v4f32 (X86zexts2vec (loadf32 addr:$src))))]>;
|
||||
[(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV,
|
||||
(v4f32 (scalar_to_vector (loadf32 addr:$src))),
|
||||
MOVL_shuffle_mask)))]>;
|
||||
def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
|
||||
"movsd {$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(v2f64 (X86zexts2vec (loadf64 addr:$src))))]>;
|
||||
[(set VR128:$dst, (v2f64 (vector_shuffle immAllZerosV,
|
||||
(v2f64 (scalar_to_vector (loadf64 addr:$src))),
|
||||
MOVL_shuffle_mask)))]>;
|
||||
// movd / movq to XMM register zero-extends
|
||||
def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src),
|
||||
"movd {$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
|
||||
(v4i32 (scalar_to_vector R32:$src)),
|
||||
MOVL_shuffle_mask)))]>;
|
||||
def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
|
||||
"movd {$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(v4i32 (X86zexts2vec (loadi32 addr:$src))))]>;
|
||||
[(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
|
||||
(v4i32 (scalar_to_vector (loadi32 addr:$src))),
|
||||
MOVL_shuffle_mask)))]>;
|
||||
def MOVZQI2PQIrr : PDI<0x7E, MRMSrcMem, (ops VR128:$dst, VR64:$src),
|
||||
"movq {$src, $dst|$dst, $src}", []>;
|
||||
def MOVZQI2PQIrm : PDI<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
|
||||
"movq {$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(bc_v2i64 (v2f64 (X86zexts2vec
|
||||
(loadf64 addr:$src)))))]>;
|
||||
[(set VR128:$dst, (bc_v2i64 (vector_shuffle immAllZerosV,
|
||||
(v2f64 (scalar_to_vector (loadf64 addr:$src))),
|
||||
MOVL_shuffle_mask)))]>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Non-Instruction Patterns
|
||||
|
|
@ -2341,17 +2350,23 @@ def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>,
|
|||
def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
|
||||
// Zeroing a VR128 then do a MOVS* to the lower bits.
|
||||
def : Pat<(v2f64 (X86zexts2vec FR64:$src)),
|
||||
// Move scalar to XMM zero-extended
|
||||
// movd to XMM register zero-extends
|
||||
let AddedComplexity = 20 in {
|
||||
def : Pat<(v8i16 (vector_shuffle immAllZerosV,
|
||||
(v8i16 (X86s2vec R32:$src)), MOVL_shuffle_mask)),
|
||||
(MOVZDI2PDIrr R32:$src)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v16i8 (vector_shuffle immAllZerosV,
|
||||
(v16i8 (X86s2vec R32:$src)), MOVL_shuffle_mask)),
|
||||
(MOVZDI2PDIrr R32:$src)>, Requires<[HasSSE2]>;
|
||||
// Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
|
||||
def : Pat<(v2f64 (vector_shuffle immAllZerosV,
|
||||
(v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
|
||||
(MOVLSD2PDrr (V_SET0_PD), FR64:$src)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v4f32 (X86zexts2vec FR32:$src)),
|
||||
def : Pat<(v4f32 (vector_shuffle immAllZerosV,
|
||||
(v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
|
||||
(MOVLSS2PSrr (V_SET0_PS), FR32:$src)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v4i32 (X86zexts2vec R32:$src)),
|
||||
(MOVLDI2PDIrr (V_SET0_PI), R32:$src)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v8i16 (X86zexts2vec R16:$src)),
|
||||
(MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr16 R16:$src))>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v16i8 (X86zexts2vec R8:$src)),
|
||||
(MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
|
||||
}
|
||||
|
||||
// Splat v2f64 / v2i64
|
||||
let AddedComplexity = 10 in {
|
||||
|
|
@ -2448,13 +2463,13 @@ def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
|
|||
(MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
||||
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
MOVS_shuffle_mask)),
|
||||
MOVL_shuffle_mask)),
|
||||
(MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
|
||||
MOVLP_shuffle_mask)),
|
||||
(MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
MOVS_shuffle_mask)),
|
||||
MOVL_shuffle_mask)),
|
||||
(MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
|
||||
MOVHP_shuffle_mask)),
|
||||
|
|
|
|||
Loading…
Reference in New Issue