forked from OSchip/llvm-project
[Power9] Add missing instructions to the Power 9 scheduler
Adding more instructions using InstRW so that we can move away from ItinRW and ultimately have a complete Power 9 scheduler. Differential Revision: https://reviews.llvm.org/D43899 llvm-svn: 326447
This commit is contained in:
Stefan Pintilie
parent
a83e226c2f
commit
e894e0ff6f
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@ -37,19 +37,7 @@ def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C,
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DISP_1C, DISP_1C, DISP_1C],
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(instrs
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(instregex "VADDU(B|H|W|D)M$"),
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VADDCUW,
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VAND,
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VANDC,
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VCMPEQUB,
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VCMPEQUD,
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VCMPEQUH,
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VCMPEQUW,
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VCMPNEB,
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VCMPNEH,
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VCMPNEW,
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VCMPNEZB,
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VCMPNEZH,
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VCMPNEZW,
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(instregex "VAND(C)?$"),
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VEQV,
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VEXTSB2D,
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VEXTSB2W,
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@ -175,14 +163,15 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C],
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(instregex "EXTSWSLI$"),
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SRADI_32,
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RLDIC,
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ADDIC,
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ADDICo,
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RFEBB,
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LA,
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(instregex "CMP(WI|LWI|W|LW)(8)?$"),
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(instregex "SUBF(I)?C(8)?$"),
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(instregex "ANDI(S)?o(8)?$"),
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(instregex "ADD(I)?C(8)?(o)?$"),
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(instregex "ADD(E|ME|ZE)(8)?$"),
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(instregex "ADDC(8)?$"),
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(instregex "ADDIC(8)?(o)?$"),
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(instregex "ADD(8|4)(o)?$"),
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(instregex "ADD(E|ME|ZE)(8)?(o)?$"),
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(instregex "SUBF(E|ME|ZE)?(8)?$"),
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(instregex "NEG(8)?$"),
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(instregex "POPCNTB$"),
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@ -191,7 +180,7 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C],
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(instregex "(X)?OR(I|IS)?(8)?$"),
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NOP,
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(instregex "NAND(8)?$"),
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(instregex "AND(C)?(8)?$"),
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(instregex "AND(C)?(8)?(o)?$"),
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(instregex "NOR(8)?$"),
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(instregex "OR(C)?(8)?$"),
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(instregex "EQV(8)?$"),
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@ -231,10 +220,19 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
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def : InstRW<[P9_ALUE_3C, P9_ALUO_3C, IP_EXECE_1C, IP_EXECO_1C,
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DISP_1C, DISP_1C, DISP_1C],
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(instrs
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(instregex "VCMPNEZ(B|H|W)$"),
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VCMPEQUB,
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VCMPEQUD,
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VCMPEQUH,
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VCMPEQUW,
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VCMPNEB,
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VCMPNEH,
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VCMPNEW,
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VBPERMD,
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VABSDUB,
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VABSDUH,
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VABSDUW,
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VADDCUW,
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VADDUBS,
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VADDUHS,
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VADDUWS,
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@ -518,9 +516,9 @@ def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
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XSNMSUBMSP
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)>;
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// 7 cycle Restricted DP operation and one 2 cycle ALU operation.
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// 7 cycle Restricted DP operation and one 3 cycle ALU operation.
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// The DP is restricted so we need a full 5 dispatches.
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def : InstRW<[P9_DPOpAndALUOp_9C, IP_EXEC_1C, IP_EXEC_1C,
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def : InstRW<[P9_DPOpAndALU2Op_10C, IP_EXEC_1C, IP_EXEC_1C,
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DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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FMULo,
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@ -665,7 +663,17 @@ def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C, DISP_1C, DISP_1C],
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XSCMPOQP,
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XSCMPUQP,
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XSTSTDCQP,
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XSXSIGQP
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XSXSIGQP,
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BCDCFNo,
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BCDCFZo,
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BCDCPSGNo,
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BCDCTNo,
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BCDCTZo,
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BCDSETSGNo,
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BCDSo,
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BCDTRUNCo,
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BCDUSo,
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BCDUTRUNCo
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)>;
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// 12 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
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@ -673,6 +681,7 @@ def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C, DISP_1C, DISP_1C],
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// dispatches.
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def : InstRW<[P9_DFU_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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BCDSRo,
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XSADDQP,
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XSADDQPO,
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XSCVDPQP,
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@ -690,6 +699,14 @@ def : InstRW<[P9_DFU_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C, DISP_1C],
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XSSUBQPO
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)>;
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// 23 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
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// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
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// dispatches.
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def : InstRW<[P9_DFU_23C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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BCDCTSQo
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)>;
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// 24 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
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// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
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// dispatches.
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@ -707,6 +724,14 @@ def : InstRW<[P9_DFU_24C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C, DISP_1C],
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XSNMSUBQPO
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)>;
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// 37 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
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// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
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// dispatches.
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def : InstRW<[P9_DFU_37C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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BCDCFSQo
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)>;
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// 58 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
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// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
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// dispatches.
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@ -730,6 +755,7 @@ def : InstRW<[P9_LS_5C, IP_AGEN_1C, DISP_1C, DISP_1C],
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(instrs
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LXSDX,
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LXVD2X,
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LXVWSX,
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LXSIWZX,
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LXV,
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LXVX,
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@ -761,9 +787,7 @@ def : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C],
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def : InstRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,
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DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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LFIWAX,
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LFSX,
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LFS
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LFIWAX
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)>;
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// Cracked Load instruction.
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@ -773,14 +797,35 @@ def : InstRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,
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def : InstRW<[P9_LoadAndALUOp_7C, IP_AGEN_1C, IP_EXEC_1C,
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DISP_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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LXSSPX,
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LXSIWAX,
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LXSSP,
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DFLOADf32,
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XFLOADf32,
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LIWAX
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)>;
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// Cracked Load instruction.
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// Requires consecutive Load (4 cycles) and ALU (3 cycles) pieces totaling 7
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// cycles. The Load and ALU operations cannot be done at the same time and so
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// their latencies are added.
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// Full 6 dispatches are required as this is a restricted instruction.
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def : InstRW<[P9_LoadAndALU2Op_7C, IP_AGEN_1C, IP_EXEC_1C,
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DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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LFSX,
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LFS
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)>;
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// Cracked Load instruction.
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// Requires consecutive Load and ALU pieces totaling 8 cycles. The Load and ALU
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// operations cannot be done at the same time and so their latencies are added.
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// Full 4 dispatches are required as this is a cracked instruction.
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def : InstRW<[P9_LoadAndALU2Op_8C, IP_AGEN_1C, IP_EXEC_1C,
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DISP_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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LXSSP,
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LXSSPX,
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XFLOADf32,
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DFLOADf32
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)>;
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// Cracked Load that requires the PM resource.
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// Since the Load and the PM cannot be done at the same time the latencies are
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// added. Requires 8 cycles.
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@ -791,7 +836,6 @@ def : InstRW<[P9_LoadAndPMOp_8C, IP_AGEN_1C, IP_EXECE_1C, IP_EXECO_1C,
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DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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LXVDSX,
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LXVWSX,
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LXVW4X
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)>;
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@ -828,7 +872,9 @@ def : InstRW<[P9_LS_1C, P9_LS_1C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
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// dispatches.
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def : InstRW<[P9_DIV_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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(instregex "M(T|F)VRSAVE(v)?$")
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(instregex "M(T|F)VRSAVE(v)?$"),
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(instregex "MF(SPR|CTR|LR)(8)?$"),
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MFDCR
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)>;
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// 16 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
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@ -905,6 +951,17 @@ def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
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MTCRF8
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)>;
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// Cracked ALU operations.
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// Here the two ALU ops can actually be done in parallel and therefore the
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// latencies are not added together. Otherwise this is like having two
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// instructions running together on two pipelines and 4 dispatches.
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// ALU ops are 2 cycles each.
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def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
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DISP_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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(instregex "ADDC(8)?o$")
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)>;
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// Cracked, restricted, ALU operations.
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// Here the two ALU ops can actually be done in parallel and therefore the
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// latencies are not added together. Otherwise this is like having two
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@ -931,7 +988,7 @@ def : InstRW<[P9_DP_33C_8, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
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)>;
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// 33 Cycle DP Instruction Restricted and Cracked with 2 Cycle ALU.
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def : InstRW<[P9_DPOpAndALUOp_35C_8, IP_EXEC_1C, IP_EXEC_1C,
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def : InstRW<[P9_DPOpAndALU2Op_36C_8, IP_EXEC_1C, IP_EXEC_1C,
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DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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FDIVo
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@ -950,7 +1007,7 @@ def : InstRW<[P9_DP_22C_5, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
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)>;
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// 22 Cycle DP Instruction Restricted and Cracked with 2 Cycle ALU.
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def : InstRW<[P9_DPOpAndALUOp_24C_5, IP_EXEC_1C, IP_EXEC_1C,
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def : InstRW<[P9_DPOpAndALU2Op_25C_5, IP_EXEC_1C, IP_EXEC_1C,
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DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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FDIVSo
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@ -988,7 +1045,7 @@ def : InstRW<[P9_DPE_33C_8, P9_DPO_33C_8, IP_EXECE_1C, IP_EXECO_1C,
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// Both the load and the ALU that depends on it are restricted and so they take
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// a total of 6 dispatches. The final 2 dispatches come from the second ALU op.
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// The two EXEC pipelines are for the 2 ALUs while the AGEN is for the load.
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def : InstRW<[P9_LoadAndALUOp_6C, P9_ALU_2C,
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def : InstRW<[P9_LoadAndALU2Op_7C, P9_ALU_2C,
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IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C,
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DISP_1C, DISP_1C, DISP_1C, DISP_1C,
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DISP_1C, DISP_1C, DISP_1C, DISP_1C],
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@ -1023,19 +1080,64 @@ def : InstRW<[P9_LS_4C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C,
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// dispatches.
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def : InstRW<[P9_CY_6C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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VPMSUMB,
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VPMSUMD,
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VPMSUMH,
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VPMSUMW,
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VCIPHER,
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VCIPHERLAST,
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VNCIPHER,
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VNCIPHERLAST,
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VSBOX
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(instregex "VPMSUM(B|H|W|D)$"),
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(instregex "V(N)?CIPHER(LAST)?$"),
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VSBOX
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)>;
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// Branch Instructions
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// Two Cycle Branch
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def : InstRW<[P9_BR_2C, DISP_1C, DISP_1C],
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(instrs
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(instregex "BCCCTR(L)?(8)?$"),
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(instregex "BCCL(A|R|RL)?$"),
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(instregex "BCCTR(L)?(8)?(n)?$"),
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(instregex "BD(N)?Z(8|A|Am|Ap|m|p)?$"),
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(instregex "BD(N)?ZL(A|Am|Ap|R|R8|RL|RLm|RLp|Rm|Rp|m|p)?$"),
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(instregex "BL(_TLS)?$"),
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(instregex "BL8(_TLS|_NOP|_NOP_TLS|_TLS_)?$"),
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(instregex "BLA(8|8_NOP)?$"),
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(instregex "BLR(8|L)?$"),
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(instregex "TAILB(A)?(8)?$"),
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(instregex "TAILBCTR(8)?$"),
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(instregex "gBC(A|Aat|CTR|CTRL|L|LA|LAat|LR|LRL|Lat|at)?$"),
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(instregex "BCLR(L)?(n)?$"),
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(instregex "BCTR(L)?(8)?$"),
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B,
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BA,
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BC,
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BCC,
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BCCA,
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BCL,
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BCLalways,
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BCLn,
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BCTRL8_LDinto_toc,
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BCn,
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CTRL_DEP
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)>;
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// Five Cycle Branch with a 2 Cycle ALU Op
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// Operations must be done consecutively and not in parallel.
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def : InstRW<[P9_BROpAndALUOp_7C, IP_EXEC_1C,
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DISP_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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ADDPCIS
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)>;
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// Instructions without scheduling support.
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def : InstRW<[],
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(instrs
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(instregex "(H)?RFI(D)?$")
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(instregex "(H)?RFI(D)?$"),
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ATTN,
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BRINC,
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CLRBHRB,
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MFBHRBE,
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NAP,
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RFCI,
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RFDI,
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RFMCI,
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SC,
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WAIT
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)> { let Unsupported = 1; }
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@ -264,11 +264,21 @@ let SchedModel = P9Model in {
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let Latency = 12;
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}
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def P9_DFU_23C : SchedWriteRes<[DFU]> {
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let Latency = 23;
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let ResourceCycles = [11];
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}
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def P9_DFU_24C : SchedWriteRes<[DFU]> {
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let Latency = 24;
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let ResourceCycles = [12];
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}
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def P9_DFU_37C : SchedWriteRes<[DFU]> {
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let Latency = 37;
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let ResourceCycles = [25];
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}
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def P9_DFU_58C : SchedWriteRes<[DFU]> {
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let Latency = 58;
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let ResourceCycles = [44];
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@ -295,6 +305,8 @@ let SchedModel = P9Model in {
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def P9_LoadAndALUOp_6C : WriteSequence<[P9_LS_4C, P9_ALU_2C]>;
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def P9_LoadAndALUOp_7C : WriteSequence<[P9_LS_5C, P9_ALU_2C]>;
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def P9_LoadAndALU2Op_7C : WriteSequence<[P9_LS_4C, P9_ALU_3C]>;
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def P9_LoadAndALU2Op_8C : WriteSequence<[P9_LS_5C, P9_ALU_3C]>;
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def P9_LoadAndPMOp_8C : WriteSequence<[P9_LS_5C, P9_PM_3C]>;
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def P9_LoadAndLoadOp_8C : WriteSequence<[P9_LS_4C, P9_LS_4C]>;
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def P9_IntDivAndALUOp_26C_8 : WriteSequence<[P9_DIV_24C_8, P9_ALU_2C]>;
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@ -302,8 +314,12 @@ let SchedModel = P9Model in {
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def P9_StoreAndALUOp_4C : WriteSequence<[P9_LS_1C, P9_ALU_3C]>;
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def P9_ALUOpAndALUOp_4C : WriteSequence<[P9_ALU_2C, P9_ALU_2C]>;
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def P9_DPOpAndALUOp_9C : WriteSequence<[P9_DP_7C, P9_ALU_2C]>;
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def P9_DPOpAndALU2Op_10C : WriteSequence<[P9_DP_7C, P9_ALU_3C]>;
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def P9_DPOpAndALUOp_24C_5 : WriteSequence<[P9_DP_22C_5, P9_ALU_2C]>;
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def P9_DPOpAndALUOp_35C_8 : WriteSequence<[P9_DP_33C_8, P9_ALU_2C]>;
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def P9_DPOpAndALU2Op_25C_5 : WriteSequence<[P9_DP_22C_5, P9_ALU_3C]>;
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def P9_DPOpAndALU2Op_36C_8 : WriteSequence<[P9_DP_33C_8, P9_ALU_3C]>;
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def P9_BROpAndALUOp_7C : WriteSequence<[P9_BR_5C, P9_ALU_2C]>;
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// ***************** Defining Itinerary Class Resources *****************
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||||
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|
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Loading…
Reference in New Issue