forked from OSchip/llvm-project
AVX-512: Lowering for 512-bit vector shuffles.
Vector types: <8 x 64>, <16 x 32>, <32 x 16> float and integer. Differential Revision: http://reviews.llvm.org/D10683 llvm-svn: 246981
This commit is contained in:
Elena Demikhovsky
parent
a89dc57b41
commit
e88038f235
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@ -503,4 +503,74 @@ void DecodeINSERTQIMask(int Len, int Idx,
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ShuffleMask.push_back(SM_SentinelUndef);
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}
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void DecodeVPERMVMask(ArrayRef<uint64_t> RawMask,
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SmallVectorImpl<int> &ShuffleMask) {
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for (int i = 0, e = RawMask.size(); i < e; ++i) {
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uint64_t M = RawMask[i];
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ShuffleMask.push_back((int)M);
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}
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}
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void DecodeVPERMV3Mask(ArrayRef<uint64_t> RawMask,
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SmallVectorImpl<int> &ShuffleMask) {
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for (int i = 0, e = RawMask.size(); i < e; ++i) {
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uint64_t M = RawMask[i];
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ShuffleMask.push_back((int)M);
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}
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}
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void DecodeVPERMVMask(const Constant *C, MVT VT,
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SmallVectorImpl<int> &ShuffleMask) {
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Type *MaskTy = C->getType();
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if (MaskTy->isVectorTy()) {
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unsigned NumElements = MaskTy->getVectorNumElements();
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if (NumElements == VT.getVectorNumElements()) {
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for (unsigned i = 0; i < NumElements; ++i) {
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Constant *COp = C->getAggregateElement(i);
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if (!COp || (!isa<UndefValue>(COp) && !isa<ConstantInt>(COp))) {
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ShuffleMask.clear();
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return;
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}
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if (isa<UndefValue>(COp))
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ShuffleMask.push_back(SM_SentinelUndef);
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else {
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uint64_t Element = cast<ConstantInt>(COp)->getZExtValue();
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Element &= (1 << NumElements) - 1;
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ShuffleMask.push_back(Element);
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}
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}
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}
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return;
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}
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// Scalar value; just broadcast it
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if (!isa<ConstantInt>(C))
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return;
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uint64_t Element = cast<ConstantInt>(C)->getZExtValue();
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int NumElements = VT.getVectorNumElements();
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Element &= (1 << NumElements) - 1;
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for (int i = 0; i < NumElements; ++i)
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ShuffleMask.push_back(Element);
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}
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void DecodeVPERMV3Mask(const Constant *C, MVT VT,
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SmallVectorImpl<int> &ShuffleMask) {
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Type *MaskTy = C->getType();
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unsigned NumElements = MaskTy->getVectorNumElements();
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if (NumElements == VT.getVectorNumElements()) {
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for (unsigned i = 0; i < NumElements; ++i) {
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Constant *COp = C->getAggregateElement(i);
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if (!COp) {
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ShuffleMask.clear();
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return;
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}
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if (isa<UndefValue>(COp))
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ShuffleMask.push_back(SM_SentinelUndef);
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else {
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uint64_t Element = cast<ConstantInt>(COp)->getZExtValue();
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Element &= (1 << NumElements*2) - 1;
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ShuffleMask.push_back(Element);
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}
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}
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}
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}
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} // llvm namespace
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@ -108,6 +108,22 @@ void DecodeEXTRQIMask(int Len, int Idx,
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/// \brief Decode a SSE4A INSERTQ instruction as a v16i8 shuffle mask.
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void DecodeINSERTQIMask(int Len, int Idx,
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SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a VPERM W/D/Q/PS/PD mask from an IR-level vector constant.
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void DecodeVPERMVMask(const Constant *C, MVT VT,
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SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a VPERM W/D/Q/PS/PD mask from a raw array of constants.
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void DecodeVPERMVMask(ArrayRef<uint64_t> RawMask,
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SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a VPERMT2 W/D/Q/PS/PD mask from an IR-level vector constant.
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void DecodeVPERMV3Mask(const Constant *C, MVT VT,
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SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a VPERMT2 W/D/Q/PS/PD mask from a raw array of constants.
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void DecodeVPERMV3Mask(ArrayRef<uint64_t> RawMask,
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SmallVectorImpl<int> &ShuffleMask);
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} // llvm namespace
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#endif
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@ -1590,6 +1590,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
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@ -3794,6 +3795,8 @@ static bool isTargetShuffle(unsigned Opcode) {
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case X86ISD::VPERMILPI:
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case X86ISD::VPERM2X128:
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case X86ISD::VPERMI:
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case X86ISD::VPERMV:
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case X86ISD::VPERMV3:
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return true;
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}
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}
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@ -4658,6 +4661,122 @@ static bool getTargetShuffleMask(SDNode *N, MVT VT,
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case X86ISD::MOVLPS:
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// Not yet implemented
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return false;
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case X86ISD::VPERMV: {
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IsUnary = true;
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SDValue MaskNode = N->getOperand(0);
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while (MaskNode->getOpcode() == ISD::BITCAST)
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MaskNode = MaskNode->getOperand(0);
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unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
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SmallVector<uint64_t, 32> RawMask;
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if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
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// If we have a build-vector, then things are easy.
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EVT MaskVT = MaskNode.getValueType();
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assert(MaskVT.isInteger() &&
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MaskVT.getVectorNumElements() == VT.getVectorNumElements());
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for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
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SDValue Op = MaskNode->getOperand(i);
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if (Op->getOpcode() == ISD::UNDEF)
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RawMask.push_back((uint64_t)SM_SentinelUndef);
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else if (isa<ConstantSDNode>(Op)) {
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APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
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RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
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} else
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return false;
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}
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DecodeVPERMVMask(RawMask, Mask);
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break;
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}
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if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
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unsigned NumEltsInMask = MaskNode->getNumOperands();
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MaskNode = MaskNode->getOperand(0);
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auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
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if (CN) {
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APInt MaskEltValue = CN->getAPIntValue();
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for (unsigned i = 0; i < NumEltsInMask; ++i)
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RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
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DecodeVPERMVMask(RawMask, Mask);
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break;
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}
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// It may be a scalar load
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}
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auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
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if (!MaskLoad)
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return false;
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SDValue Ptr = MaskLoad->getBasePtr();
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if (Ptr->getOpcode() == X86ISD::Wrapper ||
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Ptr->getOpcode() == X86ISD::WrapperRIP)
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Ptr = Ptr->getOperand(0);
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auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
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if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
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return false;
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auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
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if (C) {
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DecodeVPERMVMask(C, VT, Mask);
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if (Mask.empty())
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return false;
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break;
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}
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return false;
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}
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case X86ISD::VPERMV3: {
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IsUnary = false;
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SDValue MaskNode = N->getOperand(1);
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while (MaskNode->getOpcode() == ISD::BITCAST)
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MaskNode = MaskNode->getOperand(1);
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if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
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// If we have a build-vector, then things are easy.
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EVT MaskVT = MaskNode.getValueType();
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assert(MaskVT.isInteger() &&
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MaskVT.getVectorNumElements() == VT.getVectorNumElements());
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SmallVector<uint64_t, 32> RawMask;
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unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
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for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
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SDValue Op = MaskNode->getOperand(i);
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if (Op->getOpcode() == ISD::UNDEF)
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RawMask.push_back((uint64_t)SM_SentinelUndef);
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else {
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auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
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if (!CN)
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return false;
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APInt MaskElement = CN->getAPIntValue();
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RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
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}
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}
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DecodeVPERMV3Mask(RawMask, Mask);
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break;
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}
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auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
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if (!MaskLoad)
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return false;
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SDValue Ptr = MaskLoad->getBasePtr();
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if (Ptr->getOpcode() == X86ISD::Wrapper ||
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Ptr->getOpcode() == X86ISD::WrapperRIP)
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Ptr = Ptr->getOperand(0);
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auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
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if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
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return false;
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auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
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if (C) {
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DecodeVPERMV3Mask(C, VT, Mask);
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if (Mask.empty())
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return false;
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break;
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}
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return false;
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}
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default: llvm_unreachable("unknown target shuffle node");
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}
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@ -10445,6 +10564,73 @@ static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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}
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}
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static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
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ArrayRef<int> Mask, SDValue V1,
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SDValue V2, SelectionDAG &DAG) {
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assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
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MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
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MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
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SmallVector<SDValue, 32> VPermMask;
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for (unsigned i = 0; i < VT.getVectorNumElements(); ++i)
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VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
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DAG.getConstant(Mask[i], DL, MaskEltVT));
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SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
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VPermMask);
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if (isSingleInputShuffleMask(Mask))
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return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
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return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
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}
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// X86 has dedicated unpack instructions that can handle specific blend
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// operations: UNPCKH and UNPCKL.
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static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT,
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ArrayRef<int> Mask, SDValue V1,
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SDValue V2, SelectionDAG &DAG) {
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int NumElts = VT.getVectorNumElements();
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bool Unpckl = true;
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bool Unpckh = true;
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bool UnpcklSwapped = true;
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bool UnpckhSwapped = true;
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int NumEltsInLane = 128 / VT.getScalarSizeInBits();
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for (int i = 0; i < NumElts ; ++i) {
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unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
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int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
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int HiPos = LoPos + NumEltsInLane / 2;
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int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
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int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
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if (Mask[i] == -1)
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continue;
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if (Mask[i] != LoPos)
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Unpckl = false;
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if (Mask[i] != HiPos)
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Unpckh = false;
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if (Mask[i] != LoPosSwapped)
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UnpcklSwapped = false;
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if (Mask[i] != HiPosSwapped)
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UnpckhSwapped = false;
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if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
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return SDValue();
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}
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if (Unpckl)
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return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
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if (Unpckh)
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return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
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if (UnpcklSwapped)
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return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
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if (UnpckhSwapped)
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return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
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llvm_unreachable("Unexpected result of UNPCK mask analysis");
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return SDValue();
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}
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/// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
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static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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const X86Subtarget *Subtarget,
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@ -10456,15 +10642,12 @@ static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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ArrayRef<int> Mask = SVOp->getMask();
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assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
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// X86 has dedicated unpack instructions that can handle specific blend
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// operations: UNPCKH and UNPCKL.
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if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
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SDValue UnpckNode =
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lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG);
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if (UnpckNode)
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return UnpckNode;
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// FIXME: Implement direct support for this type!
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return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
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return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
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}
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/// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
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@ -10478,22 +10661,12 @@ static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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ArrayRef<int> Mask = SVOp->getMask();
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assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(V1, V2, Mask,
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{// First 128-bit lane.
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0, 16, 1, 17, 4, 20, 5, 21,
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// Second 128-bit lane.
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8, 24, 9, 25, 12, 28, 13, 29}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask,
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{// First 128-bit lane.
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2, 18, 3, 19, 6, 22, 7, 23,
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// Second 128-bit lane.
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10, 26, 11, 27, 14, 30, 15, 31}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
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SDValue UnpckNode =
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lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG);
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if (UnpckNode)
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return UnpckNode;
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// FIXME: Implement direct support for this type!
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return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
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return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
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}
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/// \brief Handle lowering of 8-lane 64-bit integer shuffles.
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@ -10507,15 +10680,12 @@ static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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ArrayRef<int> Mask = SVOp->getMask();
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assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
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// X86 has dedicated unpack instructions that can handle specific blend
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// operations: UNPCKH and UNPCKL.
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if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
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SDValue UnpckNode =
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lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG);
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if (UnpckNode)
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return UnpckNode;
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// FIXME: Implement direct support for this type!
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return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
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return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
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}
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/// \brief Handle lowering of 16-lane 32-bit integer shuffles.
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@ -10529,22 +10699,12 @@ static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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ArrayRef<int> Mask = SVOp->getMask();
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assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(V1, V2, Mask,
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||||
{// First 128-bit lane.
|
||||
0, 16, 1, 17, 4, 20, 5, 21,
|
||||
// Second 128-bit lane.
|
||||
8, 24, 9, 25, 12, 28, 13, 29}))
|
||||
return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
|
||||
if (isShuffleEquivalent(V1, V2, Mask,
|
||||
{// First 128-bit lane.
|
||||
2, 18, 3, 19, 6, 22, 7, 23,
|
||||
// Second 128-bit lane.
|
||||
10, 26, 11, 27, 14, 30, 15, 31}))
|
||||
return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
|
||||
SDValue UnpckNode =
|
||||
lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG);
|
||||
if (UnpckNode)
|
||||
return UnpckNode;
|
||||
|
||||
// FIXME: Implement direct support for this type!
|
||||
return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
|
||||
return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
|
||||
}
|
||||
|
||||
/// \brief Handle lowering of 32-lane 16-bit integer shuffles.
|
||||
|
|
@ -10559,8 +10719,7 @@ static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
|
|||
assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
|
||||
assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
|
||||
|
||||
// FIXME: Implement direct support for this type!
|
||||
return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
|
||||
return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
|
||||
}
|
||||
|
||||
/// \brief Handle lowering of 64-lane 8-bit integer shuffles.
|
||||
|
|
|
|||
|
|
@ -1269,26 +1269,37 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
|||
break;
|
||||
}
|
||||
|
||||
// For loads from a constant pool to a vector register, print the constant
|
||||
// loaded.
|
||||
case X86::MOVAPDrm:
|
||||
case X86::VMOVAPDrm:
|
||||
case X86::VMOVAPDYrm:
|
||||
case X86::MOVUPDrm:
|
||||
case X86::VMOVUPDrm:
|
||||
case X86::VMOVUPDYrm:
|
||||
case X86::MOVAPSrm:
|
||||
case X86::VMOVAPSrm:
|
||||
case X86::VMOVAPSYrm:
|
||||
case X86::MOVUPSrm:
|
||||
case X86::VMOVUPSrm:
|
||||
case X86::VMOVUPSYrm:
|
||||
case X86::MOVDQArm:
|
||||
case X86::VMOVDQArm:
|
||||
case X86::VMOVDQAYrm:
|
||||
case X86::MOVDQUrm:
|
||||
case X86::VMOVDQUrm:
|
||||
case X86::VMOVDQUYrm:
|
||||
#define MOV_CASE(Prefix, Suffix) \
|
||||
case X86::Prefix##MOVAPD##Suffix##rm: \
|
||||
case X86::Prefix##MOVAPS##Suffix##rm: \
|
||||
case X86::Prefix##MOVUPD##Suffix##rm: \
|
||||
case X86::Prefix##MOVUPS##Suffix##rm: \
|
||||
case X86::Prefix##MOVDQA##Suffix##rm: \
|
||||
case X86::Prefix##MOVDQU##Suffix##rm:
|
||||
|
||||
#define MOV_AVX512_CASE(Suffix) \
|
||||
case X86::VMOVDQA64##Suffix##rm: \
|
||||
case X86::VMOVDQA32##Suffix##rm: \
|
||||
case X86::VMOVDQU64##Suffix##rm: \
|
||||
case X86::VMOVDQU32##Suffix##rm: \
|
||||
case X86::VMOVDQU16##Suffix##rm: \
|
||||
case X86::VMOVDQU8##Suffix##rm: \
|
||||
case X86::VMOVAPS##Suffix##rm: \
|
||||
case X86::VMOVAPD##Suffix##rm: \
|
||||
case X86::VMOVUPS##Suffix##rm: \
|
||||
case X86::VMOVUPD##Suffix##rm:
|
||||
|
||||
#define CASE_ALL_MOV_RM() \
|
||||
MOV_CASE(, ) /* SSE */ \
|
||||
MOV_CASE(V, ) /* AVX-128 */ \
|
||||
MOV_CASE(V, Y) /* AVX-256 */ \
|
||||
MOV_AVX512_CASE(Z) \
|
||||
MOV_AVX512_CASE(Z256) \
|
||||
MOV_AVX512_CASE(Z128)
|
||||
|
||||
// For loads from a constant pool to a vector register, print the constant
|
||||
// loaded.
|
||||
CASE_ALL_MOV_RM()
|
||||
if (!OutStreamer->isVerboseAsm())
|
||||
break;
|
||||
if (MI->getNumOperands() > 4)
|
||||
|
|
|
|||
|
|
@ -12,6 +12,15 @@ define <16 x float> @shuffle_v16f32_00_10_01_11_04_14_05_15_08_18_09_19_0c_1c_0d
|
|||
ret <16 x float> %shuffle
|
||||
}
|
||||
|
||||
define <16 x float> @shuffle_v16f32_vunpcklps_swap(<16 x float> %a, <16 x float> %b) {
|
||||
; ALL-LABEL: shuffle_v16f32_vunpcklps_swap:
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vunpcklps {{.*#+}} zmm0 = zmm1[0],zmm0[0],zmm1[1],zmm0[1],zmm1[4],zmm0[4],zmm1[5],zmm0[5],zmm1[8],zmm0[8],zmm1[9],zmm0[9],zmm1[12],zmm0[12],zmm1[13],zmm0[13]
|
||||
; ALL-NEXT: retq
|
||||
%shuffle = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> <i32 16, i32 0, i32 17, i32 1, i32 20, i32 4, i32 21, i32 5, i32 24, i32 8, i32 25, i32 9, i32 28, i32 12, i32 29, i32 13>
|
||||
ret <16 x float> %shuffle
|
||||
}
|
||||
|
||||
define <16 x i32> @shuffle_v16i32_00_10_01_11_04_14_05_15_08_18_09_19_0c_1c_0d_1d(<16 x i32> %a, <16 x i32> %b) {
|
||||
; ALL-LABEL: shuffle_v16i32_00_10_01_11_04_14_05_15_08_18_09_19_0c_1c_0d_1d:
|
||||
; ALL: # BB#0:
|
||||
|
|
@ -38,3 +47,76 @@ define <16 x i32> @shuffle_v16i32_02_12_03_13_06_16_07_17_0a_1a_0b_1b_0e_1e_0f_1
|
|||
%shuffle = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32><i32 2, i32 18, i32 3, i32 19, i32 6, i32 22, i32 7, i32 23, i32 10, i32 26, i32 11, i32 27, i32 14, i32 30, i32 15, i32 31>
|
||||
ret <16 x i32> %shuffle
|
||||
}
|
||||
|
||||
define <16 x float> @shuffle_v16f32_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_01(<16 x float> %a) {
|
||||
; ALL-LABEL: shuffle_v16f32_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_01:
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vmovdqa32 {{.*#+}} zmm1 = <2,5,u,u,7,u,10,1,0,5,u,4,7,u,10,1>
|
||||
; ALL-NEXT: vpermps %zmm0, %zmm1, %zmm0
|
||||
; ALL-NEXT: retq
|
||||
%c = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1>
|
||||
ret <16 x float> %c
|
||||
}
|
||||
|
||||
define <16 x i32> @shuffle_v16i32_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_01(<16 x i32> %a) {
|
||||
; ALL-LABEL: shuffle_v16i32_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_01:
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vmovdqa32 {{.*#+}} zmm1 = <2,5,u,u,7,u,10,1,0,5,u,4,7,u,10,1>
|
||||
; ALL-NEXT: vpermd %zmm0, %zmm1, %zmm0
|
||||
; ALL-NEXT: retq
|
||||
%c = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1>
|
||||
ret <16 x i32> %c
|
||||
}
|
||||
|
||||
define <16 x i32> @shuffle_v16i32_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_18(<16 x i32> %a, <16 x i32> %b) {
|
||||
; ALL-LABEL: shuffle_v16i32_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_18:
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vmovdqa32 {{.*#+}} zmm2 = [15,31,14,22,13,29,4,28,11,27,10,26,9,25,8,24]
|
||||
; ALL-NEXT: vpermt2d %zmm1, %zmm2, %zmm0
|
||||
; ALL-NEXT: retq
|
||||
%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
|
||||
ret <16 x i32> %c
|
||||
}
|
||||
|
||||
define <16 x float> @shuffle_v16f32_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_18(<16 x float> %a, <16 x float> %b) {
|
||||
; ALL-LABEL: shuffle_v16f32_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_18:
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vmovdqa32 {{.*#+}} zmm2 = [15,31,14,22,13,29,4,28,11,27,10,26,9,25,8,24]
|
||||
; ALL-NEXT: vpermt2ps %zmm1, %zmm2, %zmm0
|
||||
; ALL-NEXT: retq
|
||||
%c = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
|
||||
ret <16 x float> %c
|
||||
}
|
||||
|
||||
define <16 x float> @shuffle_v16f32_load_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_18(<16 x float> %a, <16 x float>* %b) {
|
||||
; ALL-LABEL: shuffle_v16f32_load_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_18:
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vmovdqa32 {{.*#+}} zmm1 = [15,31,14,22,13,29,4,28,11,27,10,26,9,25,8,24]
|
||||
; ALL-NEXT: vpermt2ps (%rdi), %zmm1, %zmm0
|
||||
; ALL-NEXT: retq
|
||||
%c = load <16 x float>, <16 x float>* %b
|
||||
%d = shufflevector <16 x float> %a, <16 x float> %c, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
|
||||
ret <16 x float> %d
|
||||
}
|
||||
|
||||
define <16 x i32> @shuffle_v16i32_load_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_18(<16 x i32> %a, <16 x i32>* %b) {
|
||||
; ALL-LABEL: shuffle_v16i32_load_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_18:
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vmovdqa32 {{.*#+}} zmm1 = [15,31,14,22,13,29,4,28,11,27,10,26,9,25,8,24]
|
||||
; ALL-NEXT: vpermt2d (%rdi), %zmm1, %zmm0
|
||||
; ALL-NEXT: retq
|
||||
%c = load <16 x i32>, <16 x i32>* %b
|
||||
%d = shufflevector <16 x i32> %a, <16 x i32> %c, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
|
||||
ret <16 x i32> %d
|
||||
}
|
||||
|
||||
define <16 x i32> @shuffle_v16i32_0_1_2_13_u_u_u_u_u_u_u_u_u_u_u_u(<16 x i32> %a, <16 x i32> %b) {
|
||||
; ALL-LABEL: shuffle_v16i32_0_1_2_13_u_u_u_u_u_u_u_u_u_u_u_u:
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vmovdqa32 {{.*#+}} zmm2 = <0,1,2,19,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; ALL-NEXT: vpermt2d %zmm1, %zmm2, %zmm0
|
||||
; ALL-NEXT: retq
|
||||
%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
ret <16 x i32> %c
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512f -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512BW
|
||||
|
||||
target triple = "x86_64-unknown-unknown"
|
||||
|
||||
define <32 x i16> @shuffle_v32i16_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_01_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_1f(<32 x i16> %a) {
|
||||
; ALL-LABEL: shuffle_v32i16_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_01_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_1f:
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vmovdqu16 {{.*#+}} zmm1 = <2,5,u,u,7,u,10,1,0,5,u,4,7,u,10,1,2,5,u,u,7,u,10,1,0,5,u,4,7,u,10,31>
|
||||
; ALL-NEXT: vpermw %zmm0, %zmm1, %zmm0
|
||||
; ALL-NEXT: retq
|
||||
%c = shufflevector <32 x i16> %a, <32 x i16> undef, <32 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1, i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 31>
|
||||
ret <32 x i16> %c
|
||||
}
|
||||
|
||||
define <32 x i16> @shuffle_v32i16_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_18_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_38(<32 x i16> %a, <32 x i16> %b) {
|
||||
; ALL-LABEL: shuffle_v32i16_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_18_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_38:
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vmovdqu16 {{.*#+}} zmm2 = [15,31,14,22,13,29,4,28,11,27,10,26,9,25,8,24,15,31,14,22,13,29,4,28,11,27,10,26,9,25,8,56]
|
||||
; ALL-NEXT: vpermt2w %zmm1, %zmm2, %zmm0
|
||||
; ALL-NEXT: retq
|
||||
%c = shufflevector <32 x i16> %a, <32 x i16> %b, <32 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24, i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 56>
|
||||
ret <32 x i16> %c
|
||||
}
|
||||
|
||||
define <32 x i16> @shuffle_v16i32_0_32_1_33_2_34_3_35_8_40_9_41_u_u_u_u(<32 x i16> %a, <32 x i16> %b) {
|
||||
; ALL-LABEL: shuffle_v16i32_0_32_1_33_2_34_3_35_8_40_9_41_u_u_u_u:
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vmovdqu16 {{.*#+}} zmm2 = <0,32,1,33,2,34,3,35,8,40,9,41,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; ALL-NEXT: vpermt2w %zmm1, %zmm2, %zmm0
|
||||
; ALL-NEXT: retq
|
||||
%c = shufflevector <32 x i16> %a, <32 x i16> %b, <32 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 8, i32 40, i32 9, i32 41, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
ret <32 x i16> %c
|
||||
}
|
||||
|
||||
define <32 x i16> @shuffle_v16i32_4_36_5_37_6_38_7_39_12_44_13_45_u_u_u_u(<32 x i16> %a, <32 x i16> %b) {
|
||||
; ALL-LABEL: shuffle_v16i32_4_36_5_37_6_38_7_39_12_44_13_45_u_u_u_u:
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vmovdqu16 {{.*#+}} zmm2 = <4,36,5,37,6,38,7,39,12,44,13,45,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; ALL-NEXT: vpermt2w %zmm1, %zmm2, %zmm0
|
||||
; ALL-NEXT: retq
|
||||
%c = shufflevector <32 x i16> %a, <32 x i16> %b, <32 x i32> <i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 12, i32 44, i32 13, i32 45, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
ret <32 x i16> %c
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue