forked from OSchip/llvm-project
ARM: properly handle alignment for struct byval.
Factor out the expansion code into a function. This change is to be enabled in clang. rdar://9877866 llvm-svn: 157830
This commit is contained in:
Manman Ren
parent
2c3f63cbda
commit
e873552091
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@ -299,6 +299,15 @@ protected:
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unsigned Op1, bool Op1IsKill,
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uint64_t Imm);
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/// FastEmitInst_rrii - Emit a MachineInstr with two register operands,
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/// two immediates operands, and a result register in the given register
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/// class.
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unsigned FastEmitInst_rrii(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill,
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uint64_t Imm1, uint64_t Imm2);
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/// FastEmitInst_i - Emit a MachineInstr with a single immediate
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/// operand, and a result register in the given register class.
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unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
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@ -1306,6 +1306,30 @@ unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
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return ResultReg;
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}
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unsigned FastISel::FastEmitInst_rrii(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill,
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uint64_t Imm1, uint64_t Imm2) {
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unsigned ResultReg = createResultReg(RC);
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const MCInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addReg(Op1, Op1IsKill * RegState::Kill)
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.addImm(Imm1).addImm(Imm2);
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else {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addReg(Op1, Op1IsKill * RegState::Kill)
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.addImm(Imm1).addImm(Imm2);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(II.ImplicitDefs[0]);
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}
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return ResultReg;
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}
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unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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uint64_t Imm) {
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@ -1434,9 +1434,10 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
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SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
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MVT::i32);
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SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
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SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
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SDValue Ops[] = { Chain, Dst, Src, SizeNode};
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SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
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MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
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Ops, array_lengthof(Ops)));
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}
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@ -6239,6 +6240,270 @@ MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
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llvm_unreachable("Expecting a BB with two successors!");
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}
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MachineBasicBlock *ARMTargetLowering::
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EmitStructByval(MachineInstr *MI, MachineBasicBlock *BB) const {
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// This pseudo instruction has 3 operands: dst, src, size
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// We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
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// Otherwise, we will generate unrolled scalar copies.
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = BB;
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++It;
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unsigned dest = MI->getOperand(0).getReg();
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unsigned src = MI->getOperand(1).getReg();
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unsigned SizeVal = MI->getOperand(2).getImm();
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unsigned Align = MI->getOperand(3).getImm();
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DebugLoc dl = MI->getDebugLoc();
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bool isThumb2 = Subtarget->isThumb2();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned ldrOpc, strOpc, UnitSize;
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const TargetRegisterClass *TRC = isThumb2 ?
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(const TargetRegisterClass*)&ARM::tGPRRegClass :
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(const TargetRegisterClass*)&ARM::GPRRegClass;
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if (Align & 1) {
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ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM;
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strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM;
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UnitSize = 1;
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} else if (Align & 2) {
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ldrOpc = isThumb2 ? ARM::t2LDRH_POST : ARM::LDRH_POST;
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strOpc = isThumb2 ? ARM::t2STRH_POST : ARM::STRH_POST;
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UnitSize = 2;
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} else {
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ldrOpc = isThumb2 ? ARM::t2LDR_POST : ARM::LDR_POST_IMM;
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strOpc = isThumb2 ? ARM::t2STR_POST : ARM::STR_POST_IMM;
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UnitSize = 4;
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}
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unsigned BytesLeft = SizeVal % UnitSize;
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unsigned LoopSize = SizeVal - BytesLeft;
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if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
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// Use LDR and STR to copy.
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// [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
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// [destOut] = STR_POST(scratch, destIn, UnitSize)
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unsigned srcIn = src;
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unsigned destIn = dest;
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for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
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unsigned scratch = MRI.createVirtualRegister(TRC);
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unsigned srcOut = MRI.createVirtualRegister(TRC);
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unsigned destOut = MRI.createVirtualRegister(TRC);
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if (isThumb2) {
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AddDefaultPred(BuildMI(*BB, MI, dl,
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TII->get(ldrOpc), scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addImm(UnitSize));
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
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.addReg(scratch).addReg(destIn)
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.addImm(UnitSize));
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} else {
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AddDefaultPred(BuildMI(*BB, MI, dl,
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TII->get(ldrOpc), scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addReg(0)
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.addImm(UnitSize));
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
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.addReg(scratch).addReg(destIn)
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.addReg(0).addImm(UnitSize));
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}
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srcIn = srcOut;
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destIn = destOut;
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}
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// Handle the leftover bytes with LDRB and STRB.
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// [scratch, srcOut] = LDRB_POST(srcIn, 1)
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// [destOut] = STRB_POST(scratch, destIn, 1)
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ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM;
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strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM;
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for (unsigned i = 0; i < BytesLeft; i++) {
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unsigned scratch = MRI.createVirtualRegister(TRC);
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unsigned srcOut = MRI.createVirtualRegister(TRC);
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unsigned destOut = MRI.createVirtualRegister(TRC);
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if (isThumb2) {
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AddDefaultPred(BuildMI(*BB, MI, dl,
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TII->get(ldrOpc),scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1));
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
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.addReg(scratch).addReg(destIn)
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.addReg(0).addImm(1));
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} else {
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AddDefaultPred(BuildMI(*BB, MI, dl,
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TII->get(ldrOpc),scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1));
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
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.addReg(scratch).addReg(destIn)
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.addReg(0).addImm(1));
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}
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srcIn = srcOut;
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destIn = destOut;
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}
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MI->eraseFromParent(); // The instruction is gone now.
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return BB;
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}
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// Expand the pseudo op to a loop.
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// thisMBB:
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// ...
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// movw varEnd, # --> with thumb2
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// movt varEnd, #
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// ldrcp varEnd, idx --> without thumb2
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// fallthrough --> loopMBB
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// loopMBB:
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// PHI varPhi, varEnd, varLoop
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// PHI srcPhi, src, srcLoop
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// PHI destPhi, dst, destLoop
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// [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
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// [destLoop] = STR_POST(scratch, destPhi, UnitSize)
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// subs varLoop, varPhi, #UnitSize
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// bne loopMBB
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// fallthrough --> exitMBB
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// exitMBB:
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// epilogue to handle left-over bytes
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// [scratch, srcOut] = LDRB_POST(srcLoop, 1)
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// [destOut] = STRB_POST(scratch, destLoop, 1)
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MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MF->insert(It, loopMBB);
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MF->insert(It, exitMBB);
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// Transfer the remainder of BB and its successor edges to exitMBB.
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exitMBB->splice(exitMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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exitMBB->transferSuccessorsAndUpdatePHIs(BB);
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// Load an immediate to varEnd.
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unsigned varEnd = MRI.createVirtualRegister(TRC);
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if (isThumb2) {
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unsigned VReg1 = varEnd;
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if ((LoopSize & 0xFFFF0000) != 0)
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VReg1 = MRI.createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), VReg1)
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.addImm(LoopSize & 0xFFFF));
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if ((LoopSize & 0xFFFF0000) != 0)
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
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.addReg(VReg1)
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.addImm(LoopSize >> 16));
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} else {
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MachineConstantPool *ConstantPool = MF->getConstantPool();
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Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
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const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
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// MachineConstantPool wants an explicit alignment.
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unsigned Align = getTargetData()->getPrefTypeAlignment(Int32Ty);
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if (Align == 0)
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Align = getTargetData()->getTypeAllocSize(C->getType());
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unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::LDRcp))
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.addReg(varEnd, RegState::Define)
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.addConstantPoolIndex(Idx)
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.addImm(0));
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}
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BB->addSuccessor(loopMBB);
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// Generate the loop body:
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// varPhi = PHI(varLoop, varEnd)
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// srcPhi = PHI(srcLoop, src)
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// destPhi = PHI(destLoop, dst)
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MachineBasicBlock *entryBB = BB;
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BB = loopMBB;
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unsigned varLoop = MRI.createVirtualRegister(TRC);
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unsigned varPhi = MRI.createVirtualRegister(TRC);
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unsigned srcLoop = MRI.createVirtualRegister(TRC);
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unsigned srcPhi = MRI.createVirtualRegister(TRC);
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unsigned destLoop = MRI.createVirtualRegister(TRC);
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unsigned destPhi = MRI.createVirtualRegister(TRC);
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BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
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.addReg(varLoop).addMBB(loopMBB)
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.addReg(varEnd).addMBB(entryBB);
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BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
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.addReg(srcLoop).addMBB(loopMBB)
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.addReg(src).addMBB(entryBB);
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BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
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.addReg(destLoop).addMBB(loopMBB)
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.addReg(dest).addMBB(entryBB);
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// [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
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// [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
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unsigned scratch = MRI.createVirtualRegister(TRC);
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if (isThumb2) {
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AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
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.addReg(srcLoop, RegState::Define).addReg(srcPhi).addImm(UnitSize));
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AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
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.addReg(scratch).addReg(destPhi)
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.addImm(UnitSize));
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} else {
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AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
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.addReg(srcLoop, RegState::Define).addReg(srcPhi).addReg(0)
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.addImm(UnitSize));
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AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
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.addReg(scratch).addReg(destPhi)
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.addReg(0).addImm(UnitSize));
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}
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// Decrement loop variable by UnitSize.
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MachineInstrBuilder MIB = BuildMI(BB, dl,
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TII->get(isThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
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AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
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MIB->getOperand(5).setReg(ARM::CPSR);
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MIB->getOperand(5).setIsDef(true);
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BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
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.addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
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// loopMBB can loop back to loopMBB or fall through to exitMBB.
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BB->addSuccessor(loopMBB);
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BB->addSuccessor(exitMBB);
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// Add epilogue to handle BytesLeft.
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BB = exitMBB;
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MachineInstr *StartOfExit = exitMBB->begin();
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ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM;
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strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM;
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// [scratch, srcOut] = LDRB_POST(srcLoop, 1)
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// [destOut] = STRB_POST(scratch, destLoop, 1)
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unsigned srcIn = srcLoop;
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unsigned destIn = destLoop;
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for (unsigned i = 0; i < BytesLeft; i++) {
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unsigned scratch = MRI.createVirtualRegister(TRC);
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unsigned srcOut = MRI.createVirtualRegister(TRC);
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unsigned destOut = MRI.createVirtualRegister(TRC);
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if (isThumb2) {
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AddDefaultPred(BuildMI(*BB, StartOfExit, dl,
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TII->get(ldrOpc),scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1));
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AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut)
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.addReg(scratch).addReg(destIn)
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.addImm(1));
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} else {
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AddDefaultPred(BuildMI(*BB, StartOfExit, dl,
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TII->get(ldrOpc),scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addReg(0).addImm(1));
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AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut)
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.addReg(scratch).addReg(destIn)
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.addReg(0).addImm(1));
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}
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srcIn = srcOut;
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destIn = destOut;
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}
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MI->eraseFromParent(); // The instruction is gone now.
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return BB;
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}
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MachineBasicBlock *
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ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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@ -6594,252 +6859,9 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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// return last added BB
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return SinkBB;
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}
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case ARM::COPY_STRUCT_BYVAL_I32: {
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case ARM::COPY_STRUCT_BYVAL_I32:
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++NumLoopByVals;
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// This pseudo instruction has 3 operands: dst, src, size
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// We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
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// Otherwise, we will generate unrolled scalar copies.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = BB;
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++It;
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unsigned dest = MI->getOperand(0).getReg();
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unsigned src = MI->getOperand(1).getReg();
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unsigned size = MI->getOperand(2).getImm();
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DebugLoc dl = MI->getDebugLoc();
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unsigned BytesLeft = size & 3;
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unsigned LoopSize = size - BytesLeft;
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bool isThumb2 = Subtarget->isThumb2();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned ldrOpc = isThumb2 ? ARM::t2LDR_POST : ARM::LDR_POST_IMM;
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unsigned strOpc = isThumb2 ? ARM::t2STR_POST : ARM::STR_POST_IMM;
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const TargetRegisterClass *TRC = isThumb2 ?
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(const TargetRegisterClass*)&ARM::tGPRRegClass :
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(const TargetRegisterClass*)&ARM::GPRRegClass;
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if (size <= Subtarget->getMaxInlineSizeThreshold()) {
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// Use LDR and STR to copy.
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// [scratch, srcOut] = LDR_POST(srcIn, 4)
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// [destOut] = STR_POST(scratch, destIn, 4)
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unsigned srcIn = src;
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unsigned destIn = dest;
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for (unsigned i = 0; i < LoopSize; i+=4) {
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unsigned scratch = MRI.createVirtualRegister(TRC);
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unsigned srcOut = MRI.createVirtualRegister(TRC);
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unsigned destOut = MRI.createVirtualRegister(TRC);
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if (isThumb2) {
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AddDefaultPred(BuildMI(*BB, MI, dl,
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TII->get(ldrOpc), scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addImm(4));
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
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.addReg(scratch).addReg(destIn)
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.addImm(4));
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} else {
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AddDefaultPred(BuildMI(*BB, MI, dl,
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TII->get(ldrOpc), scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addReg(0).addImm(4));
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
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.addReg(scratch).addReg(destIn)
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.addReg(0).addImm(4));
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}
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||||
srcIn = srcOut;
|
||||
destIn = destOut;
|
||||
}
|
||||
|
||||
// Handle the leftover bytes with LDRB and STRB.
|
||||
// [scratch, srcOut] = LDRB_POST(srcIn, 1)
|
||||
// [destOut] = STRB_POST(scratch, destIn, 1)
|
||||
ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM;
|
||||
strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM;
|
||||
for (unsigned i = 0; i < BytesLeft; i++) {
|
||||
unsigned scratch = MRI.createVirtualRegister(TRC);
|
||||
unsigned srcOut = MRI.createVirtualRegister(TRC);
|
||||
unsigned destOut = MRI.createVirtualRegister(TRC);
|
||||
if (isThumb2) {
|
||||
AddDefaultPred(BuildMI(*BB, MI, dl,
|
||||
TII->get(ldrOpc),scratch)
|
||||
.addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1));
|
||||
|
||||
AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
|
||||
.addReg(scratch).addReg(destIn)
|
||||
.addReg(0).addImm(1));
|
||||
} else {
|
||||
AddDefaultPred(BuildMI(*BB, MI, dl,
|
||||
TII->get(ldrOpc),scratch)
|
||||
.addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1));
|
||||
|
||||
AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
|
||||
.addReg(scratch).addReg(destIn)
|
||||
.addReg(0).addImm(1));
|
||||
}
|
||||
srcIn = srcOut;
|
||||
destIn = destOut;
|
||||
}
|
||||
MI->eraseFromParent(); // The instruction is gone now.
|
||||
return BB;
|
||||
}
|
||||
|
||||
// Expand the pseudo op to a loop.
|
||||
// thisMBB:
|
||||
// ...
|
||||
// movw varEnd, # --> with thumb2
|
||||
// movt varEnd, #
|
||||
// ldrcp varEnd, idx --> without thumb2
|
||||
// fallthrough --> loopMBB
|
||||
// loopMBB:
|
||||
// PHI varPhi, varEnd, varLoop
|
||||
// PHI srcPhi, src, srcLoop
|
||||
// PHI destPhi, dst, destLoop
|
||||
// [scratch, srcLoop] = LDR_POST(srcPhi, 4)
|
||||
// [destLoop] = STR_POST(scratch, destPhi, 4)
|
||||
// subs varLoop, varPhi, #4
|
||||
// bne loopMBB
|
||||
// fallthrough --> exitMBB
|
||||
// exitMBB:
|
||||
// epilogue to handle left-over bytes
|
||||
// [scratch, srcOut] = LDRB_POST(srcLoop, 1)
|
||||
// [destOut] = STRB_POST(scratch, destLoop, 1)
|
||||
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
||||
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
||||
MF->insert(It, loopMBB);
|
||||
MF->insert(It, exitMBB);
|
||||
|
||||
// Transfer the remainder of BB and its successor edges to exitMBB.
|
||||
exitMBB->splice(exitMBB->begin(), BB,
|
||||
llvm::next(MachineBasicBlock::iterator(MI)),
|
||||
BB->end());
|
||||
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
|
||||
|
||||
// Load an immediate to varEnd.
|
||||
unsigned varEnd = MRI.createVirtualRegister(TRC);
|
||||
if (isThumb2) {
|
||||
unsigned VReg1 = varEnd;
|
||||
if ((LoopSize & 0xFFFF0000) != 0)
|
||||
VReg1 = MRI.createVirtualRegister(TRC);
|
||||
AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), VReg1)
|
||||
.addImm(LoopSize & 0xFFFF));
|
||||
|
||||
if ((LoopSize & 0xFFFF0000) != 0)
|
||||
AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
|
||||
.addReg(VReg1)
|
||||
.addImm(LoopSize >> 16));
|
||||
} else {
|
||||
MachineConstantPool *ConstantPool = MF->getConstantPool();
|
||||
Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
|
||||
const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
|
||||
|
||||
// MachineConstantPool wants an explicit alignment.
|
||||
unsigned Align = getTargetData()->getPrefTypeAlignment(Int32Ty);
|
||||
if (Align == 0)
|
||||
Align = getTargetData()->getTypeAllocSize(C->getType());
|
||||
unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
|
||||
|
||||
AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::LDRcp))
|
||||
.addReg(varEnd, RegState::Define)
|
||||
.addConstantPoolIndex(Idx)
|
||||
.addImm(0));
|
||||
}
|
||||
BB->addSuccessor(loopMBB);
|
||||
|
||||
// Generate the loop body:
|
||||
// varPhi = PHI(varLoop, varEnd)
|
||||
// srcPhi = PHI(srcLoop, src)
|
||||
// destPhi = PHI(destLoop, dst)
|
||||
MachineBasicBlock *entryBB = BB;
|
||||
BB = loopMBB;
|
||||
unsigned varLoop = MRI.createVirtualRegister(TRC);
|
||||
unsigned varPhi = MRI.createVirtualRegister(TRC);
|
||||
unsigned srcLoop = MRI.createVirtualRegister(TRC);
|
||||
unsigned srcPhi = MRI.createVirtualRegister(TRC);
|
||||
unsigned destLoop = MRI.createVirtualRegister(TRC);
|
||||
unsigned destPhi = MRI.createVirtualRegister(TRC);
|
||||
|
||||
BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
|
||||
.addReg(varLoop).addMBB(loopMBB)
|
||||
.addReg(varEnd).addMBB(entryBB);
|
||||
BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
|
||||
.addReg(srcLoop).addMBB(loopMBB)
|
||||
.addReg(src).addMBB(entryBB);
|
||||
BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
|
||||
.addReg(destLoop).addMBB(loopMBB)
|
||||
.addReg(dest).addMBB(entryBB);
|
||||
|
||||
// [scratch, srcLoop] = LDR_POST(srcPhi, 4)
|
||||
// [destLoop] = STR_POST(scratch, destPhi, 4)
|
||||
unsigned scratch = MRI.createVirtualRegister(TRC);
|
||||
if (isThumb2) {
|
||||
AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
|
||||
.addReg(srcLoop, RegState::Define).addReg(srcPhi).addImm(4));
|
||||
|
||||
AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
|
||||
.addReg(scratch).addReg(destPhi)
|
||||
.addImm(4));
|
||||
} else {
|
||||
AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
|
||||
.addReg(srcLoop, RegState::Define).addReg(srcPhi).addReg(0).addImm(4));
|
||||
|
||||
AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
|
||||
.addReg(scratch).addReg(destPhi)
|
||||
.addReg(0).addImm(4));
|
||||
}
|
||||
|
||||
// Decrement loop variable by 4.
|
||||
MachineInstrBuilder MIB = BuildMI(BB, dl,
|
||||
TII->get(isThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
|
||||
AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(4)));
|
||||
MIB->getOperand(5).setReg(ARM::CPSR);
|
||||
MIB->getOperand(5).setIsDef(true);
|
||||
|
||||
BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
|
||||
.addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
|
||||
|
||||
// loopMBB can loop back to loopMBB or fall through to exitMBB.
|
||||
BB->addSuccessor(loopMBB);
|
||||
BB->addSuccessor(exitMBB);
|
||||
|
||||
// Add epilogue to handle BytesLeft.
|
||||
BB = exitMBB;
|
||||
MachineInstr *StartOfExit = exitMBB->begin();
|
||||
ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM;
|
||||
strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM;
|
||||
|
||||
// [scratch, srcOut] = LDRB_POST(srcLoop, 1)
|
||||
// [destOut] = STRB_POST(scratch, destLoop, 1)
|
||||
unsigned srcIn = srcLoop;
|
||||
unsigned destIn = destLoop;
|
||||
for (unsigned i = 0; i < BytesLeft; i++) {
|
||||
unsigned scratch = MRI.createVirtualRegister(TRC);
|
||||
unsigned srcOut = MRI.createVirtualRegister(TRC);
|
||||
unsigned destOut = MRI.createVirtualRegister(TRC);
|
||||
if (isThumb2) {
|
||||
AddDefaultPred(BuildMI(*BB, StartOfExit, dl,
|
||||
TII->get(ldrOpc),scratch)
|
||||
.addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1));
|
||||
|
||||
AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut)
|
||||
.addReg(scratch).addReg(destIn)
|
||||
.addImm(1));
|
||||
} else {
|
||||
AddDefaultPred(BuildMI(*BB, StartOfExit, dl,
|
||||
TII->get(ldrOpc),scratch)
|
||||
.addReg(srcOut, RegState::Define).addReg(srcIn).addReg(0).addImm(1));
|
||||
|
||||
AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut)
|
||||
.addReg(scratch).addReg(destIn)
|
||||
.addReg(0).addImm(1));
|
||||
}
|
||||
srcIn = srcOut;
|
||||
destIn = destOut;
|
||||
}
|
||||
|
||||
MI->eraseFromParent(); // The instruction is gone now.
|
||||
return BB;
|
||||
}
|
||||
return EmitStructByval(MI, BB);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -530,6 +530,9 @@ namespace llvm {
|
|||
MachineBasicBlock *MBB) const;
|
||||
|
||||
bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
|
||||
|
||||
MachineBasicBlock *EmitStructByval(MachineInstr *MI,
|
||||
MachineBasicBlock *MBB) const;
|
||||
};
|
||||
|
||||
enum NEONModImmType {
|
||||
|
|
|
|||
|
|
@ -18,9 +18,9 @@
|
|||
// Type profiles.
|
||||
def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
|
||||
def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
|
||||
def SDT_ARMStructByVal : SDTypeProfile<0, 3,
|
||||
def SDT_ARMStructByVal : SDTypeProfile<0, 4,
|
||||
[SDTCisVT<0, i32>, SDTCisVT<1, i32>,
|
||||
SDTCisVT<2, i32>]>;
|
||||
SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
|
||||
|
||||
def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
|
||||
|
||||
|
|
@ -4174,9 +4174,9 @@ let usesCustomInserter = 1 in {
|
|||
|
||||
let usesCustomInserter = 1 in {
|
||||
def COPY_STRUCT_BYVAL_I32 : PseudoInst<
|
||||
(outs), (ins GPR:$dst, GPR:$src, i32imm:$size),
|
||||
(outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
|
||||
NoItinerary,
|
||||
[(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size)]>;
|
||||
[(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
|
||||
}
|
||||
|
||||
let mayLoad = 1 in {
|
||||
|
|
|
|||
Loading…
Reference in New Issue