forked from OSchip/llvm-project
[PowerPC] Eliminate loads/swap feeding swap/store for vector type by using big-endian load/store
In PowerPC, there is instruction to load vector in big endian element order when it's in little endian target. So we can combine vector load + reverse into big endian load to eliminate the swap instruction. Also combine vector reverse + store into big endian store. llvm-svn: 367382
This commit is contained in:
Zi Xuan Wu
parent
2594fa8593
commit
e85f6bf66c
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@ -1118,6 +1118,8 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setTargetDAGCombine(ISD::ANY_EXTEND);
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setTargetDAGCombine(ISD::TRUNCATE);
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setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
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if (Subtarget.useCRBits()) {
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setTargetDAGCombine(ISD::TRUNCATE);
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@ -1352,6 +1354,8 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case PPCISD::SExtVElems: return "PPCISD::SExtVElems";
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case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
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case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
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case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE";
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case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE";
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case PPCISD::ST_VSR_SCAL_INT:
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return "PPCISD::ST_VSR_SCAL_INT";
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case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
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@ -13113,6 +13117,60 @@ SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N,
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return Val;
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}
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SDValue PPCTargetLowering::combineVReverseMemOP(ShuffleVectorSDNode *SVN,
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LSBaseSDNode *LSBase,
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DAGCombinerInfo &DCI) const {
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assert((ISD::isNormalLoad(LSBase) || ISD::isNormalStore(LSBase)) &&
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"Not a reverse memop pattern!");
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auto IsElementReverse = [](const ShuffleVectorSDNode *SVN) -> bool {
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auto Mask = SVN->getMask();
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int i = 0;
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auto I = Mask.rbegin();
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auto E = Mask.rend();
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for (; I != E; ++I) {
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if (*I != i)
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return false;
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i++;
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}
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return true;
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};
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SelectionDAG &DAG = DCI.DAG;
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EVT VT = SVN->getValueType(0);
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if (!isTypeLegal(VT) || !Subtarget.isLittleEndian() || !Subtarget.hasVSX())
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return SDValue();
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// Before P9, we don't have vector load/store instrs in big-endian
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// element order for v8i16 or v16i8
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if (!Subtarget.hasP9Vector() && (VT == MVT::v8i16 || VT == MVT::v16i8))
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return SDValue();
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if(!IsElementReverse(SVN))
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return SDValue();
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if (LSBase->getOpcode() == ISD::LOAD) {
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SDLoc dl(SVN);
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SDValue LoadOps[] = {LSBase->getChain(), LSBase->getBasePtr()};
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return DAG.getMemIntrinsicNode(
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PPCISD::LOAD_VEC_BE, dl, DAG.getVTList(VT, MVT::Other), LoadOps,
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LSBase->getMemoryVT(), LSBase->getMemOperand());
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}
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if (LSBase->getOpcode() == ISD::STORE) {
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SDLoc dl(LSBase);
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SDValue StoreOps[] = {LSBase->getChain(), SVN->getOperand(0),
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LSBase->getBasePtr()};
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return DAG.getMemIntrinsicNode(
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PPCISD::STORE_VEC_BE, dl, DAG.getVTList(MVT::Other), StoreOps,
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LSBase->getMemoryVT(), LSBase->getMemOperand());
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}
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llvm_unreachable("Expected a load or store node here");
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}
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SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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@ -13159,6 +13217,12 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP:
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return combineFPToIntToFP(N, DCI);
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case ISD::VECTOR_SHUFFLE:
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if (ISD::isNormalLoad(N->getOperand(0).getNode())) {
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LSBaseSDNode* LSBase = cast<LSBaseSDNode>(N->getOperand(0));
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return combineVReverseMemOP(cast<ShuffleVectorSDNode>(N), LSBase, DCI);
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}
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break;
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case ISD::STORE: {
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EVT Op1VT = N->getOperand(1).getValueType();
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@ -13170,6 +13234,13 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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return Val;
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}
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if (Opcode == ISD::VECTOR_SHUFFLE && ISD::isNormalStore(N)) {
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ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N->getOperand(1));
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SDValue Val= combineVReverseMemOP(SVN, cast<LSBaseSDNode>(N), DCI);
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if (Val)
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return Val;
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}
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// Turn STORE (BSWAP) -> sthbrx/stwbrx.
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if (cast<StoreSDNode>(N)->isUnindexed() && Opcode == ISD::BSWAP &&
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N->getOperand(1).getNode()->hasOneUse() &&
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@ -456,6 +456,11 @@ namespace llvm {
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/// an xxswapd.
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LXVD2X,
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/// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
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/// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on
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/// the vector type to load vector in big-endian element order.
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LOAD_VEC_BE,
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/// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a
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/// v2f32 value into the lower half of a VSR register.
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LD_VSX_LH,
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@ -465,6 +470,11 @@ namespace llvm {
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/// an xxswapd.
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STXVD2X,
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/// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
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/// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on
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/// the vector type to store vector in big-endian element order.
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STORE_VEC_BE,
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/// Store scalar integers from VSR.
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ST_VSR_SCAL_INT,
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@ -1167,6 +1177,8 @@ namespace llvm {
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SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase,
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DAGCombinerInfo &DCI) const;
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/// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
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/// SETCC with integer subtraction when (1) there is a legal way of doing it
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@ -78,12 +78,21 @@ def SDTVecConv : SDTypeProfile<1, 2, [
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def SDTVabsd : SDTypeProfile<1, 3, [
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SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<3, i32>
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]>;
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def SDT_PPCld_vec_be : SDTypeProfile<1, 1, [
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SDTCisVec<0>, SDTCisPtrTy<1>
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]>;
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def SDT_PPCst_vec_be : SDTypeProfile<0, 2, [
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SDTCisVec<0>, SDTCisPtrTy<1>
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]>;
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def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x,
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[SDNPHasChain, SDNPMayStore]>;
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def PPCld_vec_be : SDNode<"PPCISD::LOAD_VEC_BE", SDT_PPCld_vec_be,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def PPCst_vec_be : SDNode<"PPCISD::STORE_VEC_BE", SDT_PPCst_vec_be,
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[SDNPHasChain, SDNPMayStore]>;
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def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>;
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def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
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def PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>;
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@ -1088,6 +1097,19 @@ let Predicates = [HasVSX, HasOnlySwappingMemOps] in {
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(STXVD2X $rS, xoaddr:$dst)>;
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def : Pat<(PPCstxvd2x v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
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}
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// Load vector big endian order
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let Predicates = [IsLittleEndian, HasVSX] in {
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def : Pat<(v2f64 (PPCld_vec_be xoaddr:$src)), (LXVD2X xoaddr:$src)>;
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def : Pat<(PPCst_vec_be v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
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def : Pat<(v4f32 (PPCld_vec_be xoaddr:$src)), (LXVW4X xoaddr:$src)>;
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def : Pat<(PPCst_vec_be v4f32:$rS, xoaddr:$dst), (STXVW4X $rS, xoaddr:$dst)>;
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def : Pat<(v2i64 (PPCld_vec_be xoaddr:$src)), (LXVD2X xoaddr:$src)>;
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def : Pat<(PPCst_vec_be v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
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def : Pat<(v4i32 (PPCld_vec_be xoaddr:$src)), (LXVW4X xoaddr:$src)>;
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def : Pat<(PPCst_vec_be v4i32:$rS, xoaddr:$dst), (STXVW4X $rS, xoaddr:$dst)>;
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}
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let Predicates = [IsBigEndian, HasVSX, HasOnlySwappingMemOps] in {
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def : Pat<(v2f64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
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def : Pat<(v2i64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
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@ -3024,6 +3046,16 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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(v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>;
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def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)),
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(v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>;
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def : Pat<(v8i16 (PPCld_vec_be xoaddr:$src)),
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(COPY_TO_REGCLASS (LXVH8X xoaddr:$src), VRRC)>;
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def : Pat<(PPCst_vec_be v8i16:$rS, xoaddr:$dst),
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(STXVH8X (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$dst)>;
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def : Pat<(v16i8 (PPCld_vec_be xoaddr:$src)),
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(COPY_TO_REGCLASS (LXVB16X xoaddr:$src), VRRC)>;
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def : Pat<(PPCst_vec_be v16i8:$rS, xoaddr:$dst),
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(STXVB16X (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$dst)>;
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} // IsLittleEndian, HasP9Vector
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let Predicates = [IsBigEndian, HasP9Vector] in {
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@ -986,11 +986,7 @@ define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) {
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;
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; P9LE-LABEL: fromDiffMemConsDi:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: lxv v2, 0(r3)
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; P9LE-NEXT: addis r3, r2, .LCPI8_0@toc@ha
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; P9LE-NEXT: addi r3, r3, .LCPI8_0@toc@l
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; P9LE-NEXT: lxvx v3, 0, r3
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; P9LE-NEXT: vperm v2, v2, v2, v3
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; P9LE-NEXT: lxvw4x v2, 0, r3
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; P9LE-NEXT: blr
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;
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; P8BE-LABEL: fromDiffMemConsDi:
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@ -1004,12 +1000,7 @@ define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) {
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;
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; P8LE-LABEL: fromDiffMemConsDi:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: lxvd2x vs0, 0, r3
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; P8LE-NEXT: addis r4, r2, .LCPI8_0@toc@ha
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; P8LE-NEXT: addi r3, r4, .LCPI8_0@toc@l
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; P8LE-NEXT: lvx v2, 0, r3
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; P8LE-NEXT: xxswapd v3, vs0
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; P8LE-NEXT: vperm v2, v3, v3, v2
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; P8LE-NEXT: lxvw4x v2, 0, r3
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; P8LE-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds i32, i32* %arr, i64 3
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@ -2570,11 +2561,7 @@ define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) {
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;
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; P9LE-LABEL: fromDiffMemConsDui:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: lxv v2, 0(r3)
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; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha
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; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l
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; P9LE-NEXT: lxvx v3, 0, r3
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; P9LE-NEXT: vperm v2, v2, v2, v3
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; P9LE-NEXT: lxvw4x v2, 0, r3
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; P9LE-NEXT: blr
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;
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; P8BE-LABEL: fromDiffMemConsDui:
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@ -2588,12 +2575,7 @@ define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) {
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;
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; P8LE-LABEL: fromDiffMemConsDui:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: lxvd2x vs0, 0, r3
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; P8LE-NEXT: addis r4, r2, .LCPI41_0@toc@ha
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; P8LE-NEXT: addi r3, r4, .LCPI41_0@toc@l
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; P8LE-NEXT: lvx v2, 0, r3
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; P8LE-NEXT: xxswapd v3, vs0
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; P8LE-NEXT: vperm v2, v3, v3, v2
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; P8LE-NEXT: lxvw4x v2, 0, r3
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; P8LE-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds i32, i32* %arr, i64 3
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@ -4155,8 +4137,8 @@ define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) {
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;
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; P9LE-LABEL: fromDiffMemConsDll:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: lxv v2, 16(r3)
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; P9LE-NEXT: xxswapd v2, v2
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; P9LE-NEXT: addi r3, r3, 16
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; P9LE-NEXT: lxvd2x v2, 0, r3
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; P9LE-NEXT: blr
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;
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; P8BE-LABEL: fromDiffMemConsDll:
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@ -4235,9 +4217,8 @@ define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %e
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: sldi r4, r4, 3
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; P9LE-NEXT: add r3, r3, r4
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; P9LE-NEXT: li r4, -8
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; P9LE-NEXT: lxvx v2, r3, r4
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; P9LE-NEXT: xxswapd v2, v2
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; P9LE-NEXT: addi r3, r3, -8
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; P9LE-NEXT: lxvd2x v2, 0, r3
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; P9LE-NEXT: blr
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;
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; P8BE-LABEL: fromDiffMemVarDll:
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@ -4948,8 +4929,8 @@ define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) {
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;
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; P9LE-LABEL: fromDiffMemConsDConvdtoll:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: lxv vs0, 16(r3)
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; P9LE-NEXT: xxswapd vs0, vs0
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; P9LE-NEXT: addi r3, r3, 16
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; P9LE-NEXT: lxvd2x vs0, 0, r3
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; P9LE-NEXT: xvcvdpsxds v2, vs0
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; P9LE-NEXT: blr
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;
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@ -5040,9 +5021,8 @@ define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: sldi r4, r4, 3
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; P9LE-NEXT: add r3, r3, r4
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; P9LE-NEXT: li r4, -8
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; P9LE-NEXT: lxvx vs0, r3, r4
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; P9LE-NEXT: xxswapd vs0, vs0
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; P9LE-NEXT: addi r3, r3, -8
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; P9LE-NEXT: lxvd2x vs0, 0, r3
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; P9LE-NEXT: xvcvdpsxds v2, vs0
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; P9LE-NEXT: blr
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;
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@ -5402,8 +5382,8 @@ define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) {
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;
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; P9LE-LABEL: fromDiffMemConsDull:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: lxv v2, 16(r3)
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; P9LE-NEXT: xxswapd v2, v2
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; P9LE-NEXT: addi r3, r3, 16
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; P9LE-NEXT: lxvd2x v2, 0, r3
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; P9LE-NEXT: blr
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;
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; P8BE-LABEL: fromDiffMemConsDull:
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@ -5482,9 +5462,8 @@ define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: sldi r4, r4, 3
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; P9LE-NEXT: add r3, r3, r4
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; P9LE-NEXT: li r4, -8
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; P9LE-NEXT: lxvx v2, r3, r4
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; P9LE-NEXT: xxswapd v2, v2
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; P9LE-NEXT: addi r3, r3, -8
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; P9LE-NEXT: lxvd2x v2, 0, r3
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; P9LE-NEXT: blr
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;
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; P8BE-LABEL: fromDiffMemVarDull:
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|
|
@ -6195,8 +6174,8 @@ define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) {
|
|||
;
|
||||
; P9LE-LABEL: fromDiffMemConsDConvdtoull:
|
||||
; P9LE: # %bb.0: # %entry
|
||||
; P9LE-NEXT: lxv vs0, 16(r3)
|
||||
; P9LE-NEXT: xxswapd vs0, vs0
|
||||
; P9LE-NEXT: addi r3, r3, 16
|
||||
; P9LE-NEXT: lxvd2x vs0, 0, r3
|
||||
; P9LE-NEXT: xvcvdpuxds v2, vs0
|
||||
; P9LE-NEXT: blr
|
||||
;
|
||||
|
|
@ -6287,9 +6266,8 @@ define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32
|
|||
; P9LE: # %bb.0: # %entry
|
||||
; P9LE-NEXT: sldi r4, r4, 3
|
||||
; P9LE-NEXT: add r3, r3, r4
|
||||
; P9LE-NEXT: li r4, -8
|
||||
; P9LE-NEXT: lxvx vs0, r3, r4
|
||||
; P9LE-NEXT: xxswapd vs0, vs0
|
||||
; P9LE-NEXT: addi r3, r3, -8
|
||||
; P9LE-NEXT: lxvd2x vs0, 0, r3
|
||||
; P9LE-NEXT: xvcvdpuxds v2, vs0
|
||||
; P9LE-NEXT: blr
|
||||
;
|
||||
|
|
|
|||
|
|
@ -19,8 +19,7 @@ define <2 x i64> @load_swap00(<2 x i64>* %vp1, <2 x i64>* %vp2) {
|
|||
;
|
||||
; CHECK-P9-LABEL: load_swap00:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: lxv v2, 0(r3)
|
||||
; CHECK-P9-NEXT: xxswapd v2, v2
|
||||
; CHECK-P9-NEXT: lxvd2x v2, 0, r3
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: load_swap00:
|
||||
|
|
@ -48,8 +47,7 @@ define <2 x i64> @load_swap01(<2 x i64>* %vp1, <2 x i64>* %vp2) {
|
|||
;
|
||||
; CHECK-P9-LABEL: load_swap01:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: lxv v2, 0(r4)
|
||||
; CHECK-P9-NEXT: xxswapd v2, v2
|
||||
; CHECK-P9-NEXT: lxvd2x v2, 0, r4
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: load_swap01:
|
||||
|
|
@ -72,20 +70,12 @@ define <2 x i64> @load_swap01(<2 x i64>* %vp1, <2 x i64>* %vp2) {
|
|||
define <4 x i32> @load_swap10(<4 x i32>* %vp1, <4 x i32>* %vp2) {
|
||||
; CHECK-P8-LABEL: load_swap10:
|
||||
; CHECK-P8: # %bb.0:
|
||||
; CHECK-P8-NEXT: addis r4, r2, .LCPI2_0@toc@ha
|
||||
; CHECK-P8-NEXT: lvx v3, 0, r3
|
||||
; CHECK-P8-NEXT: addi r4, r4, .LCPI2_0@toc@l
|
||||
; CHECK-P8-NEXT: lvx v2, 0, r4
|
||||
; CHECK-P8-NEXT: vperm v2, v3, v3, v2
|
||||
; CHECK-P8-NEXT: lxvw4x v2, 0, r3
|
||||
; CHECK-P8-NEXT: blr
|
||||
;
|
||||
; CHECK-P9-LABEL: load_swap10:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: lxv v2, 0(r3)
|
||||
; CHECK-P9-NEXT: addis r3, r2, .LCPI2_0@toc@ha
|
||||
; CHECK-P9-NEXT: addi r3, r3, .LCPI2_0@toc@l
|
||||
; CHECK-P9-NEXT: lxvx v3, 0, r3
|
||||
; CHECK-P9-NEXT: vperm v2, v2, v2, v3
|
||||
; CHECK-P9-NEXT: lxvw4x v2, 0, r3
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: load_swap10:
|
||||
|
|
@ -114,20 +104,12 @@ define <4 x i32> @load_swap10(<4 x i32>* %vp1, <4 x i32>* %vp2) {
|
|||
define <4 x i32> @load_swap11(<4 x i32>* %vp1, <4 x i32>* %vp2) {
|
||||
; CHECK-P8-LABEL: load_swap11:
|
||||
; CHECK-P8: # %bb.0:
|
||||
; CHECK-P8-NEXT: addis r3, r2, .LCPI3_0@toc@ha
|
||||
; CHECK-P8-NEXT: lvx v3, 0, r4
|
||||
; CHECK-P8-NEXT: addi r3, r3, .LCPI3_0@toc@l
|
||||
; CHECK-P8-NEXT: lvx v2, 0, r3
|
||||
; CHECK-P8-NEXT: vperm v2, v3, v3, v2
|
||||
; CHECK-P8-NEXT: lxvw4x v2, 0, r4
|
||||
; CHECK-P8-NEXT: blr
|
||||
;
|
||||
; CHECK-P9-LABEL: load_swap11:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha
|
||||
; CHECK-P9-NEXT: addi r3, r3, .LCPI3_0@toc@l
|
||||
; CHECK-P9-NEXT: lxv v2, 0(r4)
|
||||
; CHECK-P9-NEXT: lxvx v3, 0, r3
|
||||
; CHECK-P9-NEXT: vperm v2, v2, v2, v3
|
||||
; CHECK-P9-NEXT: lxvw4x v2, 0, r4
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: load_swap11:
|
||||
|
|
@ -165,11 +147,7 @@ define <8 x i16> @load_swap20(<8 x i16>* %vp1, <8 x i16>* %vp2){
|
|||
;
|
||||
; CHECK-P9-LABEL: load_swap20:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: lxv v2, 0(r3)
|
||||
; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha
|
||||
; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l
|
||||
; CHECK-P9-NEXT: lxvx v3, 0, r3
|
||||
; CHECK-P9-NEXT: vperm v2, v2, v2, v3
|
||||
; CHECK-P9-NEXT: lxvh8x v2, 0, r3
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: load_swap20:
|
||||
|
|
@ -207,11 +185,7 @@ define <8 x i16> @load_swap21(<8 x i16>* %vp1, <8 x i16>* %vp2){
|
|||
;
|
||||
; CHECK-P9-LABEL: load_swap21:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha
|
||||
; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l
|
||||
; CHECK-P9-NEXT: lxv v2, 0(r4)
|
||||
; CHECK-P9-NEXT: lxvx v3, 0, r3
|
||||
; CHECK-P9-NEXT: vperm v2, v2, v2, v3
|
||||
; CHECK-P9-NEXT: lxvh8x v2, 0, r4
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: load_swap21:
|
||||
|
|
@ -249,8 +223,7 @@ define <16 x i8> @load_swap30(<16 x i8>* %vp1, <16 x i8>* %vp2){
|
|||
;
|
||||
; CHECK-P9-LABEL: load_swap30:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: lxv vs0, 0(r3)
|
||||
; CHECK-P9-NEXT: xxbrq v2, vs0
|
||||
; CHECK-P9-NEXT: lxvb16x v2, 0, r3
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: load_swap30:
|
||||
|
|
@ -285,8 +258,7 @@ define <16 x i8> @load_swap31(<16 x i8>* %vp1, <16 x i8>* %vp2){
|
|||
;
|
||||
; CHECK-P9-LABEL: load_swap31:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: lxv vs0, 0(r4)
|
||||
; CHECK-P9-NEXT: xxbrq v2, vs0
|
||||
; CHECK-P9-NEXT: lxvb16x v2, 0, r4
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: load_swap31:
|
||||
|
|
@ -317,8 +289,7 @@ define <2 x double> @load_swap40(<2 x double>* %vp1, <2 x double>* %vp2) {
|
|||
;
|
||||
; CHECK-P9-LABEL: load_swap40:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: lxv vs0, 0(r4)
|
||||
; CHECK-P9-NEXT: xxswapd v2, vs0
|
||||
; CHECK-P9-NEXT: lxvd2x v2, 0, r4
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: load_swap40:
|
||||
|
|
@ -341,20 +312,12 @@ define <2 x double> @load_swap40(<2 x double>* %vp1, <2 x double>* %vp2) {
|
|||
define <4 x float> @load_swap50(<4 x float>* %vp1, <4 x float>* %vp2) {
|
||||
; CHECK-P8-LABEL: load_swap50:
|
||||
; CHECK-P8: # %bb.0:
|
||||
; CHECK-P8-NEXT: addis r4, r2, .LCPI9_0@toc@ha
|
||||
; CHECK-P8-NEXT: lvx v3, 0, r3
|
||||
; CHECK-P8-NEXT: addi r4, r4, .LCPI9_0@toc@l
|
||||
; CHECK-P8-NEXT: lvx v2, 0, r4
|
||||
; CHECK-P8-NEXT: vperm v2, v3, v3, v2
|
||||
; CHECK-P8-NEXT: lxvw4x v2, 0, r3
|
||||
; CHECK-P8-NEXT: blr
|
||||
;
|
||||
; CHECK-P9-LABEL: load_swap50:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: lxv v2, 0(r3)
|
||||
; CHECK-P9-NEXT: addis r3, r2, .LCPI9_0@toc@ha
|
||||
; CHECK-P9-NEXT: addi r3, r3, .LCPI9_0@toc@l
|
||||
; CHECK-P9-NEXT: lxvx v3, 0, r3
|
||||
; CHECK-P9-NEXT: vperm v2, v2, v2, v3
|
||||
; CHECK-P9-NEXT: lxvw4x v2, 0, r3
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: load_swap50:
|
||||
|
|
@ -383,20 +346,12 @@ define <4 x float> @load_swap50(<4 x float>* %vp1, <4 x float>* %vp2) {
|
|||
define <4 x float> @load_swap51(<4 x float>* %vp1, <4 x float>* %vp2) {
|
||||
; CHECK-P8-LABEL: load_swap51:
|
||||
; CHECK-P8: # %bb.0:
|
||||
; CHECK-P8-NEXT: addis r3, r2, .LCPI10_0@toc@ha
|
||||
; CHECK-P8-NEXT: lvx v3, 0, r4
|
||||
; CHECK-P8-NEXT: addi r3, r3, .LCPI10_0@toc@l
|
||||
; CHECK-P8-NEXT: lvx v2, 0, r3
|
||||
; CHECK-P8-NEXT: vperm v2, v3, v3, v2
|
||||
; CHECK-P8-NEXT: lxvw4x v2, 0, r4
|
||||
; CHECK-P8-NEXT: blr
|
||||
;
|
||||
; CHECK-P9-LABEL: load_swap51:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: addis r3, r2, .LCPI10_0@toc@ha
|
||||
; CHECK-P9-NEXT: addi r3, r3, .LCPI10_0@toc@l
|
||||
; CHECK-P9-NEXT: lxv v2, 0(r4)
|
||||
; CHECK-P9-NEXT: lxvx v3, 0, r3
|
||||
; CHECK-P9-NEXT: vperm v2, v2, v2, v3
|
||||
; CHECK-P9-NEXT: lxvw4x v2, 0, r4
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: load_swap51:
|
||||
|
|
@ -430,8 +385,7 @@ define void @swap_store00(<2 x i64> %v1, <2 x i64> %v2, <2 x i64>* %vp) {
|
|||
;
|
||||
; CHECK-P9-LABEL: swap_store00:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: xxswapd vs0, v2
|
||||
; CHECK-P9-NEXT: stxv vs0, 0(r7)
|
||||
; CHECK-P9-NEXT: stxvd2x v2, 0, r7
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: swap_store00:
|
||||
|
|
@ -458,8 +412,7 @@ define void @swap_store01(<2 x i64> %v1, <2 x i64> %v2, <2 x i64>* %vp) {
|
|||
;
|
||||
; CHECK-P9-LABEL: swap_store01:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: xxswapd vs0, v3
|
||||
; CHECK-P9-NEXT: stxv vs0, 0(r7)
|
||||
; CHECK-P9-NEXT: stxvd2x v3, 0, r7
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: swap_store01:
|
||||
|
|
@ -481,20 +434,12 @@ define void @swap_store01(<2 x i64> %v1, <2 x i64> %v2, <2 x i64>* %vp) {
|
|||
define void @swap_store10(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) {
|
||||
; CHECK-P8-LABEL: swap_store10:
|
||||
; CHECK-P8: # %bb.0:
|
||||
; CHECK-P8-NEXT: addis r3, r2, .LCPI13_0@toc@ha
|
||||
; CHECK-P8-NEXT: addi r3, r3, .LCPI13_0@toc@l
|
||||
; CHECK-P8-NEXT: lvx v3, 0, r3
|
||||
; CHECK-P8-NEXT: vperm v2, v2, v2, v3
|
||||
; CHECK-P8-NEXT: stvx v2, 0, r7
|
||||
; CHECK-P8-NEXT: stxvw4x v2, 0, r7
|
||||
; CHECK-P8-NEXT: blr
|
||||
;
|
||||
; CHECK-P9-LABEL: swap_store10:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: addis r3, r2, .LCPI13_0@toc@ha
|
||||
; CHECK-P9-NEXT: addi r3, r3, .LCPI13_0@toc@l
|
||||
; CHECK-P9-NEXT: lxvx v3, 0, r3
|
||||
; CHECK-P9-NEXT: vperm v2, v2, v2, v3
|
||||
; CHECK-P9-NEXT: stxv v2, 0(r7)
|
||||
; CHECK-P9-NEXT: stxvw4x v2, 0, r7
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: swap_store10:
|
||||
|
|
@ -522,20 +467,12 @@ define void @swap_store10(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) {
|
|||
define void @swap_store11(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) {
|
||||
; CHECK-P8-LABEL: swap_store11:
|
||||
; CHECK-P8: # %bb.0:
|
||||
; CHECK-P8-NEXT: addis r3, r2, .LCPI14_0@toc@ha
|
||||
; CHECK-P8-NEXT: addi r3, r3, .LCPI14_0@toc@l
|
||||
; CHECK-P8-NEXT: lvx v2, 0, r3
|
||||
; CHECK-P8-NEXT: vperm v2, v3, v3, v2
|
||||
; CHECK-P8-NEXT: stvx v2, 0, r7
|
||||
; CHECK-P8-NEXT: stxvw4x v3, 0, r7
|
||||
; CHECK-P8-NEXT: blr
|
||||
;
|
||||
; CHECK-P9-LABEL: swap_store11:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: addis r3, r2, .LCPI14_0@toc@ha
|
||||
; CHECK-P9-NEXT: addi r3, r3, .LCPI14_0@toc@l
|
||||
; CHECK-P9-NEXT: lxvx v2, 0, r3
|
||||
; CHECK-P9-NEXT: vperm v2, v3, v3, v2
|
||||
; CHECK-P9-NEXT: stxv v2, 0(r7)
|
||||
; CHECK-P9-NEXT: stxvw4x v3, 0, r7
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: swap_store11:
|
||||
|
|
@ -572,11 +509,7 @@ define void @swap_store20(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) {
|
|||
;
|
||||
; CHECK-P9-LABEL: swap_store20:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha
|
||||
; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l
|
||||
; CHECK-P9-NEXT: lxvx v3, 0, r3
|
||||
; CHECK-P9-NEXT: vperm v2, v2, v2, v3
|
||||
; CHECK-P9-NEXT: stxv v2, 0(r7)
|
||||
; CHECK-P9-NEXT: stxvh8x v2, 0, r7
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: swap_store20:
|
||||
|
|
@ -613,11 +546,7 @@ define void @swap_store21(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) {
|
|||
;
|
||||
; CHECK-P9-LABEL: swap_store21:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha
|
||||
; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l
|
||||
; CHECK-P9-NEXT: lxvx v2, 0, r3
|
||||
; CHECK-P9-NEXT: vperm v2, v3, v3, v2
|
||||
; CHECK-P9-NEXT: stxv v2, 0(r7)
|
||||
; CHECK-P9-NEXT: stxvh8x v3, 0, r7
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: swap_store21:
|
||||
|
|
@ -654,8 +583,7 @@ define void @swap_store30(<16 x i8> %v1, <16 x i8> %v2, <16 x i8>* %vp) {
|
|||
;
|
||||
; CHECK-P9-LABEL: swap_store30:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: xxbrq vs0, v2
|
||||
; CHECK-P9-NEXT: stxv vs0, 0(r7)
|
||||
; CHECK-P9-NEXT: stxvb16x v2, 0, r7
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: swap_store30:
|
||||
|
|
@ -689,8 +617,7 @@ define void @swap_store31(<16 x i8> %v1, <16 x i8> %v2, <16 x i8>* %vp) {
|
|||
;
|
||||
; CHECK-P9-LABEL: swap_store31:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: xxbrq vs0, v3
|
||||
; CHECK-P9-NEXT: stxv vs0, 0(r7)
|
||||
; CHECK-P9-NEXT: stxvb16x v3, 0, r7
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: swap_store31:
|
||||
|
|
@ -720,8 +647,7 @@ define void @swap_store40(<2 x double> %v1, <2 x double> %v2, <2 x double>* %vp)
|
|||
;
|
||||
; CHECK-P9-LABEL: swap_store40:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: xxswapd vs0, v2
|
||||
; CHECK-P9-NEXT: stxv vs0, 0(r7)
|
||||
; CHECK-P9-NEXT: stxvd2x v2, 0, r7
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: swap_store40:
|
||||
|
|
@ -748,8 +674,7 @@ define void @swap_store41(<2 x double> %v1, <2 x double> %v2, <2 x double>* %vp)
|
|||
;
|
||||
; CHECK-P9-LABEL: swap_store41:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: xxswapd vs0, v3
|
||||
; CHECK-P9-NEXT: stxv vs0, 0(r7)
|
||||
; CHECK-P9-NEXT: stxvd2x v3, 0, r7
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: swap_store41:
|
||||
|
|
@ -771,20 +696,12 @@ define void @swap_store41(<2 x double> %v1, <2 x double> %v2, <2 x double>* %vp)
|
|||
define void @swap_store50(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) {
|
||||
; CHECK-P8-LABEL: swap_store50:
|
||||
; CHECK-P8: # %bb.0:
|
||||
; CHECK-P8-NEXT: addis r3, r2, .LCPI21_0@toc@ha
|
||||
; CHECK-P8-NEXT: addi r3, r3, .LCPI21_0@toc@l
|
||||
; CHECK-P8-NEXT: lvx v3, 0, r3
|
||||
; CHECK-P8-NEXT: vperm v2, v2, v2, v3
|
||||
; CHECK-P8-NEXT: stvx v2, 0, r7
|
||||
; CHECK-P8-NEXT: stxvw4x v2, 0, r7
|
||||
; CHECK-P8-NEXT: blr
|
||||
;
|
||||
; CHECK-P9-LABEL: swap_store50:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: addis r3, r2, .LCPI21_0@toc@ha
|
||||
; CHECK-P9-NEXT: addi r3, r3, .LCPI21_0@toc@l
|
||||
; CHECK-P9-NEXT: lxvx v3, 0, r3
|
||||
; CHECK-P9-NEXT: vperm v2, v2, v2, v3
|
||||
; CHECK-P9-NEXT: stxv v2, 0(r7)
|
||||
; CHECK-P9-NEXT: stxvw4x v2, 0, r7
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: swap_store50:
|
||||
|
|
@ -812,20 +729,12 @@ define void @swap_store50(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) {
|
|||
define void @swap_store51(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) {
|
||||
; CHECK-P8-LABEL: swap_store51:
|
||||
; CHECK-P8: # %bb.0:
|
||||
; CHECK-P8-NEXT: addis r3, r2, .LCPI22_0@toc@ha
|
||||
; CHECK-P8-NEXT: addi r3, r3, .LCPI22_0@toc@l
|
||||
; CHECK-P8-NEXT: lvx v2, 0, r3
|
||||
; CHECK-P8-NEXT: vperm v2, v3, v3, v2
|
||||
; CHECK-P8-NEXT: stvx v2, 0, r7
|
||||
; CHECK-P8-NEXT: stxvw4x v3, 0, r7
|
||||
; CHECK-P8-NEXT: blr
|
||||
;
|
||||
; CHECK-P9-LABEL: swap_store51:
|
||||
; CHECK-P9: # %bb.0:
|
||||
; CHECK-P9-NEXT: addis r3, r2, .LCPI22_0@toc@ha
|
||||
; CHECK-P9-NEXT: addi r3, r3, .LCPI22_0@toc@l
|
||||
; CHECK-P9-NEXT: lxvx v2, 0, r3
|
||||
; CHECK-P9-NEXT: vperm v2, v3, v3, v2
|
||||
; CHECK-P9-NEXT: stxv v2, 0(r7)
|
||||
; CHECK-P9-NEXT: stxvw4x v3, 0, r7
|
||||
; CHECK-P9-NEXT: blr
|
||||
;
|
||||
; CHECK-P8-BE-LABEL: swap_store51:
|
||||
|
|
|
|||
|
|
@ -85,8 +85,7 @@ define <2 x double> @test10(<2 x double>* %p1, <2 x double>* %p2) {
|
|||
; CHECK: lxvd2x 34, 0, 3
|
||||
|
||||
; CHECK-P9-LABEL: @test10
|
||||
; CHECK-P9: lxv 0, 0(3)
|
||||
; CHECK-P9: xxswapd 34, 0
|
||||
; CHECK-P9: lxvd2x 34, 0, 3
|
||||
}
|
||||
|
||||
define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
|
|
@ -257,8 +256,7 @@ define <2 x double> @test32(<2 x double>* %p1, <2 x double>* %p2) {
|
|||
; CHECK: lxvd2x 34, 0, 4
|
||||
|
||||
; CHECK-P9-LABEL: @test32
|
||||
; CHECK-P9: lxv 0, 0(4)
|
||||
; CHECK-P9: xxswapd 34, 0
|
||||
; CHECK-P9: lxvd2x 34, 0, 4
|
||||
}
|
||||
|
||||
define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue