forked from OSchip/llvm-project
[AMDGPU] Fix dwordx3/southern-islands failures.
This commit fixes the dwordx3/southern-islands failures that were found in bugzilla https://bugs.llvm.org/show_bug.cgi?id=40129, by not generating the dwordx3 variants of load/store instructions that were added to the ISA after southern islands. Differential Revision: https://reviews.llvm.org/D56434 llvm-svn: 350838
This commit is contained in:
Neil Henning
parent
57f2c14860
commit
e85d45a699
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@ -822,6 +822,11 @@ public:
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return getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS;
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}
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// \returns true if the subtarget supports DWORDX3 load/store instructions.
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bool hasDwordx3LoadStores() const {
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return CIInsts;
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}
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bool hasSMovFedHazard() const {
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return getGeneration() >= AMDGPUSubtarget::GFX9;
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}
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@ -160,7 +160,7 @@ private:
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bool OptimizeAgain;
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static bool offsetsCanBeCombined(CombineInfo &CI);
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static bool widthsFit(const CombineInfo &CI);
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static bool widthsFit(const GCNSubtarget &STM, const CombineInfo &CI);
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static unsigned getNewOpcode(const CombineInfo &CI);
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static std::pair<unsigned, unsigned> getSubRegIdxs(const CombineInfo &CI);
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const TargetRegisterClass *getTargetRegisterClass(const CombineInfo &CI);
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@ -367,11 +367,12 @@ bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI) {
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return false;
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}
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bool SILoadStoreOptimizer::widthsFit(const CombineInfo &CI) {
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bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM,
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const CombineInfo &CI) {
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const unsigned Width = (CI.Width0 + CI.Width1);
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switch (CI.InstClass) {
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default:
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return Width <= 4;
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return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3));
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case S_BUFFER_LOAD_IMM:
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switch (Width) {
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default:
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@ -645,7 +646,7 @@ bool SILoadStoreOptimizer::findMatchingInst(CombineInfo &CI) {
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// We also need to go through the list of instructions that we plan to
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// move and make sure they are all safe to move down past the merged
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// instruction.
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if (widthsFit(CI) && offsetsCanBeCombined(CI))
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if (widthsFit(*STM, CI) && offsetsCanBeCombined(CI))
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if (canMoveInstsAcrossMemOp(*MBBI, CI.InstsToMove, TII, AA))
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return true;
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}
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@ -37,9 +37,10 @@ define amdgpu_kernel void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias
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; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]]
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; GCN-NOT: v_cvt_f32_ubyte3_e32
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; GCN-DAG: v_cvt_f32_ubyte2_e32 v[[HIRESULT:[0-9]+]], [[VAL]]
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; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, [[VAL]]
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; GCN-DAG: v_cvt_f32_ubyte1_e32 v[[MDRESULT:[0-9]+]], [[VAL]]
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; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[VAL]]
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; GCN: buffer_store_dwordx3 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
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; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[MDRESULT]]{{\]}},
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; VI: buffer_store_dwordx3 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
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define amdgpu_kernel void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> addrspace(1)* noalias %in) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %in, i32 %tid
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@ -60,7 +60,8 @@ endif:
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; GCN-DAG: buffer_store_dwordx3
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; GCN-DAG: buffer_store_dword v
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; GCN-DAG: buffer_store_dwordx2
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle96(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(1)* %in, float %cnd) #0 {
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entry:
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%v = load <3 x i32>, <3 x i32> addrspace(1)* %in
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@ -195,7 +195,7 @@ main_body:
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;CHECK-LABEL: {{^}}buffer_load_x3_offen_merged:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_dwordx3 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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;VI-NEXT: buffer_load_dwordx3 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x3_offen_merged(<4 x i32> inreg %rsrc, i32 %a) {
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main_body:
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@ -245,7 +245,7 @@ main_body:
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;CHECK-LABEL: {{^}}buffer_load_x3_offset_merged:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_dwordx3 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4
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;VI-NEXT: buffer_load_dwordx3 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x3_offset_merged(<4 x i32> inreg %rsrc) {
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main_body:
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@ -1,5 +1,5 @@
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs -amdgpu-load-store-vectorizer=0 < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=GCN-AA %s
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; This test is mostly to test DAG store merging, so disable the vectorizer.
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; Run with devices with different unaligned load restrictions.
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@ -65,8 +65,8 @@ define amdgpu_kernel void @merge_global_store_2_constants_i16_natural_align(i16
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}
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; GCN-LABEL: {{^}}merge_global_store_2_constants_i32:
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; SI-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0x1c8
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; SI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7b
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; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0x1c8
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; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7b
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; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
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define amdgpu_kernel void @merge_global_store_2_constants_i32(i32 addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
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@ -87,8 +87,8 @@ define amdgpu_kernel void @merge_global_store_2_constants_i32_f32(i32 addrspace(
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}
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; GCN-LABEL: {{^}}merge_global_store_2_constants_f32_i32:
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; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], 4.0
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; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], 0x7b
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; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], 4.0
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; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], 0x7b
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; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}}
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define amdgpu_kernel void @merge_global_store_2_constants_f32_i32(float addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1
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@ -164,9 +164,10 @@ define amdgpu_kernel void @merge_global_store_4_constants_mixed_i32_f32(float ad
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}
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; GCN-LABEL: {{^}}merge_global_store_3_constants_i32:
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; SI-DAG: buffer_store_dwordx3
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; SI-NOT: buffer_store_dwordx2
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; SI-NOT: buffer_store_dword
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; SI-DAG: buffer_store_dwordx2
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; SI-DAG: buffer_store_dword v
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; CI-DAG: buffer_store_dwordx3
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; GCN-NOT: buffer_store_dword
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; GCN: s_endpgm
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define amdgpu_kernel void @merge_global_store_3_constants_i32(i32 addrspace(1)* %out) #0 {
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%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
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@ -274,9 +275,13 @@ define amdgpu_kernel void @merge_global_store_4_adjacent_loads_i32(i32 addrspace
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}
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; GCN-LABEL: {{^}}merge_global_store_3_adjacent_loads_i32:
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; SI-DAG: buffer_load_dwordx3
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; SI-DAG: buffer_load_dwordx2
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; SI-DAG: buffer_load_dword v
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; CI-DAG: buffer_load_dwordx3
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; GCN: s_waitcnt
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; SI-DAG: buffer_store_dwordx3 v
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; SI-DAG: buffer_store_dwordx2
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; SI-DAG: buffer_store_dword v
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; CI-DAG: buffer_store_dwordx3
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; GCN: s_endpgm
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define amdgpu_kernel void @merge_global_store_3_adjacent_loads_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
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%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
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@ -561,7 +566,9 @@ define amdgpu_kernel void @merge_global_store_6_constants_i32(i32 addrspace(1)*
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; GCN-LABEL: {{^}}merge_global_store_7_constants_i32:
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; GCN: buffer_store_dwordx4
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; GCN: buffer_store_dwordx3
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; SI: buffer_store_dwordx2
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; SI: buffer_store_dword v
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; CI: buffer_store_dwordx3
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define amdgpu_kernel void @merge_global_store_7_constants_i32(i32 addrspace(1)* %out) {
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store i32 34, i32 addrspace(1)* %out, align 4
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%idx1 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 1
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@ -608,11 +615,15 @@ define amdgpu_kernel void @merge_global_store_8_constants_i32(i32 addrspace(1)*
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; GCN-LABEL: {{^}}copy_v3i32_align4:
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; GCN-NOT: SCRATCH_RSRC_DWORD
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; GCN-DAG: buffer_load_dwordx3 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; SI-DAG: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8
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; SI-DAG: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; CI-DAG: buffer_load_dwordx3 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GCN-NOT: offen
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; GCN: s_waitcnt vmcnt
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; GCN-NOT: offen
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; GCN-DAG: buffer_store_dwordx3 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; SI-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; SI-DAG: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8
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; CI-DAG: buffer_store_dwordx3 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GCN: ScratchSize: 0{{$}}
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define amdgpu_kernel void @copy_v3i32_align4(<3 x i32> addrspace(1)* noalias %out, <3 x i32> addrspace(1)* noalias %in) #0 {
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@ -639,11 +650,15 @@ define amdgpu_kernel void @copy_v3i64_align4(<3 x i64> addrspace(1)* noalias %ou
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; GCN-LABEL: {{^}}copy_v3f32_align4:
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; GCN-NOT: SCRATCH_RSRC_DWORD
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; GCN-DAG: buffer_load_dwordx3 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; SI-DAG: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8
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; SI-DAG: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; CI-DAG: buffer_load_dwordx3 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GCN-NOT: offen
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; GCN: s_waitcnt vmcnt
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; GCN-NOT: offen
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; GCN-DAG: buffer_store_dwordx3 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; SI-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; SI-DAG: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8
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; CI-DAG: buffer_store_dwordx3 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GCN: ScratchSize: 0{{$}}
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define amdgpu_kernel void @copy_v3f32_align4(<3 x float> addrspace(1)* noalias %out, <3 x float> addrspace(1)* noalias %in) #0 {
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%vec = load <3 x float>, <3 x float> addrspace(1)* %in, align 4
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@ -1,5 +1,5 @@
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; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=VI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
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@ -273,7 +273,10 @@ entry:
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}
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; FUNC-LABEL: {{^}}store_v3i32:
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; SIVI-DAG: buffer_store_dwordx3
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; SI-DAG: buffer_store_dwordx2
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; SI-DAG: buffer_store_dword v
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; VI-DAG: buffer_store_dwordx3
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; GFX9-DAG: global_store_dwordx2
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; GFX9-DAG: global_store_dword v
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@ -89,7 +89,9 @@ define amdgpu_kernel void @local_store_v3i64_unaligned(<3 x i64> addrspace(3)* %
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}
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; GCN-LABEL: {{^}}global_truncstore_v3i64_to_v3i32:
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; GCN-DAG: buffer_store_dwordx3
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; SI-DAG: buffer_store_dwordx2
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; SI-DAG: buffer_store_dword v
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; VI-DAG: buffer_store_dwordx3
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define amdgpu_kernel void @global_truncstore_v3i64_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i64> %x) {
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%trunc = trunc <3 x i64> %x to <3 x i32>
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store <3 x i32> %trunc, <3 x i32> addrspace(1)* %out
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