forked from OSchip/llvm-project
Add Def/Use of CPSR for Thumb-1 instructions.
llvm-svn: 74219
This commit is contained in:
David Goodwin
parent
4a5a561a24
commit
e85169cd1b
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@ -294,103 +294,134 @@ def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops),
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// Arithmetic Instructions.
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//
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// Add with carry
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let isCommutable = 1 in
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def tADC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"adc $dst, $rhs",
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[(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
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def tADDS : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"add $dst, $lhs, $rhs",
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[(set tGPR:$dst, (addc tGPR:$lhs, tGPR:$rhs))]>;
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// Add with carry register
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let isCommutable = 1, Defs = [CPSR], Uses = [CPSR] in
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def tADCS : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"adc $dst, $rhs",
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[(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
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// Add immediate
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let Defs = [CPSR] in {
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def tADDi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"add $dst, $lhs, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
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def tADDSi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"add $dst, $lhs, $rhs",
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[(set tGPR:$dst, (addc tGPR:$lhs, imm0_7:$rhs))]>;
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}
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let Defs = [CPSR] in {
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def tADDi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"add $dst, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
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def tADDSi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"add $dst, $rhs",
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[(set tGPR:$dst, (addc tGPR:$lhs, imm8_255:$rhs))]>;
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}
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// Add register
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let isCommutable = 1, Defs = [CPSR] in {
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def tADDrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"add $dst, $lhs, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
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def tADDSrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"add $dst, $lhs, $rhs",
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[(set tGPR:$dst, (addc tGPR:$lhs, tGPR:$rhs))]>;
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}
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let neverHasSideEffects = 1 in
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def tADDhirr : T1It<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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"add $dst, $rhs @ addhirr", []>;
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let isCommutable = 1 in
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// And register
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let isCommutable = 1, Defs = [CPSR] in
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def tAND : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"and $dst, $rhs",
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[(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
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// ASR immediate
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let Defs = [CPSR] in
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def tASRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"asr $dst, $lhs, $rhs",
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[(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
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// ASR register
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let Defs = [CPSR] in
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def tASRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"asr $dst, $rhs",
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[(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
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// BIC register
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let Defs = [CPSR] in
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def tBIC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"bic $dst, $rhs",
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[(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
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// CMN register
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let Defs = [CPSR] in {
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def tCMN : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"cmn $lhs, $rhs",
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[(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
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def tCMPi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
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def tCMPr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
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def tTST : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"tst $lhs, $rhs",
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[(ARMcmpNZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
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def tCMNNZ : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"cmn $lhs, $rhs",
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[(ARMcmpNZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
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}
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// CMP immediate
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let Defs = [CPSR] in {
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def tCMPi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
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def tCMPNZi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmpNZ tGPR:$lhs, imm0_255:$rhs)]>;
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}
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// CMP register
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let Defs = [CPSR] in {
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def tCMPr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
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def tCMPNZr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmpNZ tGPR:$lhs, tGPR:$rhs)]>;
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}
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// TODO: A7-37: CMP(3) - cmp hi regs
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let isCommutable = 1 in
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// XOR register
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let isCommutable = 1, Defs = [CPSR] in
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def tEOR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"eor $dst, $rhs",
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[(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
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// LSL immediate
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let Defs = [CPSR] in
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def tLSLri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"lsl $dst, $lhs, $rhs",
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[(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
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// LSL register
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let Defs = [CPSR] in
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def tLSLrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"lsl $dst, $rhs",
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[(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
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// LSR immediate
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let Defs = [CPSR] in
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def tLSRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"lsr $dst, $lhs, $rhs",
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[(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
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// LSR register
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let Defs = [CPSR] in
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def tLSRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"lsr $dst, $rhs",
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[(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
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// FIXME: This is not rematerializable because mov changes the condition code.
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// move register
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let Defs = [CPSR] in
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def tMOVi8 : T1I<(outs tGPR:$dst), (ins i32imm:$src),
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"mov $dst, $src",
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[(set tGPR:$dst, imm0_255:$src)]>;
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@ -411,25 +442,31 @@ def tMOVhir2hir : T1I<(outs GPR:$dst), (ins GPR:$src),
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"cpy $dst, $src\t@ hir2hir", []>;
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} // neverHasSideEffects
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let isCommutable = 1 in
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// multiply register
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let isCommutable = 1, Defs = [CPSR] in
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def tMUL : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"mul $dst, $rhs",
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[(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
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// move inverse register
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let Defs = [CPSR] in
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def tMVN : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"mvn $dst, $src",
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[(set tGPR:$dst, (not tGPR:$src))]>;
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// negate register
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let Defs = [CPSR] in
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def tNEG : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"neg $dst, $src",
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[(set tGPR:$dst, (ineg tGPR:$src))]>;
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let isCommutable = 1 in
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// bitwise or register
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let isCommutable = 1, Defs = [CPSR] in
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def tORR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"orr $dst, $rhs",
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[(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
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// swaps
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def tREV : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"rev $dst, $src",
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[(set tGPR:$dst, (bswap tGPR:$src))]>,
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@ -452,52 +489,77 @@ def tREVSH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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(shl tGPR:$src, (i32 8))), i16))]>,
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Requires<[IsThumb, HasV6]>;
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// rotate right register
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let Defs = [CPSR] in
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def tROR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"ror $dst, $rhs",
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[(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
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// Subtract with carry
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def tSBC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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// Subtract with carry register
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let Defs = [CPSR], Uses = [CPSR] in
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def tSBCS : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"sbc $dst, $rhs",
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[(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
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def tSUBS : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"sub $dst, $lhs, $rhs",
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[(set tGPR:$dst, (subc tGPR:$lhs, tGPR:$rhs))]>;
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// TODO: A7-96: STMIA - store multiple.
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// Subtract immediate
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let Defs = [CPSR] in {
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def tSUBi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"sub $dst, $lhs, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
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def tSUBSi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"sub $dst, $lhs, $rhs",
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[(set tGPR:$dst, (addc tGPR:$lhs, imm0_7_neg:$rhs))]>;
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}
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let Defs = [CPSR] in {
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def tSUBi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"sub $dst, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
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def tSUBSi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"sub $dst, $rhs",
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[(set tGPR:$dst, (addc tGPR:$lhs, imm8_255_neg:$rhs))]>;
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}
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// subtract register
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let Defs = [CPSR] in {
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def tSUBrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"sub $dst, $lhs, $rhs",
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[(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
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def tSUBSrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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"sub $dst, $lhs, $rhs",
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[(set tGPR:$dst, (subc tGPR:$lhs, tGPR:$rhs))]>;
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}
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// TODO: A7-96: STMIA - store multiple.
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def tSUBspi : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
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"sub $dst, $rhs * 4", []>;
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// sign-extend byte
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def tSXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"sxtb $dst, $src",
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[(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
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Requires<[IsThumb, HasV6]>;
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// sign-extend short
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def tSXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"sxth $dst, $src",
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[(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
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Requires<[IsThumb, HasV6]>;
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// test
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let Defs = [CPSR] in
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def tTST : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
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"tst $lhs, $rhs",
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[(ARMcmpNZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
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// zero-extend byte
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def tUXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"uxtb $dst, $src",
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[(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
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Requires<[IsThumb, HasV6]>;
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// zero-extend short
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def tUXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
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"uxth $dst, $src",
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[(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
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