forked from OSchip/llvm-project
GlobalISel: Make buildExtract use DstOp/SrcOp
llvm-svn: 354292
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cd8607db2d
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@ -655,7 +655,7 @@ public:
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/// \pre \p Res and \p Src must be generic virtual registers.
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///
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/// \return a MachineInstrBuilder for the newly created instruction.
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MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index);
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MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
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/// Build and insert \p Res = IMPLICIT_DEF.
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MachineInstrBuilder buildUndef(const DstOp &Res);
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@ -452,26 +452,29 @@ MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
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return buildInstr(Opcode, Dst, Src);
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}
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MachineInstrBuilder MachineIRBuilder::buildExtract(unsigned Res, unsigned Src,
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MachineInstrBuilder MachineIRBuilder::buildExtract(const DstOp &Dst,
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const SrcOp &Src,
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uint64_t Index) {
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LLT SrcTy = Src.getLLTTy(*getMRI());
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LLT DstTy = Dst.getLLTTy(*getMRI());
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#ifndef NDEBUG
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assert(getMRI()->getType(Src).isValid() && "invalid operand type");
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assert(getMRI()->getType(Res).isValid() && "invalid operand type");
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assert(Index + getMRI()->getType(Res).getSizeInBits() <=
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getMRI()->getType(Src).getSizeInBits() &&
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assert(SrcTy.isValid() && "invalid operand type");
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assert(DstTy.isValid() && "invalid operand type");
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assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
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"extracting off end of register");
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#endif
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if (getMRI()->getType(Res).getSizeInBits() ==
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getMRI()->getType(Src).getSizeInBits()) {
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if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
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assert(Index == 0 && "insertion past the end of a register");
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return buildCast(Res, Src);
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return buildCast(Dst, Src);
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}
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return buildInstr(TargetOpcode::G_EXTRACT)
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.addDef(Res)
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.addUse(Src)
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.addImm(Index);
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auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
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Dst.addDefToMIB(*getMRI(), Extract);
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Src.addSrcToMIB(Extract);
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Extract.addImm(Index);
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return Extract;
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}
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void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
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