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tidy up a bit. no functional change. 

llvm-svn: 112228
This commit is contained in:
Jim Grosbach 2010-08-26 21:56:30 +00:00
parent d4ebd6df5a
commit e82d5b4aaf
3 changed files with 12 additions and 32 deletions
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3
llvm/include/llvm/Target/TargetRegisterInfo.h
View File

@ -645,7 +645,8 @@ public:
/// getFrameIndexInstrOffset - Get the offset from the referenced frame
/// index in the instruction, if the is one.
virtual int64_t getFrameIndexInstrOffset(MachineInstr *MI, int Idx) const {
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
int Idx) const {
return 0;
}

39
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -1378,15 +1378,14 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MBB.erase(I);
}
int64_t ARMBaseRegisterInfo::
getFrameIndexInstrOffset(MachineInstr *MI, int Idx) const {
getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
const TargetInstrDesc &Desc = MI->getDesc();
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
int64_t InstrOffs = 0;;
int Scale = 1;
unsigned ImmIdx = 0;
switch(AddrMode) {
switch (AddrMode) {
case ARMII::AddrModeT2_i8:
case ARMII::AddrModeT2_i12:
// i8 supports only negative, and i12 supports only positive, so
@ -1573,15 +1572,12 @@ bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
unsigned NumBits = 0;
unsigned Scale = 1;
unsigned ImmIdx = 0;
int InstrOffs = 0;;
bool isSigned = true;
switch(AddrMode) {
switch (AddrMode) {
case ARMII::AddrModeT2_i8:
case ARMII::AddrModeT2_i12:
// i8 supports only negative, and i12 supports only positive, so
// based on Offset sign, consider the appropriate instruction
InstrOffs = MI->getOperand(i+1).getImm();
Scale = 1;
if (Offset < 0) {
NumBits = 8;
@ -1590,50 +1586,33 @@ bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
NumBits = 12;
}
break;
case ARMII::AddrMode5: {
case ARMII::AddrMode5:
// VFP address mode.
const MachineOperand &OffOp = MI->getOperand(i+1);
InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
InstrOffs = -InstrOffs;
NumBits = 8;
Scale = 4;
break;
}
case ARMII::AddrMode2: {
ImmIdx = i+2;
InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
InstrOffs = -InstrOffs;
case ARMII::AddrMode2:
NumBits = 12;
break;
}
case ARMII::AddrMode3: {
ImmIdx = i+2;
InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
InstrOffs = -InstrOffs;
case ARMII::AddrMode3:
NumBits = 8;
break;
}
case ARMII::AddrModeT1_s: {
ImmIdx = i+1;
InstrOffs = MI->getOperand(ImmIdx).getImm();
case ARMII::AddrModeT1_s:
NumBits = 5;
Scale = 4;
isSigned = false;
break;
}
default:
llvm_unreachable("Unsupported addressing mode!");
break;
}
Offset += InstrOffs * Scale;
Offset += getFrameIndexInstrOffset(MI, i);
assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
if (isSigned && Offset < 0)
Offset = -Offset;
unsigned Mask = (1 << NumBits) - 1;
if ((unsigned)Offset <= Mask * Scale)
return true;

2
llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
View File

@ -105,7 +105,7 @@ public:
bool canRealignStack(const MachineFunction &MF) const;
bool needsStackRealignment(const MachineFunction &MF) const;
int64_t getFrameIndexInstrOffset(MachineInstr *MI, int Idx) const;
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
void materializeFrameBaseRegister(MachineBasicBlock::iterator I,
unsigned BaseReg, int FrameIdx,