forked from OSchip/llvm-project
[XCore] Support functions returning more than 4 words.
Summary: If a function returns a large struct by value return the first 4 words in registers and the rest on the stack in a location reserved by the caller. This is needed to support the xC language which supports functions returning an arbitrary number of return values. Reviewers: robertlytton Reviewed By: robertlytton CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2889 llvm-svn: 202397
This commit is contained in:
Richard Osborne
parent
ed7e2ad090
commit
e82bf0988e
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@ -14,7 +14,11 @@
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//===----------------------------------------------------------------------===//
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def RetCC_XCore : CallingConv<[
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// i32 are returned in registers R0, R1, R2, R3
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CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>
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CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
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// Integer values get stored in stack slots that are 4 bytes in
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// size and 4-byte aligned.
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CCIfType<[i32], CCAssignToStack<4, 4>>
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]>;
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//===----------------------------------------------------------------------===//
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@ -50,6 +50,7 @@ getTargetNodeName(unsigned Opcode) const
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case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
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case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
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case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
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case XCoreISD::LDWSP : return "XCoreISD::LDWSP";
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case XCoreISD::STWSP : return "XCoreISD::STWSP";
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case XCoreISD::RETSP : return "XCoreISD::RETSP";
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case XCoreISD::LADD : return "XCoreISD::LADD";
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@ -1085,13 +1086,41 @@ LowerCallResult(SDValue Chain, SDValue InFlag,
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const SmallVectorImpl<CCValAssign> &RVLocs,
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SDLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) {
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// Copy all of the result registers out of their specified physreg.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
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RVLocs[i].getValVT(), InFlag).getValue(1);
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SmallVector<std::pair<int, unsigned>, 4> ResultMemLocs;
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// Copy results out of physical registers.
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for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
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const CCValAssign &VA = RVLocs[i];
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if (VA.isRegLoc()) {
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Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(),
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InFlag).getValue(1);
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InFlag = Chain.getValue(2);
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InVals.push_back(Chain.getValue(0));
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} else {
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assert(VA.isMemLoc());
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ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(),
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InVals.size()));
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// Reserve space for this result.
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InVals.push_back(SDValue());
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}
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}
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// Copy results out of memory.
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SmallVector<SDValue, 4> MemOpChains;
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for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) {
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int offset = ResultMemLocs[i].first;
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unsigned index = ResultMemLocs[i].second;
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SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
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SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, MVT::i32) };
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SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops, 2);
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InVals[index] = load;
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MemOpChains.push_back(load.getValue(1));
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}
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// Transform all loads nodes into one single node because
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// all load nodes are independent of each other.
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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return Chain;
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}
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@ -1121,8 +1150,15 @@ XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
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CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
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SmallVector<CCValAssign, 16> RVLocs;
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// Analyze return values to determine the number of bytes of stack required.
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CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
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getTargetMachine(), RVLocs, *DAG.getContext());
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RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), 4);
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RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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unsigned NumBytes = RetCCInfo.getNextStackOffset();
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Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
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getPointerTy(), true), dl);
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@ -1218,12 +1254,6 @@ XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
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InFlag, dl);
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InFlag = Chain.getValue(1);
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// Assign locations to each value returned by this call.
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SmallVector<CCValAssign, 16> RVLocs;
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CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
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getTargetMachine(), RVLocs, *DAG.getContext());
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RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
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// Handle result values, copying them out of physregs into vregs that we
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// return.
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return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals);
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@ -1274,6 +1304,7 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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@ -1286,6 +1317,9 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
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unsigned LRSaveSize = StackSlotSize;
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if (!isVarArg)
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XFI->setReturnStackOffset(CCInfo.getNextStackOffset() + LRSaveSize);
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// All getCopyFromReg ops must precede any getMemcpys to prevent the
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// scheduler clobbering a register before it has been copied.
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// The stages are:
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@ -1436,7 +1470,11 @@ CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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LLVMContext &Context) const {
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
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return CCInfo.CheckReturn(Outs, RetCC_XCore);
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if (!CCInfo.CheckReturn(Outs, RetCC_XCore))
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return false;
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if (CCInfo.getNextStackOffset() != 0 && isVarArg)
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return false;
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return true;
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}
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SDValue
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@ -1446,6 +1484,10 @@ XCoreTargetLowering::LowerReturn(SDValue Chain,
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc dl, SelectionDAG &DAG) const {
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XCoreFunctionInfo *XFI =
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DAG.getMachineFunction().getInfo<XCoreFunctionInfo>();
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MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
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// CCValAssign - represent the assignment of
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// the return value to a location
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SmallVector<CCValAssign, 16> RVLocs;
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@ -1455,6 +1497,9 @@ XCoreTargetLowering::LowerReturn(SDValue Chain,
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getTargetMachine(), RVLocs, *DAG.getContext());
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// Analyze return values.
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if (!isVarArg)
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CCInfo.AllocateStack(XFI->getReturnStackOffset(), 4);
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CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
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SDValue Flag;
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@ -1463,13 +1508,43 @@ XCoreTargetLowering::LowerReturn(SDValue Chain,
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// Return on XCore is always a "retsp 0"
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RetOps.push_back(DAG.getConstant(0, MVT::i32));
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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SmallVector<SDValue, 4> MemOpChains;
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// Handle return values that must be copied to memory.
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for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
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CCValAssign &VA = RVLocs[i];
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assert(VA.isRegLoc() && "Can only return in registers!");
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if (VA.isRegLoc())
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continue;
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assert(VA.isMemLoc());
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if (isVarArg) {
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report_fatal_error("Can't return value from vararg function in memory");
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}
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
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OutVals[i], Flag);
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int Offset = VA.getLocMemOffset();
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unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
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// Create the frame index object for the memory location.
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int FI = MFI->CreateFixedObject(ObjSize, Offset, false);
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// Create a SelectionDAG node corresponding to a store
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// to this memory location.
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SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
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MemOpChains.push_back(DAG.getStore(Chain, dl, OutVals[i], FIN,
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MachinePointerInfo::getFixedStack(FI), false, false,
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0));
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}
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// Transform all store nodes into one single node because
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// all stores are independent of each other.
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Now handle return values copied to registers.
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for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
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CCValAssign &VA = RVLocs[i];
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if (!VA.isRegLoc())
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continue;
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// Copy the result values into the output registers.
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
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// guarantee that all emitted copies are
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// stuck together, avoiding something bad
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@ -42,6 +42,9 @@ namespace llvm {
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// cp relative address
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CPRelativeWrapper,
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// Load word from stack
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LDWSP,
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// Store word to stack
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STWSP,
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@ -68,6 +68,10 @@ def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
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def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
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[SDNPHasChain, SDNPMayStore]>;
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def SDT_XCoreLdwsp : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
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def XCoreLdwsp : SDNode<"XCoreISD::LDWSP", SDT_XCoreLdwsp,
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[SDNPHasChain, SDNPMayLoad]>;
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// These are target-independent nodes, but have target-specific formats.
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def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
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def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
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@ -581,10 +585,12 @@ def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b),
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let mayLoad=1 in {
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def LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),
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"ldw $a, sp[$b]", []>;
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"ldw $a, sp[$b]",
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[(set RRegs:$a, (XCoreLdwsp immU6:$b))]>;
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def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),
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"ldw $a, sp[$b]", []>;
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"ldw $a, sp[$b]",
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[(set RRegs:$a, (XCoreLdwsp immU16:$b))]>;
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}
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let neverHasSideEffects = 1 in {
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@ -33,6 +33,8 @@ class XCoreFunctionInfo : public MachineFunctionInfo {
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int FPSpillSlot;
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bool EHSpillSlotSet;
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int EHSpillSlot[2];
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unsigned ReturnStackOffset;
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bool ReturnStackOffsetSet;
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int VarArgsFrameIndex;
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mutable int CachedEStackSize;
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std::vector<std::pair<MCSymbol*, CalleeSavedInfo> > SpillLabels;
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@ -42,6 +44,7 @@ public:
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LRSpillSlotSet(false),
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FPSpillSlotSet(false),
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EHSpillSlotSet(false),
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ReturnStackOffsetSet(false),
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VarArgsFrameIndex(0),
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CachedEStackSize(-1) {}
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@ -78,6 +81,17 @@ public:
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return EHSpillSlot;
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}
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void setReturnStackOffset(unsigned value) {
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assert(!ReturnStackOffsetSet && "Return stack offset set twice");
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ReturnStackOffset = value;
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ReturnStackOffsetSet = true;
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}
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unsigned getReturnStackOffset() const {
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assert(ReturnStackOffsetSet && "Return stack offset not set");
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return ReturnStackOffset;
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}
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bool isLargeFrame(const MachineFunction &MF) const;
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std::vector<std::pair<MCSymbol*, CalleeSavedInfo> > &getSpillLabels() {
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@ -3,8 +3,8 @@
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%0 = type { i32, i32, i32, i32 }
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%1 = type { i32, i32, i32, i32, i32 }
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; Structs of 4 words can be returned in registers
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define internal fastcc %0 @ReturnBigStruct() nounwind readnone {
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; Structs of 4 words are returned in registers
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define internal %0 @ReturnBigStruct() nounwind readnone {
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entry:
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%0 = insertvalue %0 zeroinitializer, i32 12, 0
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%1 = insertvalue %0 %0, i32 24, 1
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@ -19,8 +19,39 @@ entry:
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; CHECK: ldc r3, 24601
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; CHECK: retsp 0
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; Structs bigger than 4 words are returned via a hidden hidden sret-parameter
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define internal fastcc %1 @ReturnBigStruct2() nounwind readnone {
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; Structs of more than 4 words are partially returned in memory so long as the
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; function is not variadic.
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define { i32, i32, i32, i32, i32} @f(i32, i32, i32, i32, i32) nounwind readnone {
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; CHECK-LABEL: f:
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; CHECK: ldc [[REGISTER:r[0-9]+]], 5
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; CHECK-NEXT: stw [[REGISTER]], sp[2]
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; CHECK-NEXT: retsp 0
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body:
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ret { i32, i32, i32, i32, i32} { i32 undef, i32 undef, i32 undef, i32 undef, i32 5}
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}
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@x = external global i32
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@y = external global i32
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; Check we call a function returning more than 4 words correctly.
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define i32 @g() nounwind {
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; CHECK-LABEL: g:
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; CHECK: entsp 3
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; CHECK: ldc [[REGISTER:r[0-9]+]], 0
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; CHECK: stw [[REGISTER]], sp[1]
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; CHECK: bl f
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; CHECK-NEXT: ldw r0, sp[2]
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; CHECK-NEXT: retsp 3
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;
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body:
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%0 = call { i32, i32, i32, i32, i32 } @f(i32 0, i32 0, i32 0, i32 0, i32 0)
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%1 = extractvalue { i32, i32, i32, i32, i32 } %0, 4
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ret i32 %1
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}
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; Variadic functions return structs bigger than 4 words via a hidden
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; sret-parameter
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define internal %1 @ReturnBigStruct2(i32 %dummy, ...) nounwind readnone {
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entry:
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%0 = insertvalue %1 zeroinitializer, i32 12, 0
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%1 = insertvalue %1 %0, i32 24, 1
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