forked from OSchip/llvm-project
[X86] Add patterns to show more failures to use TBM instructions when we're trying to check flags.
We can probably add patterns to fix some of them. But the ones that use 'and' as their root node emit a X86ISD::CMP node in front of the 'and' and then pattern matching that to 'test' instruction. We can't use a tablegen pattern to fix that because we can't remap the cmp result to the flag output of a TBM instruction. llvm-svn: 311819
This commit is contained in:
parent
4b611a896d
commit
e81de105a5
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@ -37,6 +37,20 @@ define i32 @test_x86_tbm_bextri_u32_z(i32 %a, i32 %b) nounwind {
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ret i32 %t3
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}
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define i32 @test_x86_tbm_bextri_u32_z2(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_bextri_u32_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: bextr $3076, %edi, %eax # imm = 0xC04
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; CHECK-NEXT: cmovnel %edx, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%t0 = lshr i32 %a, 4
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%t1 = and i32 %t0, 4095
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%t2 = icmp eq i32 %t1, 0
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%t3 = select i1 %t2, i32 %b, i32 %c
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ret i32 %t3
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}
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define i64 @test_x86_tbm_bextri_u64(i64 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_bextri_u64:
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; CHECK: # BB#0:
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@ -71,6 +85,20 @@ define i64 @test_x86_tbm_bextri_u64_z(i64 %a, i64 %b) nounwind {
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ret i64 %t3
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}
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define i64 @test_x86_tbm_bextri_u64_z2(i64 %a, i64 %b, i64 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_bextri_u64_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: bextr $3076, %edi, %eax # imm = 0xC04
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; CHECK-NEXT: cmovneq %rdx, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: retq
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%t0 = lshr i64 %a, 4
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%t1 = and i64 %t0, 4095
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%t2 = icmp eq i64 %t1, 0
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%t3 = select i1 %t2, i64 %b, i64 %c
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ret i64 %t3
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}
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define i32 @test_x86_tbm_blcfill_u32(i32 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcfill_u32:
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; CHECK: # BB#0:
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@ -94,6 +122,22 @@ define i32 @test_x86_tbm_blcfill_u32_z(i32 %a, i32 %b) nounwind {
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ret i32 %t3
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}
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define i32 @test_x86_tbm_blcfill_u32_z2(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcfill_u32_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; CHECK-NEXT: leal 1(%rdi), %eax
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; CHECK-NEXT: testl %edi, %eax
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; CHECK-NEXT: cmovnel %edx, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%t0 = add i32 %a, 1
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%t1 = and i32 %t0, %a
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%t2 = icmp eq i32 %t1, 0
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%t3 = select i1 %t2, i32 %b, i32 %c
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ret i32 %t3
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}
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define i64 @test_x86_tbm_blcfill_u64(i64 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcfill_u64:
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; CHECK: # BB#0:
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@ -117,6 +161,21 @@ define i64 @test_x86_tbm_blcfill_u64_z(i64 %a, i64 %b) nounwind {
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ret i64 %t3
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}
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define i64 @test_x86_tbm_blcfill_u64_z2(i64 %a, i64 %b, i64 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcfill_u64_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: leaq 1(%rdi), %rax
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; CHECK-NEXT: testq %rdi, %rax
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; CHECK-NEXT: cmovneq %rdx, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: retq
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%t0 = add i64 %a, 1
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%t1 = and i64 %t0, %a
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%t2 = icmp eq i64 %t1, 0
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%t3 = select i1 %t2, i64 %b, i64 %c
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ret i64 %t3
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}
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define i32 @test_x86_tbm_blci_u32(i32 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blci_u32:
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; CHECK: # BB#0:
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@ -142,6 +201,24 @@ define i32 @test_x86_tbm_blci_u32_z(i32 %a, i32 %b) nounwind {
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ret i32 %t4
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}
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define i32 @test_x86_tbm_blci_u32_z2(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_blci_u32_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; CHECK-NEXT: leal 1(%rdi), %eax
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; CHECK-NEXT: notl %eax
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; CHECK-NEXT: orl %edi, %eax
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; CHECK-NEXT: cmovnel %edx, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%t0 = add i32 1, %a
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%t1 = xor i32 %t0, -1
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%t2 = or i32 %t1, %a
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%t3 = icmp eq i32 %t2, 0
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%t4 = select i1 %t3, i32 %b, i32 %c
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ret i32 %t4
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}
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define i64 @test_x86_tbm_blci_u64(i64 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blci_u64:
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; CHECK: # BB#0:
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@ -167,6 +244,23 @@ define i64 @test_x86_tbm_blci_u64_z(i64 %a, i64 %b) nounwind {
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ret i64 %t4
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}
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define i64 @test_x86_tbm_blci_u64_z2(i64 %a, i64 %b, i64 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_blci_u64_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: leaq 1(%rdi), %rax
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; CHECK-NEXT: notq %rax
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; CHECK-NEXT: orq %rdi, %rax
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; CHECK-NEXT: cmovneq %rdx, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: retq
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%t0 = add i64 1, %a
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%t1 = xor i64 %t0, -1
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%t2 = or i64 %t1, %a
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%t3 = icmp eq i64 %t2, 0
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%t4 = select i1 %t3, i64 %b, i64 %c
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ret i64 %t4
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}
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define i32 @test_x86_tbm_blci_u32_b(i32 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blci_u32_b:
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; CHECK: # BB#0:
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@ -212,6 +306,24 @@ define i32 @test_x86_tbm_blcic_u32_z(i32 %a, i32 %b) nounwind {
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ret i32 %t4
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}
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define i32 @test_x86_tbm_blcic_u32_z2(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcic_u32_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: notl %eax
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; CHECK-NEXT: incl %edi
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; CHECK-NEXT: testl %eax, %edi
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; CHECK-NEXT: cmovnel %edx, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%t0 = xor i32 %a, -1
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%t1 = add i32 %a, 1
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%t2 = and i32 %t1, %t0
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%t3 = icmp eq i32 %t2, 0
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%t4 = select i1 %t3, i32 %b, i32 %c
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ret i32 %t4
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}
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define i64 @test_x86_tbm_blcic_u64(i64 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcic_u64:
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; CHECK: # BB#0:
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ret i64 %t4
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}
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define i64 @test_x86_tbm_blcic_u64_z2(i64 %a, i64 %b, i64 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcic_u64_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: notq %rax
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; CHECK-NEXT: incq %rdi
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; CHECK-NEXT: testq %rax, %rdi
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; CHECK-NEXT: cmovneq %rdx, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: retq
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%t0 = xor i64 %a, -1
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%t1 = add i64 %a, 1
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%t2 = and i64 %t1, %t0
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%t3 = icmp eq i64 %t2, 0
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%t4 = select i1 %t3, i64 %b, i64 %c
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ret i64 %t4
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}
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define i32 @test_x86_tbm_blcmsk_u32(i32 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcmsk_u32:
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; CHECK: # BB#0:
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ret i32 %t3
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}
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define i32 @test_x86_tbm_blcmsk_u32_z2(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcmsk_u32_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; CHECK-NEXT: leal 1(%rdi), %eax
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; CHECK-NEXT: xorl %edi, %eax
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; CHECK-NEXT: cmovnel %edx, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%t0 = add i32 %a, 1
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%t1 = xor i32 %t0, %a
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%t2 = icmp eq i32 %t1, 0
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%t3 = select i1 %t2, i32 %b, i32 %c
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ret i32 %t3
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}
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define i64 @test_x86_tbm_blcmsk_u64(i64 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcmsk_u64:
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; CHECK: # BB#0:
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ret i64 %t3
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}
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define i64 @test_x86_tbm_blcmsk_u64_z2(i64 %a, i64 %b, i64 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcmsk_u64_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: leaq 1(%rdi), %rax
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; CHECK-NEXT: xorq %rdi, %rax
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; CHECK-NEXT: cmovneq %rdx, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: retq
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%t0 = add i64 %a, 1
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%t1 = xor i64 %t0, %a
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%t2 = icmp eq i64 %t1, 0
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%t3 = select i1 %t2, i64 %b, i64 %c
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ret i64 %t3
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}
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define i32 @test_x86_tbm_blcs_u32(i32 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcs_u32:
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; CHECK: # BB#0:
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ret i32 %t3
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}
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define i32 @test_x86_tbm_blcs_u32_z2(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcs_u32_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; CHECK-NEXT: leal 1(%rdi), %eax
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; CHECK-NEXT: orl %edi, %eax
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; CHECK-NEXT: cmovnel %edx, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%t0 = add i32 %a, 1
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%t1 = or i32 %t0, %a
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%t2 = icmp eq i32 %t1, 0
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%t3 = select i1 %t2, i32 %b, i32 %c
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ret i32 %t3
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}
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define i64 @test_x86_tbm_blcs_u64(i64 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcs_u64:
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; CHECK: # BB#0:
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ret i64 %t3
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}
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define i64 @test_x86_tbm_blcs_u64_z2(i64 %a, i64 %b, i64 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcs_u64_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: leaq 1(%rdi), %rax
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; CHECK-NEXT: orq %rdi, %rax
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; CHECK-NEXT: cmovneq %rdx, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: retq
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%t0 = add i64 %a, 1
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%t1 = or i64 %t0, %a
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%t2 = icmp eq i64 %t1, 0
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%t3 = select i1 %t2, i64 %b, i64 %c
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ret i64 %t3
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}
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define i32 @test_x86_tbm_blsfill_u32(i32 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blsfill_u32:
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; CHECK: # BB#0:
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ret i32 %t3
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}
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define i32 @test_x86_tbm_blsfill_u32_z2(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_blsfill_u32_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; CHECK-NEXT: leal -1(%rdi), %eax
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; CHECK-NEXT: orl %edi, %eax
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; CHECK-NEXT: cmovnel %edx, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%t0 = add i32 %a, -1
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%t1 = or i32 %t0, %a
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%t2 = icmp eq i32 %t1, 0
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%t3 = select i1 %t2, i32 %b, i32 %c
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ret i32 %t3
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}
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define i64 @test_x86_tbm_blsfill_u64(i64 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blsfill_u64:
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; CHECK: # BB#0:
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ret i64 %t3
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}
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define i64 @test_x86_tbm_blsfill_u64_z2(i64 %a, i64 %b, i64 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_blsfill_u64_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: leaq -1(%rdi), %rax
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; CHECK-NEXT: orq %rdi, %rax
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; CHECK-NEXT: cmovneq %rdx, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: retq
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%t0 = add i64 %a, -1
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%t1 = or i64 %t0, %a
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%t2 = icmp eq i64 %t1, 0
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%t3 = select i1 %t2, i64 %b, i64 %c
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ret i64 %t3
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}
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define i32 @test_x86_tbm_blsic_u32(i32 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blsic_u32:
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; CHECK: # BB#0:
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@ -400,6 +623,24 @@ define i32 @test_x86_tbm_blsic_u32_z(i32 %a, i32 %b) nounwind {
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ret i32 %t4
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}
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define i32 @test_x86_tbm_blsic_u32_z2(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_blsic_u32_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: notl %eax
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; CHECK-NEXT: decl %edi
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; CHECK-NEXT: orl %eax, %edi
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; CHECK-NEXT: cmovnel %edx, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%t0 = xor i32 %a, -1
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%t1 = add i32 %a, -1
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%t2 = or i32 %t0, %t1
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%t3 = icmp eq i32 %t2, 0
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%t4 = select i1 %t3, i32 %b, i32 %c
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ret i32 %t4
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}
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define i64 @test_x86_tbm_blsic_u64(i64 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blsic_u64:
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; CHECK: # BB#0:
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@ -425,6 +666,24 @@ define i64 @test_x86_tbm_blsic_u64_z(i64 %a, i64 %b) nounwind {
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ret i64 %t4
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}
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define i64 @test_x86_tbm_blsic_u64_z2(i64 %a, i64 %b, i64 %c) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blsic_u64_z2:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movq %rdi, %rax
|
||||
; CHECK-NEXT: notq %rax
|
||||
; CHECK-NEXT: decq %rdi
|
||||
; CHECK-NEXT: orq %rax, %rdi
|
||||
; CHECK-NEXT: cmovneq %rdx, %rsi
|
||||
; CHECK-NEXT: movq %rsi, %rax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = xor i64 %a, -1
|
||||
%t1 = add i64 %a, -1
|
||||
%t2 = or i64 %t0, %t1
|
||||
%t3 = icmp eq i64 %t2, 0
|
||||
%t4 = select i1 %t3, i64 %b, i64 %c
|
||||
ret i64 %t4
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_t1mskc_u32(i32 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_t1mskc_u32:
|
||||
; CHECK: # BB#0:
|
||||
|
@ -451,6 +710,24 @@ define i32 @test_x86_tbm_t1mskc_u32_z(i32 %a, i32 %b) nounwind {
|
|||
ret i32 %t4
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_t1mskc_u32_z2(i32 %a, i32 %b, i32 %c) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_t1mskc_u32_z2:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movl %edi, %eax
|
||||
; CHECK-NEXT: notl %eax
|
||||
; CHECK-NEXT: incl %edi
|
||||
; CHECK-NEXT: orl %eax, %edi
|
||||
; CHECK-NEXT: cmovnel %edx, %esi
|
||||
; CHECK-NEXT: movl %esi, %eax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = xor i32 %a, -1
|
||||
%t1 = add i32 %a, 1
|
||||
%t2 = or i32 %t0, %t1
|
||||
%t3 = icmp eq i32 %t2, 0
|
||||
%t4 = select i1 %t3, i32 %b, i32 %c
|
||||
ret i32 %t4
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_t1mskc_u64(i64 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_t1mskc_u64:
|
||||
; CHECK: # BB#0:
|
||||
|
@ -477,6 +754,24 @@ define i64 @test_x86_tbm_t1mskc_u64_z(i64 %a, i64 %b) nounwind {
|
|||
ret i64 %t4
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_t1mskc_u64_z2(i64 %a, i64 %b, i64 %c) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_t1mskc_u64_z2:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movq %rdi, %rax
|
||||
; CHECK-NEXT: notq %rax
|
||||
; CHECK-NEXT: incq %rdi
|
||||
; CHECK-NEXT: orq %rax, %rdi
|
||||
; CHECK-NEXT: cmovneq %rdx, %rsi
|
||||
; CHECK-NEXT: movq %rsi, %rax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = xor i64 %a, -1
|
||||
%t1 = add i64 %a, 1
|
||||
%t2 = or i64 %t0, %t1
|
||||
%t3 = icmp eq i64 %t2, 0
|
||||
%t4 = select i1 %t3, i64 %b, i64 %c
|
||||
ret i64 %t4
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_tzmsk_u32(i32 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_tzmsk_u32:
|
||||
; CHECK: # BB#0:
|
||||
|
@ -503,6 +798,24 @@ define i32 @test_x86_tbm_tzmsk_u32_z(i32 %a, i32 %b) nounwind {
|
|||
ret i32 %t4
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_tzmsk_u32_z2(i32 %a, i32 %b, i32 %c) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_tzmsk_u32_z2:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movl %edi, %eax
|
||||
; CHECK-NEXT: notl %eax
|
||||
; CHECK-NEXT: decl %edi
|
||||
; CHECK-NEXT: testl %edi, %eax
|
||||
; CHECK-NEXT: cmovnel %edx, %esi
|
||||
; CHECK-NEXT: movl %esi, %eax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = xor i32 %a, -1
|
||||
%t1 = add i32 %a, -1
|
||||
%t2 = and i32 %t0, %t1
|
||||
%t3 = icmp eq i32 %t2, 0
|
||||
%t4 = select i1 %t3, i32 %b, i32 %c
|
||||
ret i32 %t4
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_tzmsk_u64(i64 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_tzmsk_u64:
|
||||
; CHECK: # BB#0:
|
||||
|
@ -529,6 +842,24 @@ define i64 @test_x86_tbm_tzmsk_u64_z(i64 %a, i64 %b) nounwind {
|
|||
ret i64 %t4
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_tzmsk_u64_z2(i64 %a, i64 %b, i64 %c) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_tzmsk_u64_z2:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movq %rdi, %rax
|
||||
; CHECK-NEXT: notq %rax
|
||||
; CHECK-NEXT: decq %rdi
|
||||
; CHECK-NEXT: testq %rdi, %rax
|
||||
; CHECK-NEXT: cmovneq %rdx, %rsi
|
||||
; CHECK-NEXT: movq %rsi, %rax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = xor i64 %a, -1
|
||||
%t1 = add i64 %a, -1
|
||||
%t2 = and i64 %t0, %t1
|
||||
%t3 = icmp eq i64 %t2, 0
|
||||
%t4 = select i1 %t3, i64 %b, i64 %c
|
||||
ret i64 %t4
|
||||
}
|
||||
|
||||
define i64 @test_and_large_constant_mask(i64 %x) {
|
||||
; CHECK-LABEL: test_and_large_constant_mask:
|
||||
; CHECK: # BB#0: # %entry
|
||||
|
|
Loading…
Reference in New Issue