forked from OSchip/llvm-project
Revert r268810 becase it brakes msan bot.
16802==WARNING: MemorySanitizer: use-of-uninitialized-value
lib/Target/ARM/ARMFrameLowering.cpp:1632
llvm-svn: 268833
This commit is contained in:
Vitaly Buka
parent
6eef08138e
commit
e81d96be6f
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@ -1479,7 +1479,6 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
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bool CS1Spilled = false;
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bool LRSpilled = false;
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unsigned NumGPRSpills = 0;
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unsigned NumFPRSpills = 0;
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SmallVector<unsigned, 4> UnspilledCS1GPRs;
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SmallVector<unsigned, 4> UnspilledCS2GPRs;
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const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
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@ -1534,17 +1533,8 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
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CanEliminateFrame = false;
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}
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if (!ARM::GPRRegClass.contains(Reg)) {
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if (Spilled) {
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if (ARM::SPRRegClass.contains(Reg))
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NumFPRSpills++;
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else if (ARM::DPRRegClass.contains(Reg))
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NumFPRSpills += 2;
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else if (ARM::QPRRegClass.contains(Reg))
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NumFPRSpills += 4;
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}
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if (!ARM::GPRRegClass.contains(Reg))
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continue;
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}
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if (Spilled) {
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NumGPRSpills++;
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@ -1617,21 +1607,12 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
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// FIXME: We could add logic to be more precise about negative offsets
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// and which instructions will need a scratch register for them. Is it
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// worth the effort and added fragility?
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unsigned EstimatedStackSize =
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MFI->estimateStackSize(MF) + 4 * (NumGPRSpills + NumFPRSpills);
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if (hasFP(MF)) {
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if (AFI->hasStackFrame())
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EstimatedStackSize += 4;
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} else {
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// If FP is not used, SP will be used to access arguments, so count the
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// size of arguments into the estimation.
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EstimatedStackSize += MF.getInfo<ARMFunctionInfo>()->getArgumentStackSize();
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}
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EstimatedStackSize += 16; // For possible paddings.
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bool BigStack = EstimatedStackSize >= estimateRSStackSizeLimit(MF, this) ||
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bool BigStack = (RS && (MFI->estimateStackSize(MF) +
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((hasFP(MF) && AFI->hasStackFrame()) ? 4 : 0) >=
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estimateRSStackSizeLimit(MF, this))) ||
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MFI->hasVarSizedObjects() ||
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(MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
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bool ExtraCSSpill = false;
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if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
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AFI->setHasStackFrame(true);
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@ -1725,7 +1706,6 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
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} else if (!AFI->isThumb1OnlyFunction()) {
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// note: Thumb1 functions spill to R12, not the stack. Reserve a slot
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// closest to SP or frame pointer.
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assert(RS && "Register scavenging not provided");
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const TargetRegisterClass *RC = &ARM::GPRRegClass;
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RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
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RC->getAlignment(),
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@ -1,192 +0,0 @@
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; RUN: llc < %s
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; This test has around 4000 bytes of local variables and it also stresses register allocation
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; to force a register scavenging. It tests if the stack is treated as "BigStack" and thus
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; spill slots are reserved. If not, reg scavenger will assert.
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n8:16:32-S64"
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target triple = "thumbv7--linux-android"
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%struct.r = type { i32 (...)**, [10 x [9 x float]], [10 x [9 x float]], [101 x [9 x float]], [101 x [9 x float]], i32, i32, i32, i32, i32, [8 x [2 x i32]], [432 x float], [432 x i32], [10 x i8*], [10 x i8*], [10 x i32], [10 x i32], [10 x i32], [10 x i32], [10 x i32], [10 x i32], i32, i32, i32, i32, float, float, i32, i32, [9 x float], float*, float }
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define void @foo(%struct.r* %this, float* %srcR, float* %srcC, float* %tempPntsX, float* %tY, float* %ms, float* %sX, float* %sY, i32* dereferenceable(4) %num, float* %tm, i32 %SR, i32 %lev, i8* %tdata, i32 %siW, i32 %pyw, i32 %pyh, i8* %sdata) #0 align 2 {
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entry:
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%sFV = alloca [49 x float], align 4
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%tFV = alloca [49 x float], align 4
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%TIM = alloca [9 x float], align 4
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%sort_tmp = alloca [432 x float], align 4
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%msDiffs = alloca [432 x float], align 4
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%TM.sroa.0.0.copyload = load float, float* %tm, align 4
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%TM.sroa.8.0.copyload = load float, float* null, align 4
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%TM.sroa.9.0..sroa_idx813 = getelementptr inbounds float, float* %tm, i32 6
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%TM.sroa.9.0.copyload = load float, float* %TM.sroa.9.0..sroa_idx813, align 4
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%TM.sroa.11.0.copyload = load float, float* undef, align 4
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br i1 undef, label %for.body.lr.ph, label %if.then343
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for.body.lr.ph: ; preds = %entry
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%arrayidx8 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 0
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%arrayidx12 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 6
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%arrayidx15 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 4
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%arrayidx20 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 7
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%arrayidx24 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 0
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%arrayidx28 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 6
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%arrayidx32 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 4
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%arrayidx36 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 7
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%arrayidx84 = getelementptr inbounds [9 x float], [9 x float]* %TIM, i32 0, i32 6
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%arrayidx92 = getelementptr inbounds [9 x float], [9 x float]* %TIM, i32 0, i32 7
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%add116 = add nsw i32 %pyh, 15
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br label %for.body
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for.body: ; preds = %for.cond.cleanup40, %for.body.lr.ph
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%arrayidx.phi = phi float* [ %sX, %for.body.lr.ph ], [ %arrayidx.inc, %for.cond.cleanup40 ]
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%arrayidx4.phi = phi float* [ %sY, %for.body.lr.ph ], [ %arrayidx4.inc, %for.cond.cleanup40 ]
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%0 = load float, float* %arrayidx.phi, align 4
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%1 = load float, float* %arrayidx4.phi, align 4
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%2 = load float, float* %arrayidx12, align 4
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%add = fadd fast float 0.000000e+00, %2
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%3 = load float, float* %arrayidx20, align 4
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%add21 = fadd fast float 0.000000e+00, %3
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%mul3.i = fmul fast float %add21, %TM.sroa.8.0.copyload
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%add.i = fadd fast float 0.000000e+00, %TM.sroa.11.0.copyload
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%add5.i = fadd fast float %add.i, %mul3.i
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%conv6.i = fdiv fast float 1.000000e+00, %add5.i
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%mul8.i = fmul fast float %add, %TM.sroa.0.0.copyload
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%add11.i = fadd fast float %mul8.i, %TM.sroa.9.0.copyload
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%add13.i = fadd fast float %add11.i, 0.000000e+00
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%4 = load float, float* %arrayidx24, align 4
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%mul14.i = fmul fast float %add13.i, %4
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%mul25 = fmul fast float %mul14.i, %conv6.i
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%add29 = fadd fast float %mul25, 0.000000e+00
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%arrayidx.inc = getelementptr float, float* %arrayidx.phi, i32 1
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%arrayidx4.inc = getelementptr float, float* %arrayidx4.phi, i32 1
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%conv64.1 = sitofp i32 undef to float
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%conv64.6 = sitofp i32 undef to float
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br label %for.body41
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for.cond.cleanup40: ; preds = %for.body41
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%call = call fast float undef(%struct.r* nonnull %this, float* undef, i32 49)
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br label %for.body
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for.body41: ; preds = %for.cond.cleanup56.for.body41_crit_edge, %for.body
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%5 = phi float [ 0.000000e+00, %for.body ], [ %.pre, %for.cond.cleanup56.for.body41_crit_edge ]
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%sFVData.0840 = phi float* [ undef, %for.body ], [ undef, %for.cond.cleanup56.for.body41_crit_edge ]
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%dx.0838 = phi i32 [ -3, %for.body ], [ undef, %for.cond.cleanup56.for.body41_crit_edge ]
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%conv42 = sitofp i32 %dx.0838 to float
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%add43 = fadd fast float %conv42, %add29
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%conv44 = fptosi float %add43 to i32
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%conv48 = sitofp i32 %conv44 to float
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%mul49 = fmul fast float %5, %conv48
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%add53 = fadd fast float %mul49, 0.000000e+00
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%conv111 = fptosi float undef to i32
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%cond = select i1 undef, i32 %conv111, i32 -16
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%cond.add116 = select i1 undef, i32 %cond, i32 %add116
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%cmp132 = icmp sgt i32 undef, -16
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%cond137 = select i1 %cmp132, i32 undef, i32 -16
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%cond153 = select i1 undef, i32 %cond137, i32 undef
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%add.ptr = getelementptr inbounds i8, i8* %sdata, i32 %cond153
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%mul154 = mul nsw i32 %cond.add116, %siW
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%add.ptr155 = getelementptr inbounds i8, i8* %add.ptr, i32 %mul154
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%6 = load i8, i8* %add.ptr155, align 1
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%conv157 = uitofp i8 %6 to float
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%incdec.ptr = getelementptr inbounds float, float* %sFVData.0840, i32 1
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store float %conv157, float* %sFVData.0840, align 4
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%7 = load float, float* %arrayidx15, align 4
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%mul65.1 = fmul fast float %7, %conv64.1
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%8 = load float, float* %arrayidx20, align 4
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%add69.1 = fadd fast float %mul65.1, %8
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%conv78.1 = fdiv fast float 1.000000e+00, 0.000000e+00
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%9 = load float, float* undef, align 4
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%mul80.1 = fmul fast float %9, %add53
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%10 = load float, float* undef, align 4
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%mul82.1 = fmul fast float %10, %add69.1
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%add83.1 = fadd fast float %mul82.1, %mul80.1
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%11 = load float, float* %arrayidx84, align 4
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%add85.1 = fadd fast float %add83.1, %11
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%mul86.1 = fmul fast float %add85.1, %conv78.1
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%12 = load float, float* %arrayidx92, align 4
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%add93.1 = fadd fast float 0.000000e+00, %12
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%mul94.1 = fmul fast float %add93.1, %conv78.1
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%13 = load float, float* %arrayidx24, align 4
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%mul98.1 = fmul fast float %mul86.1, %13
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%14 = load float, float* %arrayidx28, align 4
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%add102.1 = fadd fast float %mul98.1, %14
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%15 = load float, float* %arrayidx32, align 4
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%mul106.1 = fmul fast float %mul94.1, %15
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%16 = load float, float* %arrayidx36, align 4
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%add110.1 = fadd fast float %mul106.1, %16
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%conv111.1 = fptosi float %add102.1 to i32
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%conv112.1 = fptosi float %add110.1 to i32
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%cond.1 = select i1 undef, i32 %conv111.1, i32 -16
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%cond.add116.1 = select i1 undef, i32 %cond.1, i32 %add116
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%cond137.1 = select i1 undef, i32 %conv112.1, i32 -16
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%cond153.1 = select i1 undef, i32 %cond137.1, i32 undef
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%add.ptr.1 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.1
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%mul154.1 = mul nsw i32 %cond.add116.1, %siW
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%add.ptr155.1 = getelementptr inbounds i8, i8* %add.ptr.1, i32 %mul154.1
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%17 = load i8, i8* %add.ptr155.1, align 1
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%conv157.1 = uitofp i8 %17 to float
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%incdec.ptr.1 = getelementptr inbounds float, float* %sFVData.0840, i32 2
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store float %conv157.1, float* %incdec.ptr, align 4
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%conv112.2 = fptosi float undef to i32
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%cond137.2 = select i1 undef, i32 %conv112.2, i32 -16
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%cond153.2 = select i1 undef, i32 %cond137.2, i32 undef
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%add.ptr.2 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.2
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%add.ptr155.2 = getelementptr inbounds i8, i8* %add.ptr.2, i32 0
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%18 = load i8, i8* %add.ptr155.2, align 1
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%conv157.2 = uitofp i8 %18 to float
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%incdec.ptr.2 = getelementptr inbounds float, float* %sFVData.0840, i32 3
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store float %conv157.2, float* %incdec.ptr.1, align 4
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%cmp132.3 = icmp sgt i32 undef, -16
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%cond137.3 = select i1 %cmp132.3, i32 undef, i32 -16
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%cond153.3 = select i1 undef, i32 %cond137.3, i32 undef
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%add.ptr.3 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.3
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%add.ptr155.3 = getelementptr inbounds i8, i8* %add.ptr.3, i32 0
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%19 = load i8, i8* %add.ptr155.3, align 1
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%conv157.3 = uitofp i8 %19 to float
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store float %conv157.3, float* %incdec.ptr.2, align 4
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%incdec.ptr.5 = getelementptr inbounds float, float* %sFVData.0840, i32 6
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%20 = load float, float* %arrayidx15, align 4
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%mul65.6 = fmul fast float %20, %conv64.6
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%21 = load float, float* %arrayidx20, align 4
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%add69.6 = fadd fast float %mul65.6, %21
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%conv78.6 = fdiv fast float 1.000000e+00, 0.000000e+00
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%22 = load float, float* undef, align 4
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%mul82.6 = fmul fast float %22, %add69.6
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%add83.6 = fadd fast float %mul82.6, 0.000000e+00
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%23 = load float, float* %arrayidx84, align 4
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%add85.6 = fadd fast float %add83.6, %23
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%mul86.6 = fmul fast float %add85.6, %conv78.6
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%24 = load float, float* %arrayidx24, align 4
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%mul98.6 = fmul fast float %mul86.6, %24
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%25 = load float, float* %arrayidx28, align 4
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%add102.6 = fadd fast float %mul98.6, %25
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%conv111.6 = fptosi float %add102.6 to i32
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%conv112.6 = fptosi float undef to i32
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%cond.6 = select i1 undef, i32 %conv111.6, i32 -16
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%cond.add116.6 = select i1 undef, i32 %cond.6, i32 %add116
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%cmp132.6 = icmp sgt i32 %conv112.6, -16
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%cond137.6 = select i1 %cmp132.6, i32 %conv112.6, i32 -16
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%cond153.6 = select i1 undef, i32 %cond137.6, i32 undef
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%add.ptr.6 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.6
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%mul154.6 = mul nsw i32 %cond.add116.6, %siW
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%add.ptr155.6 = getelementptr inbounds i8, i8* %add.ptr.6, i32 %mul154.6
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%26 = load i8, i8* %add.ptr155.6, align 1
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%conv157.6 = uitofp i8 %26 to float
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store float %conv157.6, float* %incdec.ptr.5, align 4
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%exitcond874 = icmp eq i32 %dx.0838, 3
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br i1 %exitcond874, label %for.cond.cleanup40, label %for.cond.cleanup56.for.body41_crit_edge
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for.cond.cleanup56.for.body41_crit_edge: ; preds = %for.body41
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%.pre = load float, float* %arrayidx8, align 4
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br label %for.body41
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if.then343: ; preds = %entry
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ret void
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}
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attributes #0 = { sspstrong uwtable "no-frame-pointer-elim"="false" "target-cpu"="cortex-a7" }
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!1 = !{!2, !2, i64 0}
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!2 = !{!"float", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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!5 = !{!3, !3, i64 0}
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