forked from OSchip/llvm-project
[AMDGPU] Added MsgPack format PAL metadata
Summary: PAL metadata now supports both the old linear reg=val pairs format and the new MsgPack format. The MsgPack format uses YAML as its textual representation. On output to YAML, a mnemonic name is provided for some hardware registers. Differential Revision: https://reviews.llvm.org/D57028 Change-Id: I2bbaabaaca4b3574f7e03b80fbef7c7a69d06a94 llvm-svn: 356591
This commit is contained in:
Tim Renouf
parent
e4588bbf80
commit
e7bd52f86e
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@ -452,9 +452,15 @@ constexpr char AssemblerDirectiveEnd[] = ".end_amdgpu_metadata";
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//===----------------------------------------------------------------------===//
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namespace PALMD {
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/// PAL metadata assembler directive.
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/// PAL metadata (old linear format) assembler directive.
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constexpr char AssemblerDirective[] = ".amd_amdgpu_pal_metadata";
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/// PAL metadata (new MsgPack format) beginning assembler directive.
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constexpr char AssemblerDirectiveBegin[] = ".amdgpu_pal_metadata";
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/// PAL metadata (new MsgPack format) ending assembler directive.
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constexpr char AssemblerDirectiveEnd[] = ".end_amdgpu_pal_metadata";
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/// PAL metadata keys.
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enum Key : uint32_t {
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R_2E12_COMPUTE_PGM_RSRC1 = 0x2e12,
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@ -1022,6 +1022,7 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
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auto CC = MF.getFunction().getCallingConv();
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auto MD = getTargetStreamer()->getPALMetadata();
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MD->setEntryPoint(CC, MF.getFunction().getName());
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MD->setNumUsedVgprs(CC, CurrentProgramInfo.NumVGPRsForWavesPerEU);
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MD->setNumUsedSgprs(CC, CurrentProgramInfo.NumSGPRsForWavesPerEU);
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if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
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@ -893,8 +893,15 @@ private:
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bool ParseDirectiveISAVersion();
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bool ParseDirectiveHSAMetadata();
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bool ParseDirectivePALMetadataBegin();
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bool ParseDirectivePALMetadata();
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/// Common code to parse out a block of text (typically YAML) between start and
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/// end directives.
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bool ParseToEndDirective(const char *AssemblerDirectiveBegin,
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const char *AssemblerDirectiveEnd,
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std::string &CollectString);
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bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
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RegisterKind RegKind, unsigned Reg1,
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unsigned RegNum);
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@ -3296,40 +3303,9 @@ bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() {
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}
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std::string HSAMetadataString;
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raw_string_ostream YamlStream(HSAMetadataString);
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getLexer().setSkipSpace(false);
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bool FoundEnd = false;
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while (!getLexer().is(AsmToken::Eof)) {
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while (getLexer().is(AsmToken::Space)) {
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YamlStream << getLexer().getTok().getString();
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Lex();
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}
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if (getLexer().is(AsmToken::Identifier)) {
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StringRef ID = getLexer().getTok().getIdentifier();
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if (ID == AssemblerDirectiveEnd) {
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Lex();
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FoundEnd = true;
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break;
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}
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}
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YamlStream << Parser.parseStringToEndOfStatement()
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<< getContext().getAsmInfo()->getSeparatorString();
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Parser.eatToEndOfStatement();
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}
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getLexer().setSkipSpace(true);
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if (getLexer().is(AsmToken::Eof) && !FoundEnd) {
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return TokError(Twine("expected directive ") +
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Twine(HSAMD::AssemblerDirectiveEnd) + Twine(" not found"));
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}
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YamlStream.flush();
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if (ParseToEndDirective(AssemblerDirectiveBegin, AssemblerDirectiveEnd,
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HSAMetadataString))
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return true;
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if (IsaInfo::hasCodeObjectV3(&getSTI())) {
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if (!getTargetStreamer().EmitHSAMetadataV3(HSAMetadataString))
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@ -3342,6 +3318,63 @@ bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() {
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return false;
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}
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/// Common code to parse out a block of text (typically YAML) between start and
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/// end directives.
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bool AMDGPUAsmParser::ParseToEndDirective(const char *AssemblerDirectiveBegin,
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const char *AssemblerDirectiveEnd,
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std::string &CollectString) {
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raw_string_ostream CollectStream(CollectString);
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getLexer().setSkipSpace(false);
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bool FoundEnd = false;
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while (!getLexer().is(AsmToken::Eof)) {
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while (getLexer().is(AsmToken::Space)) {
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CollectStream << getLexer().getTok().getString();
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Lex();
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}
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if (getLexer().is(AsmToken::Identifier)) {
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StringRef ID = getLexer().getTok().getIdentifier();
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if (ID == AssemblerDirectiveEnd) {
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Lex();
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FoundEnd = true;
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break;
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}
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}
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CollectStream << Parser.parseStringToEndOfStatement()
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<< getContext().getAsmInfo()->getSeparatorString();
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Parser.eatToEndOfStatement();
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}
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getLexer().setSkipSpace(true);
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if (getLexer().is(AsmToken::Eof) && !FoundEnd) {
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return TokError(Twine("expected directive ") +
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Twine(AssemblerDirectiveEnd) + Twine(" not found"));
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}
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CollectStream.flush();
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return false;
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}
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/// Parse the assembler directive for new MsgPack-format PAL metadata.
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bool AMDGPUAsmParser::ParseDirectivePALMetadataBegin() {
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std::string String;
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if (ParseToEndDirective(AMDGPU::PALMD::AssemblerDirectiveBegin,
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AMDGPU::PALMD::AssemblerDirectiveEnd, String))
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return true;
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auto PALMetadata = getTargetStreamer().getPALMetadata();
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if (!PALMetadata->setFromString(String))
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return Error(getParser().getTok().getLoc(), "invalid PAL metadata");
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return false;
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}
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/// Parse the assembler directive for old linear-format PAL metadata.
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bool AMDGPUAsmParser::ParseDirectivePALMetadata() {
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if (getSTI().getTargetTriple().getOS() != Triple::AMDPAL) {
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return Error(getParser().getTok().getLoc(),
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@ -3350,6 +3383,7 @@ bool AMDGPUAsmParser::ParseDirectivePALMetadata() {
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}
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auto PALMetadata = getTargetStreamer().getPALMetadata();
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PALMetadata->setLegacy();
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for (;;) {
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uint32_t Key, Value;
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if (ParseAsAbsoluteExpression(Key)) {
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@ -3406,6 +3440,9 @@ bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
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return ParseDirectiveHSAMetadata();
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}
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if (IDVal == PALMD::AssemblerDirectiveBegin)
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return ParseDirectivePALMetadataBegin();
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if (IDVal == PALMD::AssemblerDirective)
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return ParseDirectivePALMetadata();
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@ -384,12 +384,12 @@ MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() {
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// We use it for emitting the accumulated PAL metadata as a .note record.
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void AMDGPUTargetELFStreamer::finish() {
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std::string Blob;
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unsigned Type = ELF::NT_AMD_AMDGPU_PAL_METADATA;
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const char *Vendor = getPALMetadata()->getVendor();
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unsigned Type = getPALMetadata()->getType();
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getPALMetadata()->toBlob(Type, Blob);
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if (Blob.empty())
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return;
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EmitNote(ElfNote::NoteNameV2,
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MCConstantExpr::create(Blob.size(), getContext()), Type,
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EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type,
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[&](MCELFStreamer &OS) { OS.EmitBytes(Blob); });
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}
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@ -27,15 +27,28 @@
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using namespace llvm;
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using namespace llvm::AMDGPU;
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// Read the amdgpu.pal.metadata supplied by the
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// frontend into our Registers, ready for per-function modification. It
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// is a NamedMD containing an MDTuple containing a number of MDNodes each of
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// which is an integer value, and each two integer values forms a key=value
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// pair that we store as Registers[key]=value in the map.
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// Read the PAL metadata from IR metadata, where it was put by the frontend.
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void AMDGPUPALMetadata::readFromIR(Module &M) {
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auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
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auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata.msgpack");
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if (NamedMD && NamedMD->getNumOperands()) {
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// This is the new msgpack format for metadata. It is a NamedMD containing
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// an MDTuple containing an MDString containing the msgpack data.
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BlobType = ELF::NT_AMDGPU_METADATA;
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auto MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0));
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if (MDN && MDN->getNumOperands()) {
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if (auto MDS = dyn_cast<MDString>(MDN->getOperand(0)))
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setFromMsgPackBlob(MDS->getString());
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}
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return;
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}
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BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA;
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NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
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if (!NamedMD || !NamedMD->getNumOperands())
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return;
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// This is the old reg=value pair format for metadata. It is a NamedMD
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// containing an MDTuple containing a number of MDNodes each of which is an
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// integer value, and each two integer values forms a key=value pair that we
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// store as Registers[key]=value in the map.
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auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
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if (!Tuple)
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return;
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@ -44,7 +57,7 @@ void AMDGPUPALMetadata::readFromIR(Module &M) {
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auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
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if (!Key || !Val)
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continue;
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Registers[Key->getZExtValue()] = Val->getZExtValue();
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setRegister(Key->getZExtValue(), Val->getZExtValue());
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}
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}
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@ -52,13 +65,26 @@ void AMDGPUPALMetadata::readFromIR(Module &M) {
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// Returns false if bad format. Blob must remain valid for the lifetime of the
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// Metadata.
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bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) {
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assert(Type == ELF::NT_AMD_AMDGPU_PAL_METADATA);
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BlobType = Type;
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if (Type == ELF::NT_AMD_AMDGPU_PAL_METADATA)
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return setFromLegacyBlob(Blob);
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return setFromMsgPackBlob(Blob);
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}
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// Set PAL metadata from legacy (array of key=value pairs) blob.
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bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) {
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auto Data = reinterpret_cast<const uint32_t *>(Blob.data());
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for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I)
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setRegister(Data[I * 2], Data[I * 2 + 1]);
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return true;
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}
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// Set PAL metadata from msgpack blob.
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bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) {
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msgpack::Reader Reader(Blob);
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return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false);
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}
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// Given the calling convention, calculate the register number for rsrc1. In
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// principle the register number could change in future hardware, but we know
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// it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
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@ -129,68 +155,541 @@ void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) {
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}
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// Get a register from the metadata, or 0 if not currently set.
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unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) { return Registers[Reg]; }
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unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) {
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auto Regs = getRegisters();
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auto It = Regs.find(MsgPackDoc.getNode(Reg));
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if (It == Regs.end())
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return 0;
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auto N = It->second;
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if (N.getKind() != msgpack::Type::UInt)
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return 0;
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return N.getUInt();
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}
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// Set a register in the metadata.
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// In fact this ORs the value into any previous setting of the register.
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void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) {
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Registers[Reg] |= Val;
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if (!isLegacy()) {
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// In the new MsgPack format, ignore register numbered >= 0x10000000. It
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// is a PAL ABI pseudo-register in the old non-MsgPack format.
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if (Reg >= 0x10000000)
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return;
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}
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auto &N = getRegisters()[MsgPackDoc.getNode(Reg)];
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if (N.getKind() == msgpack::Type::UInt)
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Val |= N.getUInt();
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N = N.getDocument()->getNode(Val);
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}
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// Set the number of used vgprs in the metadata. This is an optional advisory
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// record for logging etc; wave dispatch actually uses the rsrc1 register for
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// the shader stage to determine the number of vgprs to allocate.
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// Set the entry point name for one shader.
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void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) {
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if (isLegacy())
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return;
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// Msgpack format.
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getHwStage(CC)[".entry_point"] = MsgPackDoc.getNode(Name, /*Copy=*/true);
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}
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// Set the number of used vgprs in the metadata. This is an optional
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// advisory record for logging etc; wave dispatch actually uses the rsrc1
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// register for the shader stage to determine the number of vgprs to
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// allocate.
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void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) {
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unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
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PALMD::Key::VS_NUM_USED_VGPRS -
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PALMD::Key::VS_SCRATCH_SIZE;
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Registers[NumUsedVgprsKey] = Val;
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if (isLegacy()) {
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// Old non-msgpack format.
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unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
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PALMD::Key::VS_NUM_USED_VGPRS -
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PALMD::Key::VS_SCRATCH_SIZE;
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setRegister(NumUsedVgprsKey, Val);
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return;
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}
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// Msgpack format.
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getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val);
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}
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// Set the number of used sgprs in the metadata. This is an optional advisory
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// record for logging etc; wave dispatch actually uses the rsrc1 register for
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// the shader stage to determine the number of sgprs to allocate.
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void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) {
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unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
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PALMD::Key::VS_NUM_USED_SGPRS -
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PALMD::Key::VS_SCRATCH_SIZE;
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Registers[NumUsedSgprsKey] = Val;
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if (isLegacy()) {
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// Old non-msgpack format.
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unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
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PALMD::Key::VS_NUM_USED_SGPRS -
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PALMD::Key::VS_SCRATCH_SIZE;
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setRegister(NumUsedSgprsKey, Val);
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return;
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}
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// Msgpack format.
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getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val);
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}
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// Set the scratch size in the metadata.
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void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) {
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Registers[getScratchSizeKey(CC)] = Val;
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if (isLegacy()) {
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// Old non-msgpack format.
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setRegister(getScratchSizeKey(CC), Val);
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return;
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}
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// Msgpack format.
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getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val);
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}
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// Convert a register number to name, for display by toString().
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// Returns nullptr if none.
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static const char *getRegisterName(unsigned RegNum) {
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// Table of registers.
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static const struct RegInfo {
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unsigned Num;
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const char *Name;
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} RegInfoTable[] = {
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// Registers that code generation sets/modifies metadata for.
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{PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, "SPI_SHADER_PGM_RSRC1_VS"},
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{PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, "SPI_SHADER_PGM_RSRC2_VS"},
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{PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"},
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{PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"},
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{PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"},
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{PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"},
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{PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"},
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{PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"},
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{PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"},
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{PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"},
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{PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"},
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{PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"},
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{PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"},
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{PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"},
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{PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"},
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{PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"},
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// Registers not known to code generation.
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{0x2c07, "SPI_SHADER_PGM_RSRC3_PS"},
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{0x2c46, "SPI_SHADER_PGM_RSRC3_VS"},
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{0x2c87, "SPI_SHADER_PGM_RSRC3_GS"},
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{0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"},
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{0x2d07, "SPI_SHADER_PGM_RSRC3_HS"},
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{0x2d47, "SPI_SHADER_PGM_RSRC3_LS"},
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||||
{0xa1c3, "SPI_SHADER_POS_FORMAT"},
|
||||
{0xa1b1, "SPI_VS_OUT_CONFIG"},
|
||||
{0xa207, "PA_CL_VS_OUT_CNTL"},
|
||||
{0xa204, "PA_CL_CLIP_CNTL"},
|
||||
{0xa206, "PA_CL_VTE_CNTL"},
|
||||
{0xa2f9, "PA_SU_VTX_CNTL"},
|
||||
{0xa293, "PA_SC_MODE_CNTL_1"},
|
||||
{0xa2a1, "VGT_PRIMITIVEID_EN"},
|
||||
{0x2c81, "SPI_SHADER_PGM_RSRC4_GS"},
|
||||
{0x2e18, "COMPUTE_TMPRING_SIZE"},
|
||||
{0xa1b5, "SPI_INTERP_CONTROL_0"},
|
||||
{0xa1ba, "SPI_TMPRING_SIZE"},
|
||||
{0xa1c4, "SPI_SHADER_Z_FORMAT"},
|
||||
{0xa1c5, "SPI_SHADER_COL_FORMAT"},
|
||||
{0xa203, "DB_SHADER_CONTROL"},
|
||||
{0xa08f, "CB_SHADER_MASK"},
|
||||
{0xa1b6, "SPI_PS_IN_CONTROL"},
|
||||
{0xa191, "SPI_PS_INPUT_CNTL_0"},
|
||||
{0xa192, "SPI_PS_INPUT_CNTL_1"},
|
||||
{0xa193, "SPI_PS_INPUT_CNTL_2"},
|
||||
{0xa194, "SPI_PS_INPUT_CNTL_3"},
|
||||
{0xa195, "SPI_PS_INPUT_CNTL_4"},
|
||||
{0xa196, "SPI_PS_INPUT_CNTL_5"},
|
||||
{0xa197, "SPI_PS_INPUT_CNTL_6"},
|
||||
{0xa198, "SPI_PS_INPUT_CNTL_7"},
|
||||
{0xa199, "SPI_PS_INPUT_CNTL_8"},
|
||||
{0xa19a, "SPI_PS_INPUT_CNTL_9"},
|
||||
{0xa19b, "SPI_PS_INPUT_CNTL_10"},
|
||||
{0xa19c, "SPI_PS_INPUT_CNTL_11"},
|
||||
{0xa19d, "SPI_PS_INPUT_CNTL_12"},
|
||||
{0xa19e, "SPI_PS_INPUT_CNTL_13"},
|
||||
{0xa19f, "SPI_PS_INPUT_CNTL_14"},
|
||||
{0xa1a0, "SPI_PS_INPUT_CNTL_15"},
|
||||
{0xa1a1, "SPI_PS_INPUT_CNTL_16"},
|
||||
{0xa1a2, "SPI_PS_INPUT_CNTL_17"},
|
||||
{0xa1a3, "SPI_PS_INPUT_CNTL_18"},
|
||||
{0xa1a4, "SPI_PS_INPUT_CNTL_19"},
|
||||
{0xa1a5, "SPI_PS_INPUT_CNTL_20"},
|
||||
{0xa1a6, "SPI_PS_INPUT_CNTL_21"},
|
||||
{0xa1a7, "SPI_PS_INPUT_CNTL_22"},
|
||||
{0xa1a8, "SPI_PS_INPUT_CNTL_23"},
|
||||
{0xa1a9, "SPI_PS_INPUT_CNTL_24"},
|
||||
{0xa1aa, "SPI_PS_INPUT_CNTL_25"},
|
||||
{0xa1ab, "SPI_PS_INPUT_CNTL_26"},
|
||||
{0xa1ac, "SPI_PS_INPUT_CNTL_27"},
|
||||
{0xa1ad, "SPI_PS_INPUT_CNTL_28"},
|
||||
{0xa1ae, "SPI_PS_INPUT_CNTL_29"},
|
||||
{0xa1af, "SPI_PS_INPUT_CNTL_30"},
|
||||
{0xa1b0, "SPI_PS_INPUT_CNTL_31"},
|
||||
|
||||
{0xa2ce, "VGT_GS_MAX_VERT_OUT"},
|
||||
{0xa2ab, "VGT_ESGS_RING_ITEMSIZE"},
|
||||
{0xa290, "VGT_GS_MODE"},
|
||||
{0xa291, "VGT_GS_ONCHIP_CNTL"},
|
||||
{0xa2d7, "VGT_GS_VERT_ITEMSIZE"},
|
||||
{0xa2d8, "VGT_GS_VERT_ITEMSIZE_1"},
|
||||
{0xa2d9, "VGT_GS_VERT_ITEMSIZE_2"},
|
||||
{0xa2da, "VGT_GS_VERT_ITEMSIZE_3"},
|
||||
{0xa298, "VGT_GSVS_RING_OFFSET_1"},
|
||||
{0xa299, "VGT_GSVS_RING_OFFSET_2"},
|
||||
{0xa29a, "VGT_GSVS_RING_OFFSET_3"},
|
||||
|
||||
{0xa2e4, "VGT_GS_INSTANCE_CNT"},
|
||||
{0xa297, "VGT_GS_PER_VS"},
|
||||
{0xa29b, "VGT_GS_OUT_PRIM_TYPE"},
|
||||
{0xa2ac, "VGT_GSVS_RING_ITEMSIZE"},
|
||||
|
||||
{0xa2d5, "VGT_SHADER_STAGES_EN"},
|
||||
{0xa2ad, "VGT_REUSE_OFF"},
|
||||
{0xa1b8, "SPI_BARYC_CNTL"},
|
||||
|
||||
{0x2c4c, "SPI_SHADER_USER_DATA_VS_0"},
|
||||
{0x2c4d, "SPI_SHADER_USER_DATA_VS_1"},
|
||||
{0x2c4e, "SPI_SHADER_USER_DATA_VS_2"},
|
||||
{0x2c4f, "SPI_SHADER_USER_DATA_VS_3"},
|
||||
{0x2c50, "SPI_SHADER_USER_DATA_VS_4"},
|
||||
{0x2c51, "SPI_SHADER_USER_DATA_VS_5"},
|
||||
{0x2c52, "SPI_SHADER_USER_DATA_VS_6"},
|
||||
{0x2c53, "SPI_SHADER_USER_DATA_VS_7"},
|
||||
{0x2c54, "SPI_SHADER_USER_DATA_VS_8"},
|
||||
{0x2c55, "SPI_SHADER_USER_DATA_VS_9"},
|
||||
{0x2c56, "SPI_SHADER_USER_DATA_VS_10"},
|
||||
{0x2c57, "SPI_SHADER_USER_DATA_VS_11"},
|
||||
{0x2c58, "SPI_SHADER_USER_DATA_VS_12"},
|
||||
{0x2c59, "SPI_SHADER_USER_DATA_VS_13"},
|
||||
{0x2c5a, "SPI_SHADER_USER_DATA_VS_14"},
|
||||
{0x2c5b, "SPI_SHADER_USER_DATA_VS_15"},
|
||||
{0x2c5c, "SPI_SHADER_USER_DATA_VS_16"},
|
||||
{0x2c5d, "SPI_SHADER_USER_DATA_VS_17"},
|
||||
{0x2c5e, "SPI_SHADER_USER_DATA_VS_18"},
|
||||
{0x2c5f, "SPI_SHADER_USER_DATA_VS_19"},
|
||||
{0x2c60, "SPI_SHADER_USER_DATA_VS_20"},
|
||||
{0x2c61, "SPI_SHADER_USER_DATA_VS_21"},
|
||||
{0x2c62, "SPI_SHADER_USER_DATA_VS_22"},
|
||||
{0x2c63, "SPI_SHADER_USER_DATA_VS_23"},
|
||||
{0x2c64, "SPI_SHADER_USER_DATA_VS_24"},
|
||||
{0x2c65, "SPI_SHADER_USER_DATA_VS_25"},
|
||||
{0x2c66, "SPI_SHADER_USER_DATA_VS_26"},
|
||||
{0x2c67, "SPI_SHADER_USER_DATA_VS_27"},
|
||||
{0x2c68, "SPI_SHADER_USER_DATA_VS_28"},
|
||||
{0x2c69, "SPI_SHADER_USER_DATA_VS_29"},
|
||||
{0x2c6a, "SPI_SHADER_USER_DATA_VS_30"},
|
||||
{0x2c6b, "SPI_SHADER_USER_DATA_VS_31"},
|
||||
|
||||
{0x2ccc, "SPI_SHADER_USER_DATA_ES_0"},
|
||||
{0x2ccd, "SPI_SHADER_USER_DATA_ES_1"},
|
||||
{0x2cce, "SPI_SHADER_USER_DATA_ES_2"},
|
||||
{0x2ccf, "SPI_SHADER_USER_DATA_ES_3"},
|
||||
{0x2cd0, "SPI_SHADER_USER_DATA_ES_4"},
|
||||
{0x2cd1, "SPI_SHADER_USER_DATA_ES_5"},
|
||||
{0x2cd2, "SPI_SHADER_USER_DATA_ES_6"},
|
||||
{0x2cd3, "SPI_SHADER_USER_DATA_ES_7"},
|
||||
{0x2cd4, "SPI_SHADER_USER_DATA_ES_8"},
|
||||
{0x2cd5, "SPI_SHADER_USER_DATA_ES_9"},
|
||||
{0x2cd6, "SPI_SHADER_USER_DATA_ES_10"},
|
||||
{0x2cd7, "SPI_SHADER_USER_DATA_ES_11"},
|
||||
{0x2cd8, "SPI_SHADER_USER_DATA_ES_12"},
|
||||
{0x2cd9, "SPI_SHADER_USER_DATA_ES_13"},
|
||||
{0x2cda, "SPI_SHADER_USER_DATA_ES_14"},
|
||||
{0x2cdb, "SPI_SHADER_USER_DATA_ES_15"},
|
||||
{0x2cdc, "SPI_SHADER_USER_DATA_ES_16"},
|
||||
{0x2cdd, "SPI_SHADER_USER_DATA_ES_17"},
|
||||
{0x2cde, "SPI_SHADER_USER_DATA_ES_18"},
|
||||
{0x2cdf, "SPI_SHADER_USER_DATA_ES_19"},
|
||||
{0x2ce0, "SPI_SHADER_USER_DATA_ES_20"},
|
||||
{0x2ce1, "SPI_SHADER_USER_DATA_ES_21"},
|
||||
{0x2ce2, "SPI_SHADER_USER_DATA_ES_22"},
|
||||
{0x2ce3, "SPI_SHADER_USER_DATA_ES_23"},
|
||||
{0x2ce4, "SPI_SHADER_USER_DATA_ES_24"},
|
||||
{0x2ce5, "SPI_SHADER_USER_DATA_ES_25"},
|
||||
{0x2ce6, "SPI_SHADER_USER_DATA_ES_26"},
|
||||
{0x2ce7, "SPI_SHADER_USER_DATA_ES_27"},
|
||||
{0x2ce8, "SPI_SHADER_USER_DATA_ES_28"},
|
||||
{0x2ce9, "SPI_SHADER_USER_DATA_ES_29"},
|
||||
{0x2cea, "SPI_SHADER_USER_DATA_ES_30"},
|
||||
{0x2ceb, "SPI_SHADER_USER_DATA_ES_31"},
|
||||
|
||||
{0x2c0c, "SPI_SHADER_USER_DATA_PS_0"},
|
||||
{0x2c0d, "SPI_SHADER_USER_DATA_PS_1"},
|
||||
{0x2c0e, "SPI_SHADER_USER_DATA_PS_2"},
|
||||
{0x2c0f, "SPI_SHADER_USER_DATA_PS_3"},
|
||||
{0x2c10, "SPI_SHADER_USER_DATA_PS_4"},
|
||||
{0x2c11, "SPI_SHADER_USER_DATA_PS_5"},
|
||||
{0x2c12, "SPI_SHADER_USER_DATA_PS_6"},
|
||||
{0x2c13, "SPI_SHADER_USER_DATA_PS_7"},
|
||||
{0x2c14, "SPI_SHADER_USER_DATA_PS_8"},
|
||||
{0x2c15, "SPI_SHADER_USER_DATA_PS_9"},
|
||||
{0x2c16, "SPI_SHADER_USER_DATA_PS_10"},
|
||||
{0x2c17, "SPI_SHADER_USER_DATA_PS_11"},
|
||||
{0x2c18, "SPI_SHADER_USER_DATA_PS_12"},
|
||||
{0x2c19, "SPI_SHADER_USER_DATA_PS_13"},
|
||||
{0x2c1a, "SPI_SHADER_USER_DATA_PS_14"},
|
||||
{0x2c1b, "SPI_SHADER_USER_DATA_PS_15"},
|
||||
{0x2c1c, "SPI_SHADER_USER_DATA_PS_16"},
|
||||
{0x2c1d, "SPI_SHADER_USER_DATA_PS_17"},
|
||||
{0x2c1e, "SPI_SHADER_USER_DATA_PS_18"},
|
||||
{0x2c1f, "SPI_SHADER_USER_DATA_PS_19"},
|
||||
{0x2c20, "SPI_SHADER_USER_DATA_PS_20"},
|
||||
{0x2c21, "SPI_SHADER_USER_DATA_PS_21"},
|
||||
{0x2c22, "SPI_SHADER_USER_DATA_PS_22"},
|
||||
{0x2c23, "SPI_SHADER_USER_DATA_PS_23"},
|
||||
{0x2c24, "SPI_SHADER_USER_DATA_PS_24"},
|
||||
{0x2c25, "SPI_SHADER_USER_DATA_PS_25"},
|
||||
{0x2c26, "SPI_SHADER_USER_DATA_PS_26"},
|
||||
{0x2c27, "SPI_SHADER_USER_DATA_PS_27"},
|
||||
{0x2c28, "SPI_SHADER_USER_DATA_PS_28"},
|
||||
{0x2c29, "SPI_SHADER_USER_DATA_PS_29"},
|
||||
{0x2c2a, "SPI_SHADER_USER_DATA_PS_30"},
|
||||
{0x2c2b, "SPI_SHADER_USER_DATA_PS_31"},
|
||||
|
||||
{0x2e40, "COMPUTE_USER_DATA_0"},
|
||||
{0x2e41, "COMPUTE_USER_DATA_1"},
|
||||
{0x2e42, "COMPUTE_USER_DATA_2"},
|
||||
{0x2e43, "COMPUTE_USER_DATA_3"},
|
||||
{0x2e44, "COMPUTE_USER_DATA_4"},
|
||||
{0x2e45, "COMPUTE_USER_DATA_5"},
|
||||
{0x2e46, "COMPUTE_USER_DATA_6"},
|
||||
{0x2e47, "COMPUTE_USER_DATA_7"},
|
||||
{0x2e48, "COMPUTE_USER_DATA_8"},
|
||||
{0x2e49, "COMPUTE_USER_DATA_9"},
|
||||
{0x2e4a, "COMPUTE_USER_DATA_10"},
|
||||
{0x2e4b, "COMPUTE_USER_DATA_11"},
|
||||
{0x2e4c, "COMPUTE_USER_DATA_12"},
|
||||
{0x2e4d, "COMPUTE_USER_DATA_13"},
|
||||
{0x2e4e, "COMPUTE_USER_DATA_14"},
|
||||
{0x2e4f, "COMPUTE_USER_DATA_15"},
|
||||
|
||||
{0x2e07, "COMPUTE_NUM_THREAD_X"},
|
||||
{0x2e08, "COMPUTE_NUM_THREAD_Y"},
|
||||
{0x2e09, "COMPUTE_NUM_THREAD_Z"},
|
||||
{0xa2db, "VGT_TF_PARAM"},
|
||||
{0xa2d6, "VGT_LS_HS_CONFIG"},
|
||||
{0xa287, "VGT_HOS_MIN_TESS_LEVEL"},
|
||||
{0xa286, "VGT_HOS_MAX_TESS_LEVEL"},
|
||||
{0xa2f8, "PA_SC_AA_CONFIG"},
|
||||
{0xa310, "PA_SC_SHADER_CONTROL"},
|
||||
{0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"},
|
||||
|
||||
{0x2d0c, "SPI_SHADER_USER_DATA_LS_0"},
|
||||
{0x2d0d, "SPI_SHADER_USER_DATA_LS_1"},
|
||||
{0x2d0e, "SPI_SHADER_USER_DATA_LS_2"},
|
||||
{0x2d0f, "SPI_SHADER_USER_DATA_LS_3"},
|
||||
{0x2d10, "SPI_SHADER_USER_DATA_LS_4"},
|
||||
{0x2d11, "SPI_SHADER_USER_DATA_LS_5"},
|
||||
{0x2d12, "SPI_SHADER_USER_DATA_LS_6"},
|
||||
{0x2d13, "SPI_SHADER_USER_DATA_LS_7"},
|
||||
{0x2d14, "SPI_SHADER_USER_DATA_LS_8"},
|
||||
{0x2d15, "SPI_SHADER_USER_DATA_LS_9"},
|
||||
{0x2d16, "SPI_SHADER_USER_DATA_LS_10"},
|
||||
{0x2d17, "SPI_SHADER_USER_DATA_LS_11"},
|
||||
{0x2d18, "SPI_SHADER_USER_DATA_LS_12"},
|
||||
{0x2d19, "SPI_SHADER_USER_DATA_LS_13"},
|
||||
{0x2d1a, "SPI_SHADER_USER_DATA_LS_14"},
|
||||
{0x2d1b, "SPI_SHADER_USER_DATA_LS_15"},
|
||||
{0x2d1c, "SPI_SHADER_USER_DATA_LS_16"},
|
||||
{0x2d1d, "SPI_SHADER_USER_DATA_LS_17"},
|
||||
{0x2d1e, "SPI_SHADER_USER_DATA_LS_18"},
|
||||
{0x2d1f, "SPI_SHADER_USER_DATA_LS_19"},
|
||||
{0x2d20, "SPI_SHADER_USER_DATA_LS_20"},
|
||||
{0x2d21, "SPI_SHADER_USER_DATA_LS_21"},
|
||||
{0x2d22, "SPI_SHADER_USER_DATA_LS_22"},
|
||||
{0x2d23, "SPI_SHADER_USER_DATA_LS_23"},
|
||||
{0x2d24, "SPI_SHADER_USER_DATA_LS_24"},
|
||||
{0x2d25, "SPI_SHADER_USER_DATA_LS_25"},
|
||||
{0x2d26, "SPI_SHADER_USER_DATA_LS_26"},
|
||||
{0x2d27, "SPI_SHADER_USER_DATA_LS_27"},
|
||||
{0x2d28, "SPI_SHADER_USER_DATA_LS_28"},
|
||||
{0x2d29, "SPI_SHADER_USER_DATA_LS_29"},
|
||||
{0x2d2a, "SPI_SHADER_USER_DATA_LS_30"},
|
||||
{0x2d2b, "SPI_SHADER_USER_DATA_LS_31"},
|
||||
|
||||
{0xa2aa, "IA_MULTI_VGT_PARAM"},
|
||||
{0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"},
|
||||
{0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"},
|
||||
{0xa2e5, "VGT_STRMOUT_CONFIG"},
|
||||
{0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"},
|
||||
{0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"},
|
||||
{0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"},
|
||||
{0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"},
|
||||
{0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"},
|
||||
|
||||
{0, nullptr}};
|
||||
auto Entry = RegInfoTable;
|
||||
for (; Entry->Num && Entry->Num != RegNum; ++Entry)
|
||||
;
|
||||
return Entry->Name;
|
||||
}
|
||||
|
||||
// Convert the accumulated PAL metadata into an asm directive.
|
||||
void AMDGPUPALMetadata::toString(std::string &String) {
|
||||
String.clear();
|
||||
if (Registers.empty())
|
||||
return;
|
||||
raw_string_ostream Stream(String);
|
||||
Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' ';
|
||||
for (auto I = Registers.begin(), E = Registers.end(); I != E; ++I) {
|
||||
if (I != Registers.begin())
|
||||
Stream << ',';
|
||||
Stream << "0x" << Twine::utohexstr(I->first) << ",0x"
|
||||
<< Twine::utohexstr(I->second);
|
||||
if (isLegacy()) {
|
||||
if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil)
|
||||
return;
|
||||
// Old linear reg=val format.
|
||||
Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' ';
|
||||
auto Regs = getRegisters();
|
||||
for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
|
||||
if (I != Regs.begin())
|
||||
Stream << ',';
|
||||
unsigned Reg = I->first.getUInt();
|
||||
unsigned Val = I->second.getUInt();
|
||||
Stream << "0x" << Twine::utohexstr(Reg) << ",0x" << Twine::utohexstr(Val);
|
||||
}
|
||||
Stream << '\n';
|
||||
return;
|
||||
}
|
||||
Stream << '\n';
|
||||
|
||||
// New msgpack-based format -- output as YAML (with unsigned numbers in hex),
|
||||
// but first change the registers map to use names.
|
||||
MsgPackDoc.setHexMode();
|
||||
auto &RegsObj = refRegisters();
|
||||
auto OrigRegs = RegsObj.getMap();
|
||||
RegsObj = MsgPackDoc.getMapNode();
|
||||
for (auto I : OrigRegs) {
|
||||
auto Key = I.first;
|
||||
if (const char *RegName = getRegisterName(Key.getUInt())) {
|
||||
std::string KeyName = Key.toString();
|
||||
KeyName += " (";
|
||||
KeyName += RegName;
|
||||
KeyName += ')';
|
||||
Key = MsgPackDoc.getNode(KeyName, /*Copy=*/true);
|
||||
}
|
||||
RegsObj.getMap()[Key] = I.second;
|
||||
}
|
||||
|
||||
// Output as YAML.
|
||||
Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n';
|
||||
MsgPackDoc.toYAML(Stream);
|
||||
Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n';
|
||||
|
||||
// Restore original registers map.
|
||||
RegsObj = OrigRegs;
|
||||
}
|
||||
|
||||
// Convert the accumulated PAL metadata into a binary blob for writing as
|
||||
// a .note record of the specified AMD type.
|
||||
void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) {
|
||||
if (Type == ELF::NT_AMD_AMDGPU_PAL_METADATA)
|
||||
toLegacyBlob(Blob);
|
||||
else
|
||||
toMsgPackBlob(Blob);
|
||||
}
|
||||
|
||||
void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) {
|
||||
Blob.clear();
|
||||
if (Type != ELF::NT_AMD_AMDGPU_PAL_METADATA)
|
||||
return;
|
||||
if (Registers.empty())
|
||||
auto Registers = getRegisters();
|
||||
if (Registers.getMap().empty())
|
||||
return;
|
||||
raw_string_ostream OS(Blob);
|
||||
support::endian::Writer EW(OS, support::endianness::little);
|
||||
for (auto I : Registers) {
|
||||
EW.write(uint32_t(I.first));
|
||||
EW.write(uint32_t(I.second));
|
||||
for (auto I : Registers.getMap()) {
|
||||
EW.write(uint32_t(I.first.getUInt()));
|
||||
EW.write(uint32_t(I.second.getUInt()));
|
||||
}
|
||||
}
|
||||
|
||||
void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) {
|
||||
Blob.clear();
|
||||
MsgPackDoc.writeToBlob(Blob);
|
||||
}
|
||||
|
||||
// Set PAL metadata from YAML text. Returns false if failed.
|
||||
bool AMDGPUPALMetadata::setFromString(StringRef S) {
|
||||
BlobType = ELF::NT_AMDGPU_METADATA;
|
||||
if (!MsgPackDoc.fromYAML(S))
|
||||
return false;
|
||||
|
||||
// In the registers map, some keys may be of the form "0xa191
|
||||
// (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a
|
||||
// string. We need to turn it into a number.
|
||||
auto &RegsObj = refRegisters();
|
||||
auto OrigRegs = RegsObj;
|
||||
RegsObj = MsgPackDoc.getMapNode();
|
||||
Registers = RegsObj.getMap();
|
||||
bool Ok = true;
|
||||
for (auto I : OrigRegs.getMap()) {
|
||||
auto Key = I.first;
|
||||
if (Key.getKind() == msgpack::Type::String) {
|
||||
StringRef S = Key.getString();
|
||||
uint64_t Val;
|
||||
if (S.consumeInteger(0, Val)) {
|
||||
Ok = false;
|
||||
errs() << "Unrecognized PAL metadata register key '" << S << "'\n";
|
||||
continue;
|
||||
}
|
||||
Key = MsgPackDoc.getNode(uint64_t(Val));
|
||||
}
|
||||
Registers.getMap()[Key] = I.second;
|
||||
}
|
||||
return Ok;
|
||||
}
|
||||
|
||||
// Reference (create if necessary) the node for the registers map.
|
||||
msgpack::DocNode &AMDGPUPALMetadata::refRegisters() {
|
||||
auto &N =
|
||||
MsgPackDoc.getRoot()
|
||||
.getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
|
||||
.getArray(/*Convert=*/true)[0]
|
||||
.getMap(/*Convert=*/true)[MsgPackDoc.getNode(".registers")];
|
||||
N.getMap(/*Convert=*/true);
|
||||
return N;
|
||||
}
|
||||
|
||||
// Get (create if necessary) the registers map.
|
||||
msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() {
|
||||
if (Registers.isEmpty())
|
||||
Registers = refRegisters();
|
||||
return Registers.getMap();
|
||||
}
|
||||
|
||||
// Return the PAL metadata hardware shader stage name.
|
||||
static const char *getStageName(CallingConv::ID CC) {
|
||||
switch (CC) {
|
||||
case CallingConv::AMDGPU_PS:
|
||||
return ".ps";
|
||||
case CallingConv::AMDGPU_VS:
|
||||
return ".vs";
|
||||
case CallingConv::AMDGPU_GS:
|
||||
return ".gs";
|
||||
case CallingConv::AMDGPU_ES:
|
||||
return ".es";
|
||||
case CallingConv::AMDGPU_HS:
|
||||
return ".hs";
|
||||
case CallingConv::AMDGPU_LS:
|
||||
return ".ls";
|
||||
default:
|
||||
return ".cs";
|
||||
}
|
||||
}
|
||||
|
||||
// Get (create if necessary) the .hardware_stages entry for the given calling
|
||||
// convention.
|
||||
msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) {
|
||||
if (HwStages.isEmpty())
|
||||
HwStages = MsgPackDoc.getRoot()
|
||||
.getMap(/*Convert=*/true)["amdpal.pipelines"]
|
||||
.getArray(/*Convert=*/true)[0]
|
||||
.getMap(/*Convert=*/true)[".hardware_stages"]
|
||||
.getMap(/*Convert=*/true);
|
||||
return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true);
|
||||
}
|
||||
|
||||
// Get .note record vendor name of metadata blob to be emitted.
|
||||
const char *AMDGPUPALMetadata::getVendor() const {
|
||||
return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3;
|
||||
}
|
||||
|
||||
// Get .note record type of metadata blob to be emitted:
|
||||
// ELF::NT_AMD_AMDGPU_PAL_METADATA (legacy key=val format), or
|
||||
// ELF::NT_AMDGPU_METADATA (MsgPack format).
|
||||
unsigned AMDGPUPALMetadata::getType() const {
|
||||
return BlobType ? BlobType : unsigned(ELF::NT_AMDGPU_METADATA);
|
||||
}
|
||||
|
||||
// Return whether the blob type is legacy PAL metadata.
|
||||
bool AMDGPUPALMetadata::isLegacy() const {
|
||||
return BlobType == ELF::NT_AMD_AMDGPU_PAL_METADATA;
|
||||
}
|
||||
|
||||
// Set legacy PAL metadata format.
|
||||
void AMDGPUPALMetadata::setLegacy() {
|
||||
BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
#define LLVM_LIB_TARGET_AMDGPU_AMDGPUPALMETADATA_H
|
||||
|
||||
#include "llvm/ADT/StringRef.h"
|
||||
#include "llvm/BinaryFormat/MsgPackDocument.h"
|
||||
#include <map>
|
||||
|
||||
namespace llvm {
|
||||
|
|
@ -25,7 +26,10 @@ class MCStreamer;
|
|||
class Module;
|
||||
|
||||
class AMDGPUPALMetadata {
|
||||
std::map<uint32_t, uint32_t> Registers;
|
||||
unsigned BlobType = 0;
|
||||
msgpack::Document MsgPackDoc;
|
||||
msgpack::DocNode Registers;
|
||||
msgpack::DocNode HwStages;
|
||||
|
||||
public:
|
||||
// Read the amdgpu.pal.metadata supplied by the frontend, ready for
|
||||
|
|
@ -60,6 +64,9 @@ public:
|
|||
// In fact this ORs the value into any previous setting of the register.
|
||||
void setRegister(unsigned Reg, unsigned Val);
|
||||
|
||||
// Set the entry point name for one shader.
|
||||
void setEntryPoint(unsigned CC, StringRef Name);
|
||||
|
||||
// Set the number of used vgprs in the metadata. This is an optional advisory
|
||||
// record for logging etc; wave dispatch actually uses the rsrc1 register for
|
||||
// the shader stage to determine the number of vgprs to allocate.
|
||||
|
|
@ -73,13 +80,50 @@ public:
|
|||
// Set the scratch size in the metadata.
|
||||
void setScratchSize(unsigned CC, unsigned Val);
|
||||
|
||||
// Emit the accumulated PAL metadata as an asm directive.
|
||||
// Emit the accumulated PAL metadata as asm directives.
|
||||
// This is called from AMDGPUTargetAsmStreamer::Finish().
|
||||
void toString(std::string &S);
|
||||
|
||||
// Set PAL metadata from YAML text.
|
||||
bool setFromString(StringRef S);
|
||||
|
||||
// Get .note record vendor name of metadata blob to be emitted.
|
||||
const char *getVendor() const;
|
||||
|
||||
// Get .note record type of metadata blob to be emitted:
|
||||
// ELF::NT_AMD_AMDGPU_PAL_METADATA (legacy key=val format), or
|
||||
// ELF::NT_AMD_AMDGPU_PAL_METADATA_MSGPACK or ELF::NT_AMDGPU_METADATA
|
||||
// (MsgPack format).
|
||||
unsigned getType() const;
|
||||
|
||||
// Emit the accumulated PAL metadata as a binary blob.
|
||||
// This is called from AMDGPUTargetELFStreamer::Finish().
|
||||
void toBlob(unsigned Type, std::string &S);
|
||||
|
||||
// Get the msgpack::Document for the PAL metadata.
|
||||
msgpack::Document *getMsgPackDoc() { return &MsgPackDoc; }
|
||||
|
||||
// Set legacy PAL metadata format.
|
||||
void setLegacy();
|
||||
|
||||
private:
|
||||
// Return whether the blob type is legacy PAL metadata.
|
||||
bool isLegacy() const;
|
||||
|
||||
// Reference (create if necessary) the node for the registers map.
|
||||
msgpack::DocNode &refRegisters();
|
||||
|
||||
// Get (create if necessary) the registers map.
|
||||
msgpack::MapDocNode getRegisters();
|
||||
|
||||
// Get (create if necessary) the .hardware_stages entry for the given calling
|
||||
// convention.
|
||||
msgpack::MapDocNode getHwStage(unsigned CC);
|
||||
|
||||
bool setFromLegacyBlob(StringRef Blob);
|
||||
bool setFromMsgPackBlob(StringRef Blob);
|
||||
void toLegacyBlob(std::string &Blob);
|
||||
void toMsgPackBlob(std::string &Blob);
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s
|
||||
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s
|
||||
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
|
||||
|
||||
; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata
|
||||
; GCN-LABEL: {{^}}cs_amdpal:
|
||||
; GCN: .amdgpu_pal_metadata
|
||||
; GCN: 0x2e12 (COMPUTE_PGM_RSRC1)
|
||||
define amdgpu_cs half @cs_amdpal(half %arg0) {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; Force MsgPack format metadata
|
||||
!amdgpu.pal.metadata.msgpack = !{!0}
|
||||
!0 = !{!""}
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
||||
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
||||
|
||||
; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata
|
||||
; GCN-LABEL: {{^}}es_amdpal:
|
||||
; GCN: .amdgpu_pal_metadata
|
||||
; GCN: 0x2cca (SPI_SHADER_PGM_RSRC1_ES)
|
||||
define amdgpu_es half @es_amdpal(half %arg0) {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; Force MsgPack format metadata
|
||||
!amdgpu.pal.metadata.msgpack = !{!0}
|
||||
!0 = !{!""}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
||||
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
||||
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
|
||||
|
||||
; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata
|
||||
; GCN-LABEL: {{^}}gs_amdpal:
|
||||
; GCN: .amdgpu_pal_metadata
|
||||
; GCN: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS)
|
||||
define amdgpu_gs half @gs_amdpal(half %arg0) {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; Force MsgPack format metadata
|
||||
!amdgpu.pal.metadata.msgpack = !{!0}
|
||||
!0 = !{!""}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
||||
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
||||
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
|
||||
|
||||
; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata
|
||||
; GCN-LABEL: {{^}}hs_amdpal:
|
||||
; GCN: .amdgpu_pal_metadata
|
||||
; GCN: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS)
|
||||
define amdgpu_hs half @hs_amdpal(half %arg0) {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; Force MsgPack format metadata
|
||||
!amdgpu.pal.metadata.msgpack = !{!0}
|
||||
!0 = !{!""}
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
||||
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
||||
|
||||
; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata
|
||||
; GCN-LABEL: {{^}}ls_amdpal:
|
||||
; GCN: .amdgpu_pal_metadata
|
||||
; GCN: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS)
|
||||
define amdgpu_ls half @ls_amdpal(half %arg0) {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; Force MsgPack format metadata
|
||||
!amdgpu.pal.metadata.msgpack = !{!0}
|
||||
!0 = !{!""}
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
||||
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
||||
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
|
||||
|
||||
; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal
|
||||
; metadata. Check for 0x2c0b (SPI_SHADER_PGM_RSRC2_PS) in pal metadata, and
|
||||
; it has a value starting 0x42 as it is set to 0x42000000 in the metadata
|
||||
; below. Also check that .internal_pipeline_hash is propagated.
|
||||
; GCN-LABEL: {{^}}ps_amdpal:
|
||||
; GCN: .amdgpu_pal_metadata
|
||||
; GCN: .internal_pipeline_hash:
|
||||
; GCN-NEXT: - 0x123456789abcdef0
|
||||
; GCN-NEXT: - 0xfedcba9876543210
|
||||
; GCN: .registers:
|
||||
; GCN: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS):
|
||||
; GCN: 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42
|
||||
define amdgpu_ps half @ps_amdpal(half %arg0) {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; amdgpu.pal.metadata.msgpack represents this:
|
||||
;
|
||||
; .amdgpu_pal_metadata
|
||||
; ---
|
||||
; amdpal.pipelines:
|
||||
; - .internal_pipeline_hash:
|
||||
; - 0x123456789abcdef0
|
||||
; - 0xfedcba9876543210
|
||||
; .registers:
|
||||
; 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000
|
||||
; ...
|
||||
; .end_amdgpu_pal_metadata
|
||||
|
||||
!amdgpu.pal.metadata.msgpack = !{!0}
|
||||
!0 = !{!"\81\b0\61\6d\64\70\61\6c\2e\70\69\70\65\6c\69\6e\65\73\91\82\b7\2e\69\6e\74\65\72\6e\61\6c\5f\70\69\70\65\6c\69\6e\65\5f\68\61\73\68\92\cf\12\34\56\78\9a\bc\de\f0\cf\fe\dc\ba\98\76\54\32\10\aa\2e\72\65\67\69\73\74\65\72\73\81\cd\2c\0b\ce\42\00\00\00"};
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
||||
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
||||
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
|
||||
|
||||
; This pixel shader does not use the result of its interpolation, so it would
|
||||
; end up with an interpolation mode set in PSAddr but not PSEnable. This test tests
|
||||
; the workaround that ensures that an interpolation mode is also set in PSEnable.
|
||||
; GCN-LABEL: {{^}}amdpal_psenable:
|
||||
; GCN: .amdgpu_pal_metadata
|
||||
; GCN: 0xa1b3 (SPI_PS_INPUT_ENA): 0x2
|
||||
; GCN: 0xa1b4 (SPI_PS_INPUT_ADDR): 0x2
|
||||
define amdgpu_ps void @amdpal_psenable(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <2 x float> %pos) #6 {
|
||||
%inst23 = extractelement <2 x float> %pos, i32 0
|
||||
%inst24 = extractelement <2 x float> %pos, i32 1
|
||||
%inst25 = tail call float @llvm.amdgcn.interp.p1(float %inst23, i32 0, i32 0, i32 %m0)
|
||||
%inst26 = tail call float @llvm.amdgcn.interp.p2(float %inst25, float %inst24, i32 0, i32 0, i32 %m0)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #2
|
||||
declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #2
|
||||
|
||||
attributes #6 = { nounwind "InitialPSInputAddr"="2" }
|
||||
|
||||
; Force MsgPack format metadata
|
||||
!amdgpu.pal.metadata.msgpack = !{!0}
|
||||
!0 = !{!""}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
||||
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
||||
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
|
||||
|
||||
; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata
|
||||
; GCN-LABEL: {{^}}vs_amdpal:
|
||||
; GCN: .amdgpu_pal_metadata
|
||||
; GCN: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS)
|
||||
define amdgpu_vs half @vs_amdpal(half %arg0) {
|
||||
%add = fadd half %arg0, 1.0
|
||||
ret half %add
|
||||
}
|
||||
|
||||
; Force MsgPack format metadata
|
||||
!amdgpu.pal.metadata.msgpack = !{!0}
|
||||
!0 = !{!""}
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
// RUN: llvm-mc -triple amdgcn--amdpal -mcpu=kaveri -show-encoding %s | FileCheck %s --check-prefix=ASM
|
||||
// RUN: llvm-mc -filetype=obj -triple amdgcn--amdpal -mcpu=kaveri -show-encoding %s | llvm-readobj -symbols -s -sd | FileCheck %s --check-prefix=ELF
|
||||
|
||||
.amdgpu_pal_metadata
|
||||
---
|
||||
amdpal.pipelines:
|
||||
- .hardware_stages:
|
||||
.ps:
|
||||
.entry_point: ps_amdpal
|
||||
.scratch_memory_size: 0
|
||||
.sgpr_count: 0x1
|
||||
.vgpr_count: 0x1
|
||||
.internal_pipeline_hash:
|
||||
- 0x123456789abcdef0
|
||||
- 0xfedcba9876543210
|
||||
.registers:
|
||||
0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0
|
||||
0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000
|
||||
0xa1b3 (SPI_PS_INPUT_ENA): 0x1
|
||||
0xa1b4 (SPI_PS_INPUT_ADDR): 0x1
|
||||
...
|
||||
.end_amdgpu_pal_metadata
|
||||
|
||||
// ASM: .amdgpu_pal_metadata
|
||||
// ASM: ---
|
||||
// ASM: amdpal.pipelines:
|
||||
// ASM: - .hardware_stages:
|
||||
// ASM: .ps:
|
||||
// ASM: .entry_point: ps_amdpal
|
||||
// ASM: .scratch_memory_size: 0
|
||||
// ASM: .sgpr_count: 0x1
|
||||
// ASM: .vgpr_count: 0x1
|
||||
// ASM: .internal_pipeline_hash:
|
||||
// ASM: - 0x123456789abcdef0
|
||||
// ASM: - 0xfedcba9876543210
|
||||
// ASM: .registers:
|
||||
// ASM: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0
|
||||
// ASM: 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000
|
||||
// ASM: 0xa1b3 (SPI_PS_INPUT_ENA): 0x1
|
||||
// ASM: 0xa1b4 (SPI_PS_INPUT_ADDR): 0x1
|
||||
// ASM: ...
|
||||
// ASM: .end_amdgpu_pal_metadata
|
||||
|
||||
// ELF: SHT_NOTE
|
||||
// ELF: 0000: 07000000 BD000000 20000000 414D4447 |........ ...AMDG|
|
||||
// ELF: 0010: 50550000 81B0616D 6470616C 2E706970 |PU....amdpal.pip|
|
||||
// ELF: 0020: 656C696E 65739183 B02E6861 72647761 |elines....hardwa|
|
||||
// ELF: 0030: 72655F73 74616765 7381A32E 707384AC |re_stages...ps..|
|
||||
// ELF: 0040: 2E656E74 72795F70 6F696E74 A970735F |.entry_point.ps_|
|
||||
// ELF: 0050: 616D6470 616CB42E 73637261 7463685F |amdpal..scratch_|
|
||||
// ELF: 0060: 6D656D6F 72795F73 697A6500 AB2E7367 |memory_size...sg|
|
||||
// ELF: 0070: 70725F63 6F756E74 01AB2E76 6770725F |pr_count...vgpr_|
|
||||
// ELF: 0080: 636F756E 7401B72E 696E7465 726E616C |count...internal|
|
||||
// ELF: 0090: 5F706970 656C696E 655F6861 736892CF |_pipeline_hash..|
|
||||
// ELF: 00A0: 12345678 9ABCDEF0 CFFEDCBA 98765432 |.4Vx.........vT2|
|
||||
// ELF: 00B0: 10AA2E72 65676973 74657273 84CD2C0A |...registers..,.|
|
||||
// ELF: 00C0: 00CD2C0B CE420000 00CDA1B3 01CDA1B4 |..,..B..........|
|
||||
// ELF: 00D0: 01000000 |....|
|
||||
|
||||
|
||||
Loading…
Reference in New Issue