maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[RISCV][RFC] add MC support for zbkc subextension 

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117874
This commit is contained in:
Alex Fan 2022-01-21 19:51:09 +08:00
parent b95150418f
commit e796eaf2af
10 changed files with 65 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
llvm/lib/Support/RISCVISAInfo.cpp
View File

@ -57,6 +57,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"zbs", RISCVExtensionVersion{1, 0}},
{"zbkb", RISCVExtensionVersion{1, 0}},
{"zbkc", RISCVExtensionVersion{1, 0}},
};
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {

15
llvm/lib/Target/RISCV/RISCV.td
View File

@ -163,6 +163,21 @@ def HasStdExtZbbOrZbpOrZbkb
"'Zbp' (Permutation 'B' Instructions) or "
"'Zbkb' (Bitmanip instructions for Cryptography)">;
// The Carry-less multiply subextension for cryptography is a subset of basic carry-less multiply subextension. The former should be enabled if the latter is enabled.
def FeatureStdExtZbkc
: SubtargetFeature<"zbkc", "HasStdExtZbkc", "true",
"'Zbkc' (Carry-less multiply instructions for Cryptography)">;
def HasStdExtZbkc
: Predicate<"Subtarget->hasStdExtZbkc()">,
AssemblerPredicate<(all_of FeatureStdExtZbkc),
"'Zbkc' (Carry-less multiply instructions for Cryptography)">;
def HasStdExtZbcOrZbkc
: Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">,
AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc),
"'Zbc' (Carry-Less 'B' Instructions) or "
"'Zbkc' (Carry-less multiply instructions for Cryptography)">;
def FeatureNoRVCHints
: SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
"Disable RVC Hint Instructions.">;

9
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
View File

@ -440,13 +440,16 @@ def CRC32CD : RVBUnary<0b0110000, 0b11011, 0b001, OPC_OP_IMM, "crc32c.d">,
Sched<[]>;
let Predicates = [HasStdExtZbc] in {
def CLMUL : ALU_rr<0b0000101, 0b001, "clmul">,
Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>;
def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr">,
Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>;
} // Predicates = [HasStdExtZbc]
let Predicates = [HasStdExtZbcOrZbkc] in {
def CLMUL : ALU_rr<0b0000101, 0b001, "clmul">,
Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>;
def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh">,
Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>;
} // Predicates = [HasStdExtZbc]
} // Predicates = [HasStdExtZbcOrZbkc]
let Predicates = [HasStdExtZbb] in {
def MIN : ALU_rr<0b0000101, 0b100, "min">,

2
llvm/lib/Target/RISCV/RISCVSchedRocket.td
View File

@ -17,7 +17,7 @@ def RocketModel : SchedMachineModel {
let LoadLatency = 3;
let MispredictPenalty = 3;
let CompleteModel = false;
let UnsupportedFeatures = [HasStdExtZbkb, HasVInstructions, HasVInstructionsI64];
let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasVInstructions, HasVInstructionsI64];
}
//===----------------------------------------------------------------------===//

2
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
View File

@ -15,7 +15,7 @@ def SiFive7Model : SchedMachineModel {
let LoadLatency = 3;
let MispredictPenalty = 3;
let CompleteModel = 0;
let UnsupportedFeatures = [HasStdExtZbkb, HasVInstructions];
let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasVInstructions];
}
// The SiFive7 microarchitecture has two pipelines: A and B.

2
llvm/lib/Target/RISCV/RISCVSubtarget.h
View File

@ -84,6 +84,7 @@ private:
bool HasStdExtZfhmin = false;
bool HasStdExtZfh = false;
bool HasStdExtZbkb = false;
bool HasStdExtZbkc = false;
bool HasRV64 = false;
bool IsRV32E = false;
bool EnableLinkerRelax = false;
@ -158,6 +159,7 @@ public:
bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
bool hasStdExtZfh() const { return HasStdExtZfh; }
bool hasStdExtZbkb() const { return HasStdExtZbkb; }
bool hasStdExtZbkc() const { return HasStdExtZbkc; }
bool is64Bit() const { return HasRV64; }
bool isRV32E() const { return IsRV32E; }
bool enableLinkerRelax() const { return EnableLinkerRelax; }

4
llvm/test/CodeGen/RISCV/attributes.ll
View File

@ -20,6 +20,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV32V %s
; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV32COMBINED %s
; RUN: llc -mtriple=riscv32 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV32ZBKB %s
; RUN: llc -mtriple=riscv32 -mattr=+zbkc %s -o - | FileCheck --check-prefix=RV32ZBKC %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@ -40,6 +41,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV64V %s
; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV64COMBINED %s
; RUN: llc -mtriple=riscv64 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV64ZBKB %s
; RUN: llc -mtriple=riscv64 -mattr=+zbkc %s -o - | FileCheck --check-prefix=RV64ZBKC %s
; RV32M: .attribute 5, "rv32i2p0_m2p0"
@ -62,6 +64,7 @@
; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zfhmin1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"
; RV32ZBKC: .attribute 5, "rv32i2p0_zbkc1p0"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64A: .attribute 5, "rv64i2p0_a2p0"
@ -83,6 +86,7 @@
; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zfhmin1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"
; RV64ZBKC: .attribute 5, "rv64i2p0_zbkc1p0"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1

3
llvm/test/MC/RISCV/attribute-arch.s
View File

@ -130,3 +130,6 @@
.attribute arch, "rv32i_zbkb1p0"
# CHECK: attribute 5, "rv32i2p0_zbkb1p0"
.attribute arch, "rv32i_zbkc1p0"
# CHECK: attribute 5, "rv32i2p0_zbkc1p0"

9
llvm/test/MC/RISCV/rv32zbkc-invalid.s Normal file
View File

@ -0,0 +1,9 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+zbkc < %s 2>&1 | FileCheck %s
# Too few operands
clmul t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
clmulh t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Undefined zbc instruction in zbkc
clmulr t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less 'B' Instructions)

23
llvm/test/MC/RISCV/rv32zbkc-valid.s Normal file
View File

@ -0,0 +1,23 @@
# With Bitmanip carry-less multiply extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbkc -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbkc -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbkc < %s \
# RUN: | llvm-objdump --mattr=+zbkc -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbkc < %s \
# RUN: | llvm-objdump --mattr=+zbkc -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbkc,+zbc -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbkc,+zbc < %s \
# RUN: | llvm-objdump --mattr=+zbkc,+zbc -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: clmul t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x0a]
clmul t0, t1, t2
# CHECK-ASM-AND-OBJ: clmulh t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x0a]
clmulh t0, t1, t2