forked from OSchip/llvm-project
[X86] Rename Subtarget Tuning Feature Flag Prefix. NFC.
As suggested on D107370, this patch renames the tuning feature flags to start with 'Tuning' instead of 'Feature'. Differential Revision: https://reviews.llvm.org/D107459
This commit is contained in:
Simon Pilgrim
parent
cc947e29ea
commit
e78bf49a58
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@ -1086,11 +1086,11 @@ unsigned X86AsmBackend::getMaximumNopSize() const {
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return 4;
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if (!STI.hasFeature(X86::FeatureNOPL) && !STI.hasFeature(X86::Mode64Bit))
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return 1;
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if (STI.getFeatureBits()[X86::FeatureFast7ByteNOP])
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if (STI.getFeatureBits()[X86::TuningFast7ByteNOP])
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return 7;
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if (STI.getFeatureBits()[X86::FeatureFast15ByteNOP])
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if (STI.getFeatureBits()[X86::TuningFast15ByteNOP])
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return 15;
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if (STI.getFeatureBits()[X86::FeatureFast11ByteNOP])
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if (STI.getFeatureBits()[X86::TuningFast11ByteNOP])
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return 11;
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// FIXME: handle 32-bit mode
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// 15-bytes is the longest single NOP instruction, but 10-bytes is
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@ -367,120 +367,120 @@ def FeatureLVILoadHardening
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// X86 Subtarget Tuning features
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//===----------------------------------------------------------------------===//
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def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
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def TuningSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
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"SHLD instruction is slow">;
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def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
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def TuningSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
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"PMULLD instruction is slow">;
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def FeatureSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow",
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def TuningSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow",
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"true",
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"PMADDWD is slower than PMULLD">;
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// FIXME: This should not apply to CPUs that do not have SSE.
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def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
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def TuningSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
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"IsUAMem16Slow", "true",
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"Slow unaligned 16-byte memory access">;
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def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
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def TuningSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
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"IsUAMem32Slow", "true",
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"Slow unaligned 32-byte memory access">;
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def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
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def TuningLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
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"Use LEA for adjusting the stack pointer">;
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def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
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def TuningSlowDivide32 : SubtargetFeature<"idivl-to-divb",
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"HasSlowDivide32", "true",
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"Use 8-bit divide for positive values less than 256">;
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def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
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def TuningSlowDivide64 : SubtargetFeature<"idivq-to-divl",
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"HasSlowDivide64", "true",
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"Use 32-bit divide for positive values less than 2^32">;
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def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
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def TuningPadShortFunctions : SubtargetFeature<"pad-short-functions",
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"PadShortFunctions", "true",
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"Pad short functions">;
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// On some processors, instructions that implicitly take two memory operands are
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// slow. In practice, this means that CALL, PUSH, and POP with memory operands
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// should be avoided in favor of a MOV + register CALL/PUSH/POP.
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def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
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def TuningSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
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"SlowTwoMemOps", "true",
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"Two memory operand instructions are slow">;
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def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
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def TuningLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
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"LEA instruction needs inputs at AG stage">;
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def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
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def TuningSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
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"LEA instruction with certain arguments is slow">;
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def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
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def TuningSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
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"LEA instruction with 3 ops or certain registers is slow">;
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def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
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def TuningSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
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"INC and DEC instructions are slower than ADD and SUB">;
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def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt",
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def TuningPOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt",
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"HasPOPCNTFalseDeps", "true",
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"POPCNT has a false dependency on dest register">;
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def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
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def TuningLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
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"HasLZCNTFalseDeps", "true",
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"LZCNT/TZCNT have a false dependency on dest register">;
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// On recent X86 (port bound) processors, its preferable to combine to a single shuffle
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// using a variable mask over multiple fixed shuffles.
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def FeatureFastVariableCrossLaneShuffle
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def TuningFastVariableCrossLaneShuffle
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: SubtargetFeature<"fast-variable-crosslane-shuffle",
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"HasFastVariableCrossLaneShuffle",
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"true", "Cross-lane shuffles with variable masks are fast">;
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def FeatureFastVariablePerLaneShuffle
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def TuningFastVariablePerLaneShuffle
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: SubtargetFeature<"fast-variable-perlane-shuffle",
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"HasFastVariablePerLaneShuffle",
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"true", "Per-lane shuffles with variable masks are fast">;
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// On some X86 processors, a vzeroupper instruction should be inserted after
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// using ymm/zmm registers before executing code that may use SSE instructions.
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def FeatureInsertVZEROUPPER
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def TuningInsertVZEROUPPER
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: SubtargetFeature<"vzeroupper",
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"InsertVZEROUPPER",
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"true", "Should insert vzeroupper instructions">;
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// FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
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// than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
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// TuningFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
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// than the corresponding NR code. TuningFastVectorFSQRT should be enabled if
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// vector FSQRT has higher throughput than the corresponding NR code.
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// The idea is that throughput bound code is likely to be vectorized, so for
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// vectorized code we should care about the throughput of SQRT operations.
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// But if the code is scalar that probably means that the code has some kind of
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// dependency and we should care more about reducing the latency.
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def FeatureFastScalarFSQRT
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def TuningFastScalarFSQRT
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: SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
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"true", "Scalar SQRT is fast (disable Newton-Raphson)">;
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def FeatureFastVectorFSQRT
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def TuningFastVectorFSQRT
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: SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
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"true", "Vector SQRT is fast (disable Newton-Raphson)">;
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// If lzcnt has equivalent latency/throughput to most simple integer ops, it can
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// be used to replace test/set sequences.
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def FeatureFastLZCNT
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def TuningFastLZCNT
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: SubtargetFeature<
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"fast-lzcnt", "HasFastLZCNT", "true",
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"LZCNT instructions are as fast as most simple integer ops">;
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// If the target can efficiently decode NOPs upto 7-bytes in length.
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def FeatureFast7ByteNOP
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def TuningFast7ByteNOP
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: SubtargetFeature<
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"fast-7bytenop", "HasFast7ByteNOP", "true",
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"Target can quickly decode up to 7 byte NOPs">;
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// If the target can efficiently decode NOPs upto 11-bytes in length.
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def FeatureFast11ByteNOP
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def TuningFast11ByteNOP
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: SubtargetFeature<
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"fast-11bytenop", "HasFast11ByteNOP", "true",
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"Target can quickly decode up to 11 byte NOPs">;
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// If the target can efficiently decode NOPs upto 15-bytes in length.
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def FeatureFast15ByteNOP
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def TuningFast15ByteNOP
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: SubtargetFeature<
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"fast-15bytenop", "HasFast15ByteNOP", "true",
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"Target can quickly decode up to 15 byte NOPs">;
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@ -488,21 +488,21 @@ def FeatureFast15ByteNOP
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// Sandy Bridge and newer processors can use SHLD with the same source on both
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// inputs to implement rotate to avoid the partial flag update of the normal
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// rotate instructions.
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def FeatureFastSHLDRotate
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def TuningFastSHLDRotate
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: SubtargetFeature<
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"fast-shld-rotate", "HasFastSHLDRotate", "true",
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"SHLD can be used as a faster rotate">;
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// Bulldozer and newer processors can merge CMP/TEST (but not other
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// instructions) with conditional branches.
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def FeatureBranchFusion
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def TuningBranchFusion
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: SubtargetFeature<"branchfusion", "HasBranchFusion", "true",
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"CMP/TEST can be fused with conditional branches">;
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// Sandy Bridge and newer processors have many instructions that can be
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// fused with conditional branches and pass through the CPU as a single
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// operation.
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def FeatureMacroFusion
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def TuningMacroFusion
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: SubtargetFeature<"macrofusion", "HasMacroFusion", "true",
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"Various instructions can be fused with conditional branches">;
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@ -510,50 +510,50 @@ def FeatureMacroFusion
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// generate Gathers on all AVX2 processors. But the overhead on HSW is high.
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// Skylake Client processor has faster Gathers than HSW and performance is
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// similar to Skylake Server (AVX-512).
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def FeatureFastGather
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def TuningFastGather
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: SubtargetFeature<"fast-gather", "HasFastGather", "true",
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"Indicates if gather is reasonably fast">;
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def FeaturePrefer128Bit
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def TuningPrefer128Bit
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: SubtargetFeature<"prefer-128-bit", "Prefer128Bit", "true",
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"Prefer 128-bit AVX instructions">;
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def FeaturePrefer256Bit
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def TuningPrefer256Bit
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: SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true",
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"Prefer 256-bit AVX instructions">;
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def FeaturePreferMaskRegisters
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def TuningPreferMaskRegisters
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: SubtargetFeature<"prefer-mask-registers", "PreferMaskRegisters", "true",
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"Prefer AVX512 mask registers over PTEST/MOVMSK">;
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def FeatureFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true",
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def TuningFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true",
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"Indicates that the BEXTR instruction is implemented as a single uop "
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"with good throughput">;
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// Combine vector math operations with shuffles into horizontal math
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// instructions if a CPU implements horizontal operations (introduced with
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// SSE3) with better latency/throughput than the alternative sequence.
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def FeatureFastHorizontalOps
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def TuningFastHorizontalOps
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: SubtargetFeature<
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"fast-hops", "HasFastHorizontalOps", "true",
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"Prefer horizontal vector math instructions (haddp, phsub, etc.) over "
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"normal vector instructions with shuffles">;
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def FeatureFastScalarShiftMasks
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def TuningFastScalarShiftMasks
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: SubtargetFeature<
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"fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true",
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"Prefer a left/right scalar logical shift pair over a shift+and pair">;
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def FeatureFastVectorShiftMasks
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def TuningFastVectorShiftMasks
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: SubtargetFeature<
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"fast-vector-shift-masks", "HasFastVectorShiftMasks", "true",
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"Prefer a left/right vector logical shift pair over a shift+and pair">;
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def FeatureFastMOVBE
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def TuningFastMOVBE
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: SubtargetFeature<"fast-movbe", "HasFastMOVBE", "true",
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"Prefer a movbe over a single-use load + bswap / single-use bswap + store">;
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def FeatureUseGLMDivSqrtCosts
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def TuningUseGLMDivSqrtCosts
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: SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true",
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"Use Goldmont specific floating point div/sqrt costs">;
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@ -631,8 +631,8 @@ def ProcessorFeatures {
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// Nehalem
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list<SubtargetFeature> NHMFeatures = X86_64V2Features;
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list<SubtargetFeature> NHMTuning = [FeatureMacroFusion,
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FeatureInsertVZEROUPPER];
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list<SubtargetFeature> NHMTuning = [TuningMacroFusion,
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TuningInsertVZEROUPPER];
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// Westmere
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list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL];
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@ -644,15 +644,15 @@ def ProcessorFeatures {
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list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX,
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FeatureXSAVE,
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FeatureXSAVEOPT];
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list<SubtargetFeature> SNBTuning = [FeatureMacroFusion,
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FeatureSlow3OpsLEA,
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FeatureSlowDivide64,
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FeatureSlowUAMem32,
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FeatureFastScalarFSQRT,
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FeatureFastSHLDRotate,
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FeatureFast15ByteNOP,
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FeaturePOPCNTFalseDeps,
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FeatureInsertVZEROUPPER];
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list<SubtargetFeature> SNBTuning = [TuningMacroFusion,
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TuningSlow3OpsLEA,
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TuningSlowDivide64,
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TuningSlowUAMem32,
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TuningFastScalarFSQRT,
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TuningFastSHLDRotate,
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TuningFast15ByteNOP,
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TuningPOPCNTFalseDeps,
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TuningInsertVZEROUPPER];
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list<SubtargetFeature> SNBFeatures =
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!listconcat(WSMFeatures, SNBAdditionalFeatures);
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@ -673,17 +673,17 @@ def ProcessorFeatures {
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FeatureINVPCID,
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FeatureLZCNT,
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FeatureMOVBE];
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list<SubtargetFeature> HSWTuning = [FeatureMacroFusion,
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FeatureSlow3OpsLEA,
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FeatureSlowDivide64,
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FeatureFastScalarFSQRT,
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FeatureFastSHLDRotate,
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FeatureFast15ByteNOP,
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FeatureFastVariableCrossLaneShuffle,
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FeatureFastVariablePerLaneShuffle,
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FeaturePOPCNTFalseDeps,
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FeatureLZCNTFalseDeps,
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FeatureInsertVZEROUPPER];
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list<SubtargetFeature> HSWTuning = [TuningMacroFusion,
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TuningSlow3OpsLEA,
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TuningSlowDivide64,
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TuningFastScalarFSQRT,
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TuningFastSHLDRotate,
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TuningFast15ByteNOP,
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TuningFastVariableCrossLaneShuffle,
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TuningFastVariablePerLaneShuffle,
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TuningPOPCNTFalseDeps,
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TuningLZCNTFalseDeps,
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TuningInsertVZEROUPPER];
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list<SubtargetFeature> HSWFeatures =
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!listconcat(IVBFeatures, HSWAdditionalFeatures);
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@ -700,18 +700,18 @@ def ProcessorFeatures {
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FeatureXSAVEC,
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FeatureXSAVES,
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FeatureCLFLUSHOPT];
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list<SubtargetFeature> SKLTuning = [FeatureFastGather,
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FeatureMacroFusion,
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FeatureSlow3OpsLEA,
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FeatureSlowDivide64,
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FeatureFastScalarFSQRT,
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FeatureFastVectorFSQRT,
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FeatureFastSHLDRotate,
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FeatureFast15ByteNOP,
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FeatureFastVariableCrossLaneShuffle,
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FeatureFastVariablePerLaneShuffle,
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FeaturePOPCNTFalseDeps,
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FeatureInsertVZEROUPPER];
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list<SubtargetFeature> SKLTuning = [TuningFastGather,
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TuningMacroFusion,
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TuningSlow3OpsLEA,
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TuningSlowDivide64,
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TuningFastScalarFSQRT,
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TuningFastVectorFSQRT,
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TuningFastSHLDRotate,
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TuningFast15ByteNOP,
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TuningFastVariableCrossLaneShuffle,
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TuningFastVariablePerLaneShuffle,
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TuningPOPCNTFalseDeps,
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TuningInsertVZEROUPPER];
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list<SubtargetFeature> SKLFeatures =
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!listconcat(BDWFeatures, SKLAdditionalFeatures);
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@ -727,19 +727,19 @@ def ProcessorFeatures {
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FeatureVLX,
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FeaturePKU,
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FeatureCLWB];
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list<SubtargetFeature> SKXTuning = [FeatureFastGather,
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FeatureMacroFusion,
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FeatureSlow3OpsLEA,
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FeatureSlowDivide64,
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FeatureFastScalarFSQRT,
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FeatureFastVectorFSQRT,
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FeatureFastSHLDRotate,
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FeatureFast15ByteNOP,
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FeatureFastVariableCrossLaneShuffle,
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FeatureFastVariablePerLaneShuffle,
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FeaturePrefer256Bit,
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FeaturePOPCNTFalseDeps,
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FeatureInsertVZEROUPPER];
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list<SubtargetFeature> SKXTuning = [TuningFastGather,
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TuningMacroFusion,
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TuningSlow3OpsLEA,
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TuningSlowDivide64,
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TuningFastScalarFSQRT,
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TuningFastVectorFSQRT,
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TuningFastSHLDRotate,
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TuningFast15ByteNOP,
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TuningFastVariableCrossLaneShuffle,
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TuningFastVariablePerLaneShuffle,
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TuningPrefer256Bit,
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TuningPOPCNTFalseDeps,
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TuningInsertVZEROUPPER];
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list<SubtargetFeature> SKXFeatures =
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!listconcat(BDWFeatures, SKXAdditionalFeatures);
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@ -765,18 +765,18 @@ def ProcessorFeatures {
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FeatureVBMI,
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FeatureIFMA,
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FeatureSHA];
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list<SubtargetFeature> CNLTuning = [FeatureFastGather,
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FeatureMacroFusion,
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FeatureSlow3OpsLEA,
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FeatureSlowDivide64,
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FeatureFastScalarFSQRT,
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FeatureFastVectorFSQRT,
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FeatureFastSHLDRotate,
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FeatureFast15ByteNOP,
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FeatureFastVariableCrossLaneShuffle,
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FeatureFastVariablePerLaneShuffle,
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FeaturePrefer256Bit,
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FeatureInsertVZEROUPPER];
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list<SubtargetFeature> CNLTuning = [TuningFastGather,
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TuningMacroFusion,
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TuningSlow3OpsLEA,
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TuningSlowDivide64,
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TuningFastScalarFSQRT,
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TuningFastVectorFSQRT,
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TuningFastSHLDRotate,
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TuningFast15ByteNOP,
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TuningFastVariableCrossLaneShuffle,
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TuningFastVariablePerLaneShuffle,
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TuningPrefer256Bit,
|
||||
TuningInsertVZEROUPPER];
|
||||
list<SubtargetFeature> CNLFeatures =
|
||||
!listconcat(SKLFeatures, CNLAdditionalFeatures);
|
||||
|
||||
|
|
@ -846,14 +846,14 @@ def ProcessorFeatures {
|
|||
FeatureMOVBE,
|
||||
FeatureLAHFSAHF];
|
||||
list<SubtargetFeature> AtomTuning = [ProcIntelAtom,
|
||||
FeatureSlowUAMem16,
|
||||
FeatureLEAForSP,
|
||||
FeatureSlowDivide32,
|
||||
FeatureSlowDivide64,
|
||||
FeatureSlowTwoMemOps,
|
||||
FeatureLEAUsesAG,
|
||||
FeaturePadShortFunctions,
|
||||
FeatureInsertVZEROUPPER];
|
||||
TuningSlowUAMem16,
|
||||
TuningLEAForSP,
|
||||
TuningSlowDivide32,
|
||||
TuningSlowDivide64,
|
||||
TuningSlowTwoMemOps,
|
||||
TuningLEAUsesAG,
|
||||
TuningPadShortFunctions,
|
||||
TuningInsertVZEROUPPER];
|
||||
|
||||
// Silvermont
|
||||
list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42,
|
||||
|
|
@ -862,15 +862,15 @@ def ProcessorFeatures {
|
|||
FeaturePRFCHW,
|
||||
FeatureRDRAND];
|
||||
list<SubtargetFeature> SLMTuning = [ProcIntelSLM,
|
||||
FeatureSlowTwoMemOps,
|
||||
FeatureSlowLEA,
|
||||
FeatureSlowIncDec,
|
||||
FeatureSlowDivide64,
|
||||
FeatureSlowPMULLD,
|
||||
FeatureFast7ByteNOP,
|
||||
FeatureFastMOVBE,
|
||||
FeaturePOPCNTFalseDeps,
|
||||
FeatureInsertVZEROUPPER];
|
||||
TuningSlowTwoMemOps,
|
||||
TuningSlowLEA,
|
||||
TuningSlowIncDec,
|
||||
TuningSlowDivide64,
|
||||
TuningSlowPMULLD,
|
||||
TuningFast7ByteNOP,
|
||||
TuningFastMOVBE,
|
||||
TuningPOPCNTFalseDeps,
|
||||
TuningInsertVZEROUPPER];
|
||||
list<SubtargetFeature> SLMFeatures =
|
||||
!listconcat(AtomFeatures, SLMAdditionalFeatures);
|
||||
|
||||
|
|
@ -884,25 +884,25 @@ def ProcessorFeatures {
|
|||
FeatureXSAVES,
|
||||
FeatureCLFLUSHOPT,
|
||||
FeatureFSGSBase];
|
||||
list<SubtargetFeature> GLMTuning = [FeatureUseGLMDivSqrtCosts,
|
||||
FeatureSlowTwoMemOps,
|
||||
FeatureSlowLEA,
|
||||
FeatureSlowIncDec,
|
||||
FeatureFastMOVBE,
|
||||
FeaturePOPCNTFalseDeps,
|
||||
FeatureInsertVZEROUPPER];
|
||||
list<SubtargetFeature> GLMTuning = [TuningUseGLMDivSqrtCosts,
|
||||
TuningSlowTwoMemOps,
|
||||
TuningSlowLEA,
|
||||
TuningSlowIncDec,
|
||||
TuningFastMOVBE,
|
||||
TuningPOPCNTFalseDeps,
|
||||
TuningInsertVZEROUPPER];
|
||||
list<SubtargetFeature> GLMFeatures =
|
||||
!listconcat(SLMFeatures, GLMAdditionalFeatures);
|
||||
|
||||
// Goldmont Plus
|
||||
list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE,
|
||||
FeatureRDPID];
|
||||
list<SubtargetFeature> GLPTuning = [FeatureUseGLMDivSqrtCosts,
|
||||
FeatureSlowTwoMemOps,
|
||||
FeatureSlowLEA,
|
||||
FeatureSlowIncDec,
|
||||
FeatureFastMOVBE,
|
||||
FeatureInsertVZEROUPPER];
|
||||
list<SubtargetFeature> GLPTuning = [TuningUseGLMDivSqrtCosts,
|
||||
TuningSlowTwoMemOps,
|
||||
TuningSlowLEA,
|
||||
TuningSlowIncDec,
|
||||
TuningFastMOVBE,
|
||||
TuningInsertVZEROUPPER];
|
||||
list<SubtargetFeature> GLPFeatures =
|
||||
!listconcat(GLMFeatures, GLPAdditionalFeatures);
|
||||
|
||||
|
|
@ -969,14 +969,14 @@ def ProcessorFeatures {
|
|||
FeatureBMI2,
|
||||
FeatureFMA,
|
||||
FeaturePRFCHW];
|
||||
list<SubtargetFeature> KNLTuning = [FeatureSlowDivide64,
|
||||
FeatureSlow3OpsLEA,
|
||||
FeatureSlowIncDec,
|
||||
FeatureSlowTwoMemOps,
|
||||
FeaturePreferMaskRegisters,
|
||||
FeatureFastGather,
|
||||
FeatureFastMOVBE,
|
||||
FeatureSlowPMADDWD];
|
||||
list<SubtargetFeature> KNLTuning = [TuningSlowDivide64,
|
||||
TuningSlow3OpsLEA,
|
||||
TuningSlowIncDec,
|
||||
TuningSlowTwoMemOps,
|
||||
TuningPreferMaskRegisters,
|
||||
TuningFastGather,
|
||||
TuningFastMOVBE,
|
||||
TuningSlowPMADDWD];
|
||||
// TODO Add AVX5124FMAPS/AVX5124VNNIW features
|
||||
list<SubtargetFeature> KNMFeatures =
|
||||
!listconcat(KNLFeatures, [FeatureVPOPCNTDQ]);
|
||||
|
|
@ -995,9 +995,9 @@ def ProcessorFeatures {
|
|||
FeatureLAHFSAHF,
|
||||
FeatureCMOV,
|
||||
Feature64Bit];
|
||||
list<SubtargetFeature> BarcelonaTuning = [FeatureFastScalarShiftMasks,
|
||||
FeatureSlowSHLD,
|
||||
FeatureInsertVZEROUPPER];
|
||||
list<SubtargetFeature> BarcelonaTuning = [TuningFastScalarShiftMasks,
|
||||
TuningSlowSHLD,
|
||||
TuningInsertVZEROUPPER];
|
||||
|
||||
// Bobcat
|
||||
list<SubtargetFeature> BtVer1Features = [FeatureX87,
|
||||
|
|
@ -1014,11 +1014,11 @@ def ProcessorFeatures {
|
|||
FeatureLZCNT,
|
||||
FeaturePOPCNT,
|
||||
FeatureLAHFSAHF];
|
||||
list<SubtargetFeature> BtVer1Tuning = [FeatureFast15ByteNOP,
|
||||
FeatureFastScalarShiftMasks,
|
||||
FeatureFastVectorShiftMasks,
|
||||
FeatureSlowSHLD,
|
||||
FeatureInsertVZEROUPPER];
|
||||
list<SubtargetFeature> BtVer1Tuning = [TuningFast15ByteNOP,
|
||||
TuningFastScalarShiftMasks,
|
||||
TuningFastVectorShiftMasks,
|
||||
TuningSlowSHLD,
|
||||
TuningInsertVZEROUPPER];
|
||||
|
||||
// Jaguar
|
||||
list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX,
|
||||
|
|
@ -1029,14 +1029,14 @@ def ProcessorFeatures {
|
|||
FeatureMOVBE,
|
||||
FeatureXSAVE,
|
||||
FeatureXSAVEOPT];
|
||||
list<SubtargetFeature> BtVer2Tuning = [FeatureFastLZCNT,
|
||||
FeatureFastBEXTR,
|
||||
FeatureFastHorizontalOps,
|
||||
FeatureFast15ByteNOP,
|
||||
FeatureFastScalarShiftMasks,
|
||||
FeatureFastVectorShiftMasks,
|
||||
FeatureFastMOVBE,
|
||||
FeatureSlowSHLD];
|
||||
list<SubtargetFeature> BtVer2Tuning = [TuningFastLZCNT,
|
||||
TuningFastBEXTR,
|
||||
TuningFastHorizontalOps,
|
||||
TuningFast15ByteNOP,
|
||||
TuningFastScalarShiftMasks,
|
||||
TuningFastVectorShiftMasks,
|
||||
TuningFastMOVBE,
|
||||
TuningSlowSHLD];
|
||||
list<SubtargetFeature> BtVer2Features =
|
||||
!listconcat(BtVer1Features, BtVer2AdditionalFeatures);
|
||||
|
||||
|
|
@ -1058,19 +1058,19 @@ def ProcessorFeatures {
|
|||
FeatureXSAVE,
|
||||
FeatureLWP,
|
||||
FeatureLAHFSAHF];
|
||||
list<SubtargetFeature> BdVer1Tuning = [FeatureSlowSHLD,
|
||||
FeatureFast11ByteNOP,
|
||||
FeatureFastScalarShiftMasks,
|
||||
FeatureBranchFusion,
|
||||
FeatureInsertVZEROUPPER];
|
||||
list<SubtargetFeature> BdVer1Tuning = [TuningSlowSHLD,
|
||||
TuningFast11ByteNOP,
|
||||
TuningFastScalarShiftMasks,
|
||||
TuningBranchFusion,
|
||||
TuningInsertVZEROUPPER];
|
||||
|
||||
// PileDriver
|
||||
list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C,
|
||||
FeatureBMI,
|
||||
FeatureTBM,
|
||||
FeatureFMA];
|
||||
list<SubtargetFeature> BdVer2AdditionalTuning = [FeatureFastBEXTR,
|
||||
FeatureFastMOVBE];
|
||||
list<SubtargetFeature> BdVer2AdditionalTuning = [TuningFastBEXTR,
|
||||
TuningFastMOVBE];
|
||||
list<SubtargetFeature> BdVer2Tuning =
|
||||
!listconcat(BdVer1Tuning, BdVer2AdditionalTuning);
|
||||
list<SubtargetFeature> BdVer2Features =
|
||||
|
|
@ -1127,14 +1127,14 @@ def ProcessorFeatures {
|
|||
FeatureXSAVEC,
|
||||
FeatureXSAVEOPT,
|
||||
FeatureXSAVES];
|
||||
list<SubtargetFeature> ZNTuning = [FeatureFastLZCNT,
|
||||
FeatureFastBEXTR,
|
||||
FeatureFast15ByteNOP,
|
||||
FeatureBranchFusion,
|
||||
FeatureFastScalarShiftMasks,
|
||||
FeatureFastMOVBE,
|
||||
FeatureSlowSHLD,
|
||||
FeatureInsertVZEROUPPER];
|
||||
list<SubtargetFeature> ZNTuning = [TuningFastLZCNT,
|
||||
TuningFastBEXTR,
|
||||
TuningFast15ByteNOP,
|
||||
TuningBranchFusion,
|
||||
TuningFastScalarShiftMasks,
|
||||
TuningFastMOVBE,
|
||||
TuningSlowSHLD,
|
||||
TuningInsertVZEROUPPER];
|
||||
list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB,
|
||||
FeatureRDPID,
|
||||
FeatureWBNOINVD];
|
||||
|
|
@ -1147,8 +1147,8 @@ def ProcessorFeatures {
|
|||
FeatureVAES,
|
||||
FeatureVPCLMULQDQ];
|
||||
list<SubtargetFeature> ZN3AdditionalTuning =
|
||||
[FeatureMacroFusion,
|
||||
FeatureFastVariablePerLaneShuffle];
|
||||
[TuningMacroFusion,
|
||||
TuningFastVariablePerLaneShuffle];
|
||||
list<SubtargetFeature> ZN3Tuning =
|
||||
!listconcat(ZNTuning, ZN3AdditionalTuning);
|
||||
list<SubtargetFeature> ZN3Features =
|
||||
|
|
@ -1175,37 +1175,37 @@ class ProcModel<string Name, SchedMachineModel Model,
|
|||
// It has no effect on code generation.
|
||||
def : ProcModel<"generic", SandyBridgeModel,
|
||||
[FeatureX87, FeatureCMPXCHG8B, Feature64Bit],
|
||||
[FeatureSlow3OpsLEA,
|
||||
FeatureSlowDivide64,
|
||||
FeatureSlowIncDec,
|
||||
FeatureMacroFusion,
|
||||
FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlow3OpsLEA,
|
||||
TuningSlowDivide64,
|
||||
TuningSlowIncDec,
|
||||
TuningMacroFusion,
|
||||
TuningInsertVZEROUPPER]>;
|
||||
|
||||
def : Proc<"i386", [FeatureX87],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
def : Proc<"i486", [FeatureX87],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
def : Proc<"i586", [FeatureX87, FeatureCMPXCHG8B],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
def : Proc<"pentium", [FeatureX87, FeatureCMPXCHG8B],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
def : Proc<"pentium-mmx", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
|
||||
def : Proc<"i686", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
def : Proc<"pentiumpro", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV,
|
||||
FeatureNOPL],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
|
||||
def : Proc<"pentium2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureCMOV,
|
||||
FeatureFXSR, FeatureNOPL],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
|
||||
foreach P = ["pentium3", "pentium3m"] in {
|
||||
def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX,
|
||||
FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
}
|
||||
|
||||
// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
|
||||
|
|
@ -1221,30 +1221,30 @@ foreach P = ["pentium3", "pentium3m"] in {
|
|||
def : ProcModel<"pentium-m", GenericPostRAModel,
|
||||
[FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2,
|
||||
FeatureFXSR, FeatureNOPL, FeatureCMOV],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
|
||||
foreach P = ["pentium4", "pentium4m"] in {
|
||||
def : ProcModel<P, GenericPostRAModel,
|
||||
[FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2,
|
||||
FeatureFXSR, FeatureNOPL, FeatureCMOV],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
}
|
||||
|
||||
// Intel Quark.
|
||||
def : Proc<"lakemont", [FeatureCMPXCHG8B],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
|
||||
// Intel Core Duo.
|
||||
def : ProcModel<"yonah", SandyBridgeModel,
|
||||
[FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3,
|
||||
FeatureFXSR, FeatureNOPL, FeatureCMOV],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
|
||||
// NetBurst.
|
||||
def : ProcModel<"prescott", GenericPostRAModel,
|
||||
[FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3,
|
||||
FeatureFXSR, FeatureNOPL, FeatureCMOV],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
def : ProcModel<"nocona", GenericPostRAModel, [
|
||||
FeatureX87,
|
||||
FeatureCMPXCHG8B,
|
||||
|
|
@ -1257,8 +1257,8 @@ def : ProcModel<"nocona", GenericPostRAModel, [
|
|||
FeatureCMPXCHG16B,
|
||||
],
|
||||
[
|
||||
FeatureSlowUAMem16,
|
||||
FeatureInsertVZEROUPPER
|
||||
TuningSlowUAMem16,
|
||||
TuningInsertVZEROUPPER
|
||||
]>;
|
||||
|
||||
// Intel Core 2 Solo/Duo.
|
||||
|
|
@ -1275,9 +1275,9 @@ def : ProcModel<"core2", SandyBridgeModel, [
|
|||
FeatureLAHFSAHF
|
||||
],
|
||||
[
|
||||
FeatureMacroFusion,
|
||||
FeatureSlowUAMem16,
|
||||
FeatureInsertVZEROUPPER
|
||||
TuningMacroFusion,
|
||||
TuningSlowUAMem16,
|
||||
TuningInsertVZEROUPPER
|
||||
]>;
|
||||
def : ProcModel<"penryn", SandyBridgeModel, [
|
||||
FeatureX87,
|
||||
|
|
@ -1292,9 +1292,9 @@ def : ProcModel<"penryn", SandyBridgeModel, [
|
|||
FeatureLAHFSAHF
|
||||
],
|
||||
[
|
||||
FeatureMacroFusion,
|
||||
FeatureSlowUAMem16,
|
||||
FeatureInsertVZEROUPPER
|
||||
TuningMacroFusion,
|
||||
TuningSlowUAMem16,
|
||||
TuningInsertVZEROUPPER
|
||||
]>;
|
||||
|
||||
// Atom CPUs.
|
||||
|
|
@ -1379,37 +1379,37 @@ def : ProcModel<"alderlake", SkylakeClientModel,
|
|||
// AMD CPUs.
|
||||
|
||||
def : Proc<"k6", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
def : Proc<"k6-2", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
def : Proc<"k6-3", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
|
||||
foreach P = ["athlon", "athlon-tbird"] in {
|
||||
def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, Feature3DNowA,
|
||||
FeatureNOPL],
|
||||
[FeatureSlowSHLD, FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
}
|
||||
|
||||
foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
|
||||
def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV,
|
||||
FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL],
|
||||
[FeatureSlowSHLD, FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
}
|
||||
|
||||
foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
|
||||
def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE2, Feature3DNowA,
|
||||
FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMOV],
|
||||
[FeatureFastScalarShiftMasks, FeatureSlowSHLD, FeatureSlowUAMem16,
|
||||
FeatureInsertVZEROUPPER]>;
|
||||
[TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
|
||||
TuningInsertVZEROUPPER]>;
|
||||
}
|
||||
|
||||
foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
|
||||
def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE3, Feature3DNowA,
|
||||
FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureCMOV,
|
||||
Feature64Bit],
|
||||
[FeatureFastScalarShiftMasks, FeatureSlowSHLD, FeatureSlowUAMem16,
|
||||
FeatureInsertVZEROUPPER]>;
|
||||
[TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
|
||||
TuningInsertVZEROUPPER]>;
|
||||
}
|
||||
|
||||
foreach P = ["amdfam10", "barcelona"] in {
|
||||
|
|
@ -1445,17 +1445,17 @@ def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features,
|
|||
ProcessorFeatures.ZN3Tuning>;
|
||||
|
||||
def : Proc<"geode", [FeatureX87, FeatureCMPXCHG8B, Feature3DNowA],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
|
||||
def : Proc<"winchip-c6", [FeatureX87, FeatureMMX],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
def : Proc<"winchip2", [FeatureX87, Feature3DNow],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
def : Proc<"c3", [FeatureX87, Feature3DNow],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
def : Proc<"c3-2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX,
|
||||
FeatureSSE1, FeatureFXSR, FeatureCMOV],
|
||||
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
|
||||
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
|
||||
|
||||
// We also provide a generic 64-bit specific x86 processor model which tries to
|
||||
// be good for modern chips without enabling instruction set encodings past the
|
||||
|
|
@ -1469,11 +1469,11 @@ def : Proc<"c3-2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX,
|
|||
// forming a common base for them.
|
||||
def : ProcModel<"x86-64", SandyBridgeModel, ProcessorFeatures.X86_64V1Features,
|
||||
[
|
||||
FeatureSlow3OpsLEA,
|
||||
FeatureSlowDivide64,
|
||||
FeatureSlowIncDec,
|
||||
FeatureMacroFusion,
|
||||
FeatureInsertVZEROUPPER
|
||||
TuningSlow3OpsLEA,
|
||||
TuningSlowDivide64,
|
||||
TuningSlowIncDec,
|
||||
TuningMacroFusion,
|
||||
TuningInsertVZEROUPPER
|
||||
]>;
|
||||
|
||||
// x86-64 micro-architecture levels.
|
||||
|
|
|
|||
|
|
@ -1094,11 +1094,11 @@ static unsigned emitNop(MCStreamer &OS, unsigned NumBytes,
|
|||
if (Subtarget->is64Bit()) {
|
||||
// FIXME: We can use NOOPL on 32-bit targets with FeatureNOPL, but the
|
||||
// IndexReg/BaseReg below need to be updated.
|
||||
if (Subtarget->hasFeature(X86::FeatureFast7ByteNOP))
|
||||
if (Subtarget->hasFeature(X86::TuningFast7ByteNOP))
|
||||
MaxNopLength = 7;
|
||||
else if (Subtarget->hasFeature(X86::FeatureFast15ByteNOP))
|
||||
else if (Subtarget->hasFeature(X86::TuningFast15ByteNOP))
|
||||
MaxNopLength = 15;
|
||||
else if (Subtarget->hasFeature(X86::FeatureFast11ByteNOP))
|
||||
else if (Subtarget->hasFeature(X86::TuningFast11ByteNOP))
|
||||
MaxNopLength = 11;
|
||||
else
|
||||
MaxNopLength = 10;
|
||||
|
|
|
|||
|
|
@ -45,48 +45,50 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
|
|||
X86::FeatureCMPXCHG16B,
|
||||
X86::FeatureLAHFSAHF,
|
||||
|
||||
// Codegen control options.
|
||||
X86::FeatureFast11ByteNOP,
|
||||
X86::FeatureFast15ByteNOP,
|
||||
X86::FeatureFastBEXTR,
|
||||
X86::FeatureFastHorizontalOps,
|
||||
X86::FeatureFastLZCNT,
|
||||
X86::FeatureFastScalarFSQRT,
|
||||
X86::FeatureFastSHLDRotate,
|
||||
X86::FeatureFastScalarShiftMasks,
|
||||
X86::FeatureFastVectorShiftMasks,
|
||||
X86::FeatureFastVariableCrossLaneShuffle,
|
||||
X86::FeatureFastVariablePerLaneShuffle,
|
||||
X86::FeatureFastVectorFSQRT,
|
||||
X86::FeatureLEAForSP,
|
||||
X86::FeatureLEAUsesAG,
|
||||
X86::FeatureLZCNTFalseDeps,
|
||||
X86::FeatureBranchFusion,
|
||||
X86::FeatureMacroFusion,
|
||||
X86::FeaturePadShortFunctions,
|
||||
X86::FeaturePOPCNTFalseDeps,
|
||||
// Some older targets can be setup to fold unaligned loads.
|
||||
X86::FeatureSSEUnalignedMem,
|
||||
X86::FeatureSlow3OpsLEA,
|
||||
X86::FeatureSlowDivide32,
|
||||
X86::FeatureSlowDivide64,
|
||||
X86::FeatureSlowIncDec,
|
||||
X86::FeatureSlowLEA,
|
||||
X86::FeatureSlowPMADDWD,
|
||||
X86::FeatureSlowPMULLD,
|
||||
X86::FeatureSlowSHLD,
|
||||
X86::FeatureSlowTwoMemOps,
|
||||
X86::FeatureSlowUAMem16,
|
||||
X86::FeaturePreferMaskRegisters,
|
||||
X86::FeatureInsertVZEROUPPER,
|
||||
X86::FeatureUseGLMDivSqrtCosts,
|
||||
|
||||
// Codegen control options.
|
||||
X86::TuningFast11ByteNOP,
|
||||
X86::TuningFast15ByteNOP,
|
||||
X86::TuningFastBEXTR,
|
||||
X86::TuningFastHorizontalOps,
|
||||
X86::TuningFastLZCNT,
|
||||
X86::TuningFastScalarFSQRT,
|
||||
X86::TuningFastSHLDRotate,
|
||||
X86::TuningFastScalarShiftMasks,
|
||||
X86::TuningFastVectorShiftMasks,
|
||||
X86::TuningFastVariableCrossLaneShuffle,
|
||||
X86::TuningFastVariablePerLaneShuffle,
|
||||
X86::TuningFastVectorFSQRT,
|
||||
X86::TuningLEAForSP,
|
||||
X86::TuningLEAUsesAG,
|
||||
X86::TuningLZCNTFalseDeps,
|
||||
X86::TuningBranchFusion,
|
||||
X86::TuningMacroFusion,
|
||||
X86::TuningPadShortFunctions,
|
||||
X86::TuningPOPCNTFalseDeps,
|
||||
X86::TuningSlow3OpsLEA,
|
||||
X86::TuningSlowDivide32,
|
||||
X86::TuningSlowDivide64,
|
||||
X86::TuningSlowIncDec,
|
||||
X86::TuningSlowLEA,
|
||||
X86::TuningSlowPMADDWD,
|
||||
X86::TuningSlowPMULLD,
|
||||
X86::TuningSlowSHLD,
|
||||
X86::TuningSlowTwoMemOps,
|
||||
X86::TuningSlowUAMem16,
|
||||
X86::TuningPreferMaskRegisters,
|
||||
X86::TuningInsertVZEROUPPER,
|
||||
X86::TuningUseGLMDivSqrtCosts,
|
||||
|
||||
// Perf-tuning flags.
|
||||
X86::FeatureFastGather,
|
||||
X86::FeatureSlowUAMem32,
|
||||
X86::TuningFastGather,
|
||||
X86::TuningSlowUAMem32,
|
||||
|
||||
// Based on whether user set the -mprefer-vector-width command line.
|
||||
X86::FeaturePrefer128Bit,
|
||||
X86::FeaturePrefer256Bit,
|
||||
X86::TuningPrefer128Bit,
|
||||
X86::TuningPrefer256Bit,
|
||||
|
||||
// CPU name enums. These just follow CPU string.
|
||||
X86::ProcIntelAtom,
|
||||
|
|
|
|||
Loading…
Reference in New Issue