diff --git a/llvm/include/llvm/CodeGen/Register.h b/llvm/include/llvm/CodeGen/Register.h index b83a6264c80a..cc93bc2978b9 100644 --- a/llvm/include/llvm/CodeGen/Register.h +++ b/llvm/include/llvm/CodeGen/Register.h @@ -21,6 +21,7 @@ class Register { public: Register(unsigned Val = 0): Reg(Val) {} + Register(MCRegister Val): Reg(Val) {} // Register numbers can represent physical registers, virtual registers, and // sometimes stack slots. The unsigned values are divided into these ranges: @@ -114,6 +115,22 @@ public: } }; +// Provide DenseMapInfo for Register +template<> struct DenseMapInfo { + static inline unsigned getEmptyKey() { + return DenseMapInfo::getEmptyKey(); + } + static inline unsigned getTombstoneKey() { + return DenseMapInfo::getTombstoneKey(); + } + static unsigned getHashValue(const unsigned &Val) { + return DenseMapInfo::getHashValue(Val); + } + static bool isEqual(const unsigned &LHS, const unsigned &RHS) { + return DenseMapInfo::isEqual(LHS, RHS); + } +}; + } #endif // ifndef LLVM_CODEGEN_REGISTER_H diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h index deb40291a8f8..11596cb7ee7c 100644 --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -976,6 +976,13 @@ public: const MachineRegisterInfo &MRI) const { return nullptr; } + + /// Returns the physical register number of sub-register "Index" + /// for physical register RegNo. Return zero if the sub-register does not + /// exist. + inline Register getSubReg(MCRegister Reg, unsigned Idx) const { + return static_cast(this)->getSubReg(Reg, Idx); + } }; //===----------------------------------------------------------------------===// diff --git a/llvm/include/llvm/MC/MCRegister.h b/llvm/include/llvm/MC/MCRegister.h index bcb9f387111e..99033aaaf8e0 100644 --- a/llvm/include/llvm/MC/MCRegister.h +++ b/llvm/include/llvm/MC/MCRegister.h @@ -9,6 +9,7 @@ #ifndef LLVM_MC_REGISTER_H #define LLVM_MC_REGISTER_H +#include "llvm/ADT/DenseMapInfo.h" #include namespace llvm { @@ -64,6 +65,22 @@ public: } }; +// Provide DenseMapInfo for MCRegister +template<> struct DenseMapInfo { + static inline unsigned getEmptyKey() { + return DenseMapInfo::getEmptyKey(); + } + static inline unsigned getTombstoneKey() { + return DenseMapInfo::getTombstoneKey(); + } + static unsigned getHashValue(const unsigned &Val) { + return DenseMapInfo::getHashValue(Val); + } + static bool isEqual(const unsigned &LHS, const unsigned &RHS) { + return DenseMapInfo::isEqual(LHS, RHS); + } +}; + } #endif // ifndef LLVM_MC_REGISTER_H diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h index 4db7619df61a..8671a861d2ac 100644 --- a/llvm/include/llvm/MC/MCRegisterInfo.h +++ b/llvm/include/llvm/MC/MCRegisterInfo.h @@ -150,8 +150,8 @@ public: private: const MCRegisterDesc *Desc; // Pointer to the descriptor array unsigned NumRegs; // Number of entries in the array - unsigned RAReg; // Return address register - unsigned PCReg; // Program counter register + MCRegister RAReg; // Return address register + MCRegister PCReg; // Program counter register const MCRegisterClass *Classes; // Pointer to the regclass array unsigned NumClasses; // Number of entries in the array unsigned NumRegUnits; // Number of regunits. @@ -177,8 +177,8 @@ private: const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH - DenseMap L2SEHRegs; // LLVM to SEH regs mapping - DenseMap L2CVRegs; // LLVM to CV regs mapping + DenseMap L2SEHRegs; // LLVM to SEH regs mapping + DenseMap L2CVRegs; // LLVM to CV regs mapping public: /// DiffListIterator - Base iterator class that can traverse the @@ -204,7 +204,7 @@ public: /// advance - Move to the next list position, return the applied /// differential. This function does not detect the end of the list, that /// is the caller's responsibility (by checking for a 0 return value). - unsigned advance() { + MCRegister advance() { assert(isValid() && "Cannot move off the end of the list."); MCPhysReg D = *List++; Val += D; @@ -216,7 +216,7 @@ public: bool isValid() const { return List; } /// Dereference the iterator to get the value at the current position. - unsigned operator*() const { return Val; } + MCRegister operator*() const { return Val; } /// Pre-increment to move to the next position. void operator++() { @@ -311,26 +311,26 @@ public: /// as the LLVM register number. /// FIXME: TableGen these numbers. Currently this requires target specific /// initialization code. - void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { + void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg) { L2SEHRegs[LLVMReg] = SEHReg; } - void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) { + void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg) { L2CVRegs[LLVMReg] = CVReg; } /// This method should return the register where the return /// address can be found. - unsigned getRARegister() const { + MCRegister getRARegister() const { return RAReg; } /// Return the register which is the program counter. - unsigned getProgramCounter() const { + MCRegister getProgramCounter() const { return PCReg; } - const MCRegisterDesc &operator[](unsigned RegNo) const { + const MCRegisterDesc &operator[](MCRegister RegNo) const { assert(RegNo < NumRegs && "Attempting to access record for invalid register number!"); return Desc[RegNo]; @@ -338,24 +338,24 @@ public: /// Provide a get method, equivalent to [], but more useful with a /// pointer to this object. - const MCRegisterDesc &get(unsigned RegNo) const { + const MCRegisterDesc &get(MCRegister RegNo) const { return operator[](RegNo); } /// Returns the physical register number of sub-register "Index" /// for physical register RegNo. Return zero if the sub-register does not /// exist. - unsigned getSubReg(unsigned Reg, unsigned Idx) const; + MCRegister getSubReg(MCRegister Reg, unsigned Idx) const; /// Return a super-register of the specified register /// Reg so its sub-register of index SubIdx is Reg. - unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, - const MCRegisterClass *RC) const; + MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, + const MCRegisterClass *RC) const; /// For a given register pair, return the sub-register index /// if the second register is a sub-register of the first. Return zero /// otherwise. - unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const; + unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const; /// Get the size of the bit range covered by a sub-register index. /// If the index isn't continuous, return the sum of the sizes of its parts. @@ -369,7 +369,7 @@ public: /// Return the human-readable symbolic target-specific name for the /// specified physical register. - const char *getName(unsigned RegNo) const { + const char *getName(MCRegister RegNo) const { return RegStrings + get(RegNo).Name; } @@ -397,7 +397,7 @@ public: /// number. Returns -1 if there is no equivalent value. The second /// parameter allows targets to use different numberings for EH info and /// debugging info. - int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getDwarfRegNum(MCRegister RegNum, bool isEH) const; /// Map a dwarf register back to a target register. int getLLVMRegNum(unsigned RegNum, bool isEH) const; @@ -413,11 +413,11 @@ public: /// Map a target register to an equivalent SEH register /// number. Returns LLVM register number if there is no equivalent value. - int getSEHRegNum(unsigned RegNum) const; + int getSEHRegNum(MCRegister RegNum) const; /// Map a target register to an equivalent CodeView register /// number. - int getCodeViewRegNum(unsigned RegNum) const; + int getCodeViewRegNum(MCRegister RegNum) const; regclass_iterator regclass_begin() const { return Classes; } regclass_iterator regclass_end() const { return Classes+NumClasses; } @@ -441,34 +441,34 @@ public: } /// Returns the encoding for RegNo - uint16_t getEncodingValue(unsigned RegNo) const { + uint16_t getEncodingValue(MCRegister RegNo) const { assert(RegNo < NumRegs && "Attempting to get encoding for invalid register number!"); return RegEncodingTable[RegNo]; } /// Returns true if RegB is a sub-register of RegA. - bool isSubRegister(unsigned RegA, unsigned RegB) const { + bool isSubRegister(MCRegister RegA, MCRegister RegB) const { return isSuperRegister(RegB, RegA); } /// Returns true if RegB is a super-register of RegA. - bool isSuperRegister(unsigned RegA, unsigned RegB) const; + bool isSuperRegister(MCRegister RegA, MCRegister RegB) const; /// Returns true if RegB is a sub-register of RegA or if RegB == RegA. - bool isSubRegisterEq(unsigned RegA, unsigned RegB) const { + bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { return isSuperRegisterEq(RegB, RegA); } /// Returns true if RegB is a super-register of RegA or if /// RegB == RegA. - bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const { + bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { return RegA == RegB || isSuperRegister(RegA, RegB); } /// Returns true if RegB is a super-register or sub-register of RegA /// or if RegB == RegA. - bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const { + bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); } }; @@ -484,8 +484,8 @@ public: /// If IncludeSelf is set, Reg itself is included in the list. class MCSubRegIterator : public MCRegisterInfo::DiffListIterator { public: - MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI, - bool IncludeSelf = false) { + MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, + bool IncludeSelf = false) { init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs); // Initially, the iterator points to Reg itself. if (!IncludeSelf) @@ -502,13 +502,13 @@ class MCSubRegIndexIterator { public: /// Constructs an iterator that traverses subregisters and their /// associated subregister indices. - MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI) + MCSubRegIndexIterator(MCRegister Reg, const MCRegisterInfo *MCRI) : SRIter(Reg, MCRI) { SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices; } /// Returns current sub-register. - unsigned getSubReg() const { + MCRegister getSubReg() const { return *SRIter; } @@ -533,7 +533,7 @@ class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator { public: MCSuperRegIterator() = default; - MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI, + MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf = false) { init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs); // Initially, the iterator points to Reg itself. @@ -544,7 +544,7 @@ public: // Definition for isSuperRegister. Put it down here since it needs the // iterator defined above in addition to the MCRegisterInfo class itself. -inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{ +inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{ for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I) if (*I == RegB) return true; @@ -571,7 +571,7 @@ public: /// in Reg. MCRegUnitIterator() = default; - MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) { + MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI) { assert(Reg && "Null register has no regunits"); // Decode the RegUnits MCRegisterDesc field. unsigned RU = MCRI->get(Reg).RegUnits; @@ -602,7 +602,7 @@ public: /// Constructs an iterator that traverses the register units and their /// associated LaneMasks in Reg. - MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI) + MCRegUnitMaskIterator(MCRegister Reg, const MCRegisterInfo *MCRI) : RUIter(Reg, MCRI) { uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks; MaskListIter = &MCRI->RegUnitMaskSequences[Idx]; @@ -669,7 +669,7 @@ public: /// any ordering or that entries are unique. class MCRegAliasIterator { private: - unsigned Reg; + MCRegister Reg; const MCRegisterInfo *MCRI; bool IncludeSelf; @@ -678,7 +678,7 @@ private: MCSuperRegIterator SI; public: - MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, + MCRegAliasIterator(MCRegister Reg, const MCRegisterInfo *MCRI, bool IncludeSelf) : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) { // Initialize the iterators. @@ -694,7 +694,7 @@ public: bool isValid() const { return RI.isValid(); } - unsigned operator*() const { + MCRegister operator*() const { assert(SI.isValid() && "Cannot dereference an invalid iterator."); return *SI; } diff --git a/llvm/lib/CodeGen/CalcSpillWeights.cpp b/llvm/lib/CodeGen/CalcSpillWeights.cpp index dd454a06077d..6d0a02f99db5 100644 --- a/llvm/lib/CodeGen/CalcSpillWeights.cpp +++ b/llvm/lib/CodeGen/CalcSpillWeights.cpp @@ -48,10 +48,11 @@ void llvm::calculateSpillWeightsAndHints(LiveIntervals &LIS, } // Return the preferred allocation register for reg, given a COPY instruction. -static unsigned copyHint(const MachineInstr *mi, unsigned reg, +static Register copyHint(const MachineInstr *mi, unsigned reg, const TargetRegisterInfo &tri, const MachineRegisterInfo &mri) { - unsigned sub, hreg, hsub; + unsigned sub, hsub; + Register hreg; if (mi->getOperand(0).getReg() == reg) { sub = mi->getOperand(0).getSubReg(); hreg = mi->getOperand(1).getReg(); @@ -66,10 +67,10 @@ static unsigned copyHint(const MachineInstr *mi, unsigned reg, return 0; if (Register::isVirtualRegister(hreg)) - return sub == hsub ? hreg : 0; + return sub == hsub ? hreg : Register(); const TargetRegisterClass *rc = mri.getRegClass(reg); - unsigned CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg); + Register CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg); if (rc->contains(CopiedPReg)) return CopiedPReg; diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp index 79789522cca2..fbf81c258818 100644 --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -862,7 +862,7 @@ bool RegAllocFast::setPhysReg(MachineInstr &MI, MachineOperand &MO, } // Handle subregister index. - MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); + MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : Register()); MO.setIsRenamable(true); MO.setSubReg(0); diff --git a/llvm/lib/MC/MCRegisterInfo.cpp b/llvm/lib/MC/MCRegisterInfo.cpp index 4273b876b7bb..7c7376d906f7 100644 --- a/llvm/lib/MC/MCRegisterInfo.cpp +++ b/llvm/lib/MC/MCRegisterInfo.cpp @@ -20,15 +20,16 @@ using namespace llvm; -unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, - const MCRegisterClass *RC) const { +MCRegister +MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, + const MCRegisterClass *RC) const { for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers) if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) return *Supers; return 0; } -unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { +MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const { assert(Idx && Idx < getNumSubRegIndices() && "This is not a subregister index"); // Get a pointer to the corresponding SubRegIndices list. This list has the @@ -40,7 +41,8 @@ unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { return 0; } -unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { +unsigned MCRegisterInfo::getSubRegIndex(MCRegister Reg, + MCRegister SubReg) const { assert(SubReg && SubReg < getNumRegs() && "This is not a register"); // Get a pointer to the corresponding SubRegIndices list. This list has the // name of each sub-register in the same order as MCSubRegIterator. @@ -63,7 +65,7 @@ unsigned MCRegisterInfo::getSubRegIdxOffset(unsigned Idx) const { return SubRegIdxRanges[Idx].Offset; } -int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { +int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const { const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs; unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize; @@ -116,16 +118,16 @@ int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const { return RegNum; } -int MCRegisterInfo::getSEHRegNum(unsigned RegNum) const { - const DenseMap::const_iterator I = L2SEHRegs.find(RegNum); +int MCRegisterInfo::getSEHRegNum(MCRegister RegNum) const { + const DenseMap::const_iterator I = L2SEHRegs.find(RegNum); if (I == L2SEHRegs.end()) return (int)RegNum; return I->second; } -int MCRegisterInfo::getCodeViewRegNum(unsigned RegNum) const { +int MCRegisterInfo::getCodeViewRegNum(MCRegister RegNum) const { if (L2CVRegs.empty()) report_fatal_error("target does not implement codeview register mapping"); - const DenseMap::const_iterator I = L2CVRegs.find(RegNum); + const DenseMap::const_iterator I = L2CVRegs.find(RegNum); if (I == L2CVRegs.end()) report_fatal_error("unknown codeview register " + (RegNum < getNumRegs() ? getName(RegNum) diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 3c5d8fc576a5..c16bdad04e3c 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -716,7 +716,7 @@ void SIRegisterInfo::buildSpillLoadStore(MachineBasicBlock::iterator MI, for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += EltSize) { unsigned SubReg = NumSubRegs == 1 ? - ValueReg : getSubReg(ValueReg, getSubRegFromChannel(i)); + Register(ValueReg) : getSubReg(ValueReg, getSubRegFromChannel(i)); unsigned SOffsetRegState = 0; unsigned SrcDstRegState = getDefRegState(!IsStore); @@ -806,7 +806,7 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, const GCNSubtarget &ST = MF->getSubtarget(); const SIInstrInfo *TII = ST.getInstrInfo(); - unsigned SuperReg = MI->getOperand(0).getReg(); + Register SuperReg = MI->getOperand(0).getReg(); bool IsKill = MI->getOperand(0).isKill(); const DebugLoc &DL = MI->getDebugLoc(); @@ -988,7 +988,7 @@ bool SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI, const SIInstrInfo *TII = ST.getInstrInfo(); const DebugLoc &DL = MI->getDebugLoc(); - unsigned SuperReg = MI->getOperand(0).getReg(); + Register SuperReg = MI->getOperand(0).getReg(); bool SpillToSMEM = spillSGPRToSMEM(); if (SpillToSMEM && OnlyToVGPR) return false; diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp index a2dcad1932c7..efd5ed915127 100644 --- a/llvm/lib/Target/Hexagon/BitTracker.cpp +++ b/llvm/lib/Target/Hexagon/BitTracker.cpp @@ -340,7 +340,8 @@ uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { return TRI.getRegSizeInBits(VC); } assert(Register::isPhysicalRegister(RR.Reg)); - unsigned PhysR = (RR.Sub == 0) ? RR.Reg : TRI.getSubReg(RR.Reg, RR.Sub); + Register PhysR = + (RR.Sub == 0) ? Register(RR.Reg) : TRI.getSubReg(RR.Reg, RR.Sub); return getPhysRegBitWidth(PhysR); } diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp index 52e97edac1a1..6175b29135b7 100644 --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -579,7 +579,7 @@ unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO, using namespace Hexagon; if (SO.isReg()) { - unsigned PhysR; + Register PhysR; RegisterRef RS = SO; if (Register::isVirtualRegister(RS.Reg)) { const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);