forked from OSchip/llvm-project
Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h with
HexagonInstrFormats.td. llvm-svn: 175537
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@ -17,6 +17,9 @@
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#ifndef HEXAGONBASEINFO_H
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#define HEXAGONBASEINFO_H
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#include "HexagonMCTargetDesc.h"
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#include "llvm/Support/ErrorHandling.h"
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namespace llvm {
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/// HexagonII - This namespace holds all of the target specific flags that
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@ -40,7 +43,7 @@ namespace HexagonII {
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TypeMEMOP = 9,
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TypeNV = 10,
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TypePREFIX = 30, // Such as extenders.
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TypeMARKER = 31 // Such as end of a HW loop.
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TypeENDLOOP = 31 // Such as end of a HW loop.
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};
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enum SubTarget {
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@ -65,6 +68,14 @@ namespace HexagonII {
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BaseRegOffset = 5 // Indirect with register offset
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};
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enum MemAccessSize {
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NoMemAccess = 0, // Not a memory acces instruction.
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ByteAccess = 1, // Byte access instruction (memb).
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HalfWordAccess = 2, // Half word access instruction (memh).
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WordAccess = 3, // Word access instrution (memw).
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DoubleWordAccess = 4 // Double word access instruction (memd)
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};
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// MCInstrDesc TSFlags
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// *** Must match HexagonInstrFormat*.td ***
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enum {
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@ -79,45 +90,66 @@ namespace HexagonII {
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// Predicated instructions.
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PredicatedPos = 6,
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PredicatedMask = 0x1,
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PredicatedNewPos = 7,
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PredicatedFalsePos = 7,
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PredicatedFalseMask = 0x1,
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PredicatedNewPos = 8,
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PredicatedNewMask = 0x1,
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// Stores that can be newified.
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mayNVStorePos = 8,
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// New-Value consumer instructions.
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NewValuePos = 9,
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NewValueMask = 0x1,
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// New-Value producer instructions.
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hasNewValuePos = 10,
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hasNewValueMask = 0x1,
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// Which operand consumes or produces a new value.
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NewValueOpPos = 11,
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NewValueOpMask = 0x7,
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// Which bits encode the new value.
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NewValueBitsPos = 14,
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NewValueBitsMask = 0x3,
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// Stores that can become new-value stores.
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mayNVStorePos = 16,
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mayNVStoreMask = 0x1,
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// Dot new value store instructions.
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NVStorePos = 9,
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// New-value store instructions.
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NVStorePos = 17,
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NVStoreMask = 0x1,
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// Extendable insns.
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ExtendablePos = 10,
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ExtendablePos = 18,
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ExtendableMask = 0x1,
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// Insns must be extended.
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ExtendedPos = 11,
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ExtendedPos = 19,
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ExtendedMask = 0x1,
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// Which operand may be extended.
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ExtendableOpPos = 12,
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ExtendableOpPos = 20,
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ExtendableOpMask = 0x7,
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// Signed or unsigned range.
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ExtentSignedPos = 15,
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ExtentSignedPos = 23,
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ExtentSignedMask = 0x1,
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// Number of bits of range before extending operand.
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ExtentBitsPos = 16,
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ExtentBitsPos = 24,
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ExtentBitsMask = 0x1f,
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// Valid subtargets
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validSubTargetPos = 21,
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validSubTargetPos = 29,
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validSubTargetMask = 0xf,
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// Addressing mode for load/store instructions
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AddrModePos = 25,
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AddrModeMask = 0xf
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// Addressing mode for load/store instructions.
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AddrModePos = 33,
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AddrModeMask = 0x7,
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// Access size of memory access instructions (load/store).
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MemAccessSizePos = 36,
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MemAccesSizeMask = 0x7
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};
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// *** The code above must match HexagonInstrFormat*.td *** //
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