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[C++] Use 'nullptr'. 

llvm-svn: 207394
This commit is contained in:
Craig Topper 2014-04-28 04:05:08 +00:00
parent 09ced5f66b
commit e73658ddbb
124 changed files with 350 additions and 341 deletions
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8
llvm/include/llvm/ADT/EquivalenceClasses.h
View File

@ -86,14 +86,14 @@ class EquivalenceClasses {
}
void setNext(const ECValue *NewNext) const {
assert(getNext() == 0 && "Already has a next pointer!");
assert(getNext() == nullptr && "Already has a next pointer!");
Next = (const ECValue*)((intptr_t)NewNext | (intptr_t)isLeader());
}
public:
ECValue(const ECValue &RHS) : Leader(this), Next((ECValue*)(intptr_t)1),
Data(RHS.Data) {
// Only support copying of singleton nodes.
assert(RHS.isLeader() && RHS.getNext() == 0 && "Not a singleton!");
assert(RHS.isLeader() && RHS.getNext() == nullptr && "Not a singleton!");
}
bool operator<(const ECValue &UFN) const { return Data < UFN.Data; }
@ -251,13 +251,13 @@ public:
explicit member_iterator(const ECValue *N) : Node(N) {}
reference operator*() const {
assert(Node != 0 && "Dereferencing end()!");
assert(Node != nullptr && "Dereferencing end()!");
return Node->getData();
}
reference operator->() const { return operator*(); }
member_iterator &operator++() {
assert(Node != 0 && "++'d off the end of the list!");
assert(Node != nullptr && "++'d off the end of the list!");
Node = Node->getNext();
return *this;
}

2
llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
View File

@ -1395,7 +1395,7 @@ public:
void doFunction(const FunctionT *F, const BranchProbabilityInfoT *BPI,
const LoopInfoT *LI);
BlockFrequencyInfoImpl() : BPI(0), LI(0), F(0) {}
BlockFrequencyInfoImpl() : BPI(nullptr), LI(nullptr), F(nullptr) {}
using BlockFrequencyInfoImplBase::getEntryFreq;
BlockFrequency getBlockFreq(const BlockT *BB) const {

2
llvm/lib/Analysis/IPA/CallGraph.cpp
View File

@ -280,7 +280,7 @@ void CallGraphWrapperPass::print(raw_ostream &OS, const Module *) const {
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
void CallGraphWrapperPass::dump() const { print(dbgs(), 0); }
void CallGraphWrapperPass::dump() const { print(dbgs(), nullptr); }
#endif
// Enuse that users of CallGraph.h also link with this file

20
llvm/lib/Bitcode/Reader/BitcodeReader.h
View File

@ -224,13 +224,13 @@ public:
}
explicit BitcodeReader(MemoryBuffer *buffer, LLVMContext &C)
: Context(C), TheModule(0), Buffer(buffer), BufferOwned(false),
LazyStreamer(0), NextUnreadBit(0), SeenValueSymbolTable(false),
: Context(C), TheModule(nullptr), Buffer(buffer), BufferOwned(false),
LazyStreamer(nullptr), NextUnreadBit(0), SeenValueSymbolTable(false),
ValueList(C), MDValueList(C),
SeenFirstFunctionBody(false), UseRelativeIDs(false) {
}
explicit BitcodeReader(DataStreamer *streamer, LLVMContext &C)
: Context(C), TheModule(0), Buffer(0), BufferOwned(false),
: Context(C), TheModule(nullptr), Buffer(nullptr), BufferOwned(false),
LazyStreamer(streamer), NextUnreadBit(0), SeenValueSymbolTable(false),
ValueList(C), MDValueList(C),
SeenFirstFunctionBody(false), UseRelativeIDs(false) {
@ -271,7 +271,7 @@ private:
return ValueList.getValueFwdRef(ID, Ty);
}
BasicBlock *getBasicBlock(unsigned ID) const {
if (ID >= FunctionBBs.size()) return 0; // Invalid ID
if (ID >= FunctionBBs.size()) return nullptr; // Invalid ID
return FunctionBBs[ID];
}
AttributeSet getAttributes(unsigned i) const {
@ -293,15 +293,15 @@ private:
if (ValNo < InstNum) {
// If this is not a forward reference, just return the value we already
// have.
ResVal = getFnValueByID(ValNo, 0);
return ResVal == 0;
ResVal = getFnValueByID(ValNo, nullptr);
return ResVal == nullptr;
} else if (Slot == Record.size()) {
return true;
}
unsigned TypeNo = (unsigned)Record[Slot++];
ResVal = getFnValueByID(ValNo, getTypeByID(TypeNo));
return ResVal == 0;
return ResVal == nullptr;
}
/// popValue - Read a value out of the specified record from slot 'Slot'.
@ -320,14 +320,14 @@ private:
bool getValue(SmallVectorImpl<uint64_t> &Record, unsigned Slot,
unsigned InstNum, Type *Ty, Value *&ResVal) {
ResVal = getValue(Record, Slot, InstNum, Ty);
return ResVal == 0;
return ResVal == nullptr;
}
/// getValue -- Version of getValue that returns ResVal directly,
/// or 0 if there is an error.
Value *getValue(SmallVectorImpl<uint64_t> &Record, unsigned Slot,
unsigned InstNum, Type *Ty) {
if (Slot == Record.size()) return 0;
if (Slot == Record.size()) return nullptr;
unsigned ValNo = (unsigned)Record[Slot];
// Adjust the ValNo, if it was encoded relative to the InstNum.
if (UseRelativeIDs)
@ -338,7 +338,7 @@ private:
/// getValueSigned -- Like getValue, but decodes signed VBRs.
Value *getValueSigned(SmallVectorImpl<uint64_t> &Record, unsigned Slot,
unsigned InstNum, Type *Ty) {
if (Slot == Record.size()) return 0;
if (Slot == Record.size()) return nullptr;
unsigned ValNo = (unsigned)decodeSignRotatedValue(Record[Slot]);
// Adjust the ValNo, if it was encoded relative to the InstNum.
if (UseRelativeIDs)

2
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
View File

@ -110,7 +110,7 @@ AsmPrinter::AsmPrinter(TargetMachine &tm, MCStreamer &Streamer)
}
AsmPrinter::~AsmPrinter() {
assert(DD == 0 && Handlers.empty() && "Debug/EH info didn't get finalized");
assert(!DD && Handlers.empty() && "Debug/EH info didn't get finalized");
if (GCMetadataPrinters) {
gcp_map_type &GCMap = getGCMap(GCMetadataPrinters);

2
llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h
View File

@ -94,7 +94,7 @@ private:
const DwarfCompileUnit *Unit;
public:
DebugLocEntry() : Begin(0), End(0), Unit(0) {}
DebugLocEntry() : Begin(nullptr), End(nullptr), Unit(nullptr) {}
DebugLocEntry(const MCSymbol *B, const MCSymbol *E,
Value Val, const DwarfCompileUnit *U)
: Begin(B), End(E), Unit(U) {

10
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
View File

@ -994,8 +994,8 @@ void DwarfDebug::endSections() {
// Emit all Dwarf sections that should come after the content.
void DwarfDebug::endModule() {
assert(CurFn == 0);
assert(CurMI == 0);
assert(CurFn == nullptr);
assert(CurMI == nullptr);
if (!FirstCU)
return;
@ -1279,7 +1279,7 @@ MCSymbol *DwarfDebug::getLabelAfterInsn(const MachineInstr *MI) {
// Process beginning of an instruction.
void DwarfDebug::beginInstruction(const MachineInstr *MI) {
assert(CurMI == 0);
assert(CurMI == nullptr);
CurMI = MI;
// Check if source location changes, but ignore DBG_VALUE locations.
if (!MI->isDebugValue()) {
@ -1323,7 +1323,7 @@ void DwarfDebug::beginInstruction(const MachineInstr *MI) {
// Process end of an instruction.
void DwarfDebug::endInstruction() {
assert(CurMI != 0);
assert(CurMI != nullptr);
// Don't create a new label after DBG_VALUE instructions.
// They don't generate code.
if (!CurMI->isDebugValue())
@ -1608,7 +1608,7 @@ void DwarfDebug::endFunction(const MachineFunction *MF) {
CurFn = MF;
else
assert(CurFn == MF);
assert(CurFn != 0);
assert(CurFn != nullptr);
if (!MMI->hasDebugInfo() || LScopes.empty()) {
// If we don't have a lexical scope for this function then there will

8
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
View File

@ -78,8 +78,8 @@ class DbgVariable {
public:
// AbsVar may be NULL.
DbgVariable(DIVariable V, DbgVariable *AV, DwarfDebug *DD)
: Var(V), TheDIE(0), DotDebugLocOffset(~0U), AbsVar(AV), MInsn(0),
FrameIndex(~0), DD(DD) {}
: Var(V), TheDIE(nullptr), DotDebugLocOffset(~0U), AbsVar(AV),
MInsn(nullptr), FrameIndex(~0), DD(DD) {}
// Accessors.
DIVariable getVariable() const { return Var; }
@ -523,7 +523,7 @@ class DwarfDebug : public AsmPrinterHandler {
/// \brief Ensure that a label will be emitted before MI.
void requestLabelBeforeInsn(const MachineInstr *MI) {
LabelsBeforeInsn.insert(std::make_pair(MI, (MCSymbol *)0));
LabelsBeforeInsn.insert(std::make_pair(MI, nullptr));
}
/// \brief Return Label preceding the instruction.
@ -531,7 +531,7 @@ class DwarfDebug : public AsmPrinterHandler {
/// \brief Ensure that a label will be emitted after MI.
void requestLabelAfterInsn(const MachineInstr *MI) {
LabelsAfterInsn.insert(std::make_pair(MI, (MCSymbol *)0));
LabelsAfterInsn.insert(std::make_pair(MI, nullptr));
}
/// \brief Return Label immediately following the instruction.

2
llvm/lib/CodeGen/AsmPrinter/WinCodeViewLineTables.cpp
View File

@ -216,7 +216,7 @@ void WinCodeViewLineTables::endModule() {
if (FnDebugInfo.empty())
return;
assert(Asm != 0);
assert(Asm != nullptr);
Asm->OutStreamer.SwitchSection(
Asm->getObjFileLowering().getCOFFDebugSymbolsSection());
Asm->EmitInt32(COFF::DEBUG_SECTION_MAGIC);

4
llvm/lib/CodeGen/AsmPrinter/WinCodeViewLineTables.h
View File

@ -38,7 +38,7 @@ class WinCodeViewLineTables : public AsmPrinterHandler {
struct FunctionInfo {
SmallVector<MCSymbol *, 10> Instrs;
MCSymbol *End;
FunctionInfo() : End(0) {}
FunctionInfo() : End(nullptr) {}
} *CurFn;
typedef DenseMap<const Function *, FunctionInfo> FnDebugInfoTy;
@ -104,7 +104,7 @@ class WinCodeViewLineTables : public AsmPrinterHandler {
void maybeRecordLocation(DebugLoc DL, const MachineFunction *MF);
void clear() {
assert(CurFn == 0);
assert(CurFn == nullptr);
FileNameRegistry.clear();
InstrInfo.clear();
}

18
llvm/lib/DebugInfo/DWARFDebugInfoEntry.h
View File

@ -39,7 +39,7 @@ class DWARFDebugInfoEntryMinimal {
const DWARFAbbreviationDeclaration *AbbrevDecl;
public:
DWARFDebugInfoEntryMinimal()
: Offset(0), ParentIdx(0), SiblingIdx(0), AbbrevDecl(0) {}
: Offset(0), ParentIdx(0), SiblingIdx(0), AbbrevDecl(nullptr) {}
void dump(raw_ostream &OS, const DWARFUnit *u, unsigned recurseDepth,
unsigned indent = 0) const;
@ -52,7 +52,7 @@ public:
bool extractFast(const DWARFUnit *U, uint32_t *OffsetPtr);
uint32_t getTag() const { return AbbrevDecl ? AbbrevDecl->getTag() : 0; }
bool isNULL() const { return AbbrevDecl == 0; }
bool isNULL() const { return AbbrevDecl == nullptr; }
/// Returns true if DIE represents a subprogram (not inlined).
bool isSubprogramDIE() const;
@ -66,27 +66,27 @@ public:
// We know we are kept in a vector of contiguous entries, so we know
// our parent will be some index behind "this".
DWARFDebugInfoEntryMinimal *getParent() {
return ParentIdx > 0 ? this - ParentIdx : 0;
return ParentIdx > 0 ? this - ParentIdx : nullptr;
}
const DWARFDebugInfoEntryMinimal *getParent() const {
return ParentIdx > 0 ? this - ParentIdx : 0;
return ParentIdx > 0 ? this - ParentIdx : nullptr;
}
// We know we are kept in a vector of contiguous entries, so we know
// our sibling will be some index after "this".
DWARFDebugInfoEntryMinimal *getSibling() {
return SiblingIdx > 0 ? this + SiblingIdx : 0;
return SiblingIdx > 0 ? this + SiblingIdx : nullptr;
}
const DWARFDebugInfoEntryMinimal *getSibling() const {
return SiblingIdx > 0 ? this + SiblingIdx : 0;
return SiblingIdx > 0 ? this + SiblingIdx : nullptr;
}
// We know we are kept in a vector of contiguous entries, so we know
// we don't need to store our child pointer, if we have a child it will
// be the next entry in the list...
DWARFDebugInfoEntryMinimal *getFirstChild() {
return hasChildren() ? this + 1 : 0;
return hasChildren() ? this + 1 : nullptr;
}
const DWARFDebugInfoEntryMinimal *getFirstChild() const {
return hasChildren() ? this + 1 : 0;
return hasChildren() ? this + 1 : nullptr;
}
void setParent(DWARFDebugInfoEntryMinimal *parent) {
@ -168,7 +168,7 @@ public:
/// (except the last DIE) in this chain is contained in address
/// range for next DIE in the chain.
struct DWARFDebugInfoEntryInlinedChain {
DWARFDebugInfoEntryInlinedChain() : U(0) {}
DWARFDebugInfoEntryInlinedChain() : U(nullptr) {}
SmallVector<DWARFDebugInfoEntryMinimal, 4> DIEs;
const DWARFUnit *U;
};

2
llvm/lib/DebugInfo/DWARFDebugLine.h
View File

@ -24,7 +24,7 @@ class DWARFDebugLine {
public:
DWARFDebugLine(const RelocAddrMap* LineInfoRelocMap) : RelocMap(LineInfoRelocMap) {}
struct FileNameEntry {
FileNameEntry() : Name(0), DirIdx(0), ModTime(0), Length(0) {}
FileNameEntry() : Name(nullptr), DirIdx(0), ModTime(0), Length(0) {}
const char *Name;
uint64_t DirIdx;

2
llvm/lib/DebugInfo/DWARFUnit.h
View File

@ -118,7 +118,7 @@ public:
const DWARFDebugInfoEntryMinimal *
getCompileUnitDIE(bool extract_cu_die_only = true) {
extractDIEsIfNeeded(extract_cu_die_only);
return DieArray.empty() ? NULL : &DieArray[0];
return DieArray.empty() ? nullptr : &DieArray[0];
}
const char *getCompilationDir();

62
llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
View File

@ -58,7 +58,7 @@ static void executeFAddInst(GenericValue &Dest, GenericValue Src1,
IMPLEMENT_BINARY_OPERATOR(+, Double);
default:
dbgs() << "Unhandled type for FAdd instruction: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
}
@ -69,7 +69,7 @@ static void executeFSubInst(GenericValue &Dest, GenericValue Src1,
IMPLEMENT_BINARY_OPERATOR(-, Double);
default:
dbgs() << "Unhandled type for FSub instruction: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
}
@ -80,7 +80,7 @@ static void executeFMulInst(GenericValue &Dest, GenericValue Src1,
IMPLEMENT_BINARY_OPERATOR(*, Double);
default:
dbgs() << "Unhandled type for FMul instruction: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
}
@ -91,7 +91,7 @@ static void executeFDivInst(GenericValue &Dest, GenericValue Src1,
IMPLEMENT_BINARY_OPERATOR(/, Double);
default:
dbgs() << "Unhandled type for FDiv instruction: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
}
@ -106,7 +106,7 @@ static void executeFRemInst(GenericValue &Dest, GenericValue Src1,
break;
default:
dbgs() << "Unhandled type for Rem instruction: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
}
@ -143,7 +143,7 @@ static GenericValue executeICMP_EQ(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(==);
default:
dbgs() << "Unhandled type for ICMP_EQ predicate: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -157,7 +157,7 @@ static GenericValue executeICMP_NE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(!=);
default:
dbgs() << "Unhandled type for ICMP_NE predicate: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -171,7 +171,7 @@ static GenericValue executeICMP_ULT(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(<);
default:
dbgs() << "Unhandled type for ICMP_ULT predicate: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -185,7 +185,7 @@ static GenericValue executeICMP_SLT(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(<);
default:
dbgs() << "Unhandled type for ICMP_SLT predicate: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -199,7 +199,7 @@ static GenericValue executeICMP_UGT(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(>);
default:
dbgs() << "Unhandled type for ICMP_UGT predicate: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -213,7 +213,7 @@ static GenericValue executeICMP_SGT(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(>);
default:
dbgs() << "Unhandled type for ICMP_SGT predicate: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -227,7 +227,7 @@ static GenericValue executeICMP_ULE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(<=);
default:
dbgs() << "Unhandled type for ICMP_ULE predicate: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -241,7 +241,7 @@ static GenericValue executeICMP_SLE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(<=);
default:
dbgs() << "Unhandled type for ICMP_SLE predicate: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -255,7 +255,7 @@ static GenericValue executeICMP_UGE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(>=);
default:
dbgs() << "Unhandled type for ICMP_UGE predicate: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -269,7 +269,7 @@ static GenericValue executeICMP_SGE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_POINTER_ICMP(>=);
default:
dbgs() << "Unhandled type for ICMP_SGE predicate: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -294,7 +294,7 @@ void Interpreter::visitICmpInst(ICmpInst &I) {
case ICmpInst::ICMP_SGE: R = executeICMP_SGE(Src1, Src2, Ty); break;
default:
dbgs() << "Don't know how to handle this ICmp predicate!\n-->" << I;
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
SetValue(&I, R, SF);
@ -330,7 +330,7 @@ static GenericValue executeFCMP_OEQ(GenericValue Src1, GenericValue Src2,
IMPLEMENT_VECTOR_FCMP(==);
default:
dbgs() << "Unhandled type for FCmp EQ instruction: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -386,7 +386,7 @@ static GenericValue executeFCMP_ONE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_VECTOR_FCMP(!=);
default:
dbgs() << "Unhandled type for FCmp NE instruction: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
// in vector case mask out NaN elements
if (Ty->isVectorTy())
@ -406,7 +406,7 @@ static GenericValue executeFCMP_OLE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_VECTOR_FCMP(<=);
default:
dbgs() << "Unhandled type for FCmp LE instruction: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -420,7 +420,7 @@ static GenericValue executeFCMP_OGE(GenericValue Src1, GenericValue Src2,
IMPLEMENT_VECTOR_FCMP(>=);
default:
dbgs() << "Unhandled type for FCmp GE instruction: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -434,7 +434,7 @@ static GenericValue executeFCMP_OLT(GenericValue Src1, GenericValue Src2,
IMPLEMENT_VECTOR_FCMP(<);
default:
dbgs() << "Unhandled type for FCmp LT instruction: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -448,7 +448,7 @@ static GenericValue executeFCMP_OGT(GenericValue Src1, GenericValue Src2,
IMPLEMENT_VECTOR_FCMP(>);
default:
dbgs() << "Unhandled type for FCmp GT instruction: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
return Dest;
}
@ -616,7 +616,7 @@ void Interpreter::visitFCmpInst(FCmpInst &I) {
switch (I.getPredicate()) {
default:
dbgs() << "Don't know how to handle this FCmp predicate!\n-->" << I;
llvm_unreachable(0);
llvm_unreachable(nullptr);
break;
case FCmpInst::FCMP_FALSE: R = executeFCMP_BOOL(Src1, Src2, Ty, false);
break;
@ -673,7 +673,7 @@ static GenericValue executeCmpInst(unsigned predicate, GenericValue Src1,
case FCmpInst::FCMP_TRUE: return executeFCMP_BOOL(Src1, Src2, Ty, true);
default:
dbgs() << "Unhandled Cmp predicate\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
}
@ -727,7 +727,7 @@ void Interpreter::visitBinaryOperator(BinaryOperator &I) {
switch(I.getOpcode()){
default:
dbgs() << "Don't know how to handle this binary operator!\n-->" << I;
llvm_unreachable(0);
llvm_unreachable(nullptr);
break;
case Instruction::Add: INTEGER_VECTOR_OPERATION(+) break;
case Instruction::Sub: INTEGER_VECTOR_OPERATION(-) break;
@ -755,7 +755,7 @@ void Interpreter::visitBinaryOperator(BinaryOperator &I) {
fmod(Src1.AggregateVal[i].DoubleVal, Src2.AggregateVal[i].DoubleVal);
else {
dbgs() << "Unhandled type for Rem instruction: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
}
break;
@ -764,7 +764,7 @@ void Interpreter::visitBinaryOperator(BinaryOperator &I) {
switch (I.getOpcode()) {
default:
dbgs() << "Don't know how to handle this binary operator!\n-->" << I;
llvm_unreachable(0);
llvm_unreachable(nullptr);
break;
case Instruction::Add: R.IntVal = Src1.IntVal + Src2.IntVal; break;
case Instruction::Sub: R.IntVal = Src1.IntVal - Src2.IntVal; break;
@ -980,7 +980,7 @@ void Interpreter::visitAllocaInst(AllocaInst &I) {
<< uintptr_t(Memory) << '\n');
GenericValue Result = PTOGV(Memory);
assert(Result.PointerVal != 0 && "Null pointer returned by malloc!");
assert(Result.PointerVal && "Null pointer returned by malloc!");
SetValue(&I, Result, SF);
if (I.getOpcode() == Instruction::Alloca)
@ -1733,7 +1733,7 @@ void Interpreter::visitVAArgInst(VAArgInst &I) {
IMPLEMENT_VAARG(Double);
default:
dbgs() << "Unhandled dest type for vaarg instruction: " << *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
// Set the Value of this Instruction.
@ -1757,7 +1757,7 @@ void Interpreter::visitExtractElementInst(ExtractElementInst &I) {
default:
dbgs() << "Unhandled destination type for extractelement instruction: "
<< *Ty << "\n";
llvm_unreachable(0);
llvm_unreachable(nullptr);
break;
case Type::IntegerTyID:
Dest.IntVal = Src1.AggregateVal[indx].IntVal;
@ -2074,7 +2074,7 @@ GenericValue Interpreter::getOperandValue(Value *V, ExecutionContext &SF) {
//
void Interpreter::callFunction(Function *F,
const std::vector<GenericValue> &ArgVals) {
assert((ECStack.empty() || ECStack.back().Caller.getInstruction() == 0 ||
assert((ECStack.empty() || !ECStack.back().Caller.getInstruction() ||
ECStack.back().Caller.arg_size() == ArgVals.size()) &&
"Incorrect number of arguments passed into function call!");
// Make a new stack frame... and fill it in.

4
llvm/lib/ExecutionEngine/Interpreter/Interpreter.h
View File

@ -108,7 +108,7 @@ public:
/// create - Create an interpreter ExecutionEngine. This can never fail.
///
static ExecutionEngine *create(Module *M, std::string *ErrorStr = 0);
static ExecutionEngine *create(Module *M, std::string *ErrorStr = nullptr);
/// run - Start execution with the specified function and arguments.
///
@ -118,7 +118,7 @@ public:
void *getPointerToNamedFunction(const std::string &Name,
bool AbortOnFailure = true) override {
// FIXME: not implemented.
return 0;
return nullptr;
}
/// recompileAndRelinkFunction - For the interpreter, functions are always

2
llvm/lib/ExecutionEngine/JIT/JIT.h
View File

@ -189,7 +189,7 @@ public:
TargetMachine *TM);
// Run the JIT on F and return information about the generated code
void runJITOnFunction(Function *F, MachineCodeInfo *MCI = 0) override;
void runJITOnFunction(Function *F, MachineCodeInfo *MCI = nullptr) override;
void RegisterJITEventListener(JITEventListener *L) override;
void UnregisterJITEventListener(JITEventListener *L) override;

2
llvm/lib/ExecutionEngine/JIT/JITMemoryManager.cpp
View File

@ -643,7 +643,7 @@ DefaultJITMemoryManager::DefaultJITMemoryManager()
}
void DefaultJITMemoryManager::AllocateGOT() {
assert(GOTBase == 0 && "Cannot allocate the got multiple times");
assert(!GOTBase && "Cannot allocate the got multiple times");
GOTBase = new uint8_t[sizeof(void*) * 8192];
HasGOT = true;
}

2
llvm/lib/ExecutionEngine/MCJIT/MCJIT.h
View File

@ -71,7 +71,7 @@ public:
ClientMM->deregisterEHFrames(Addr, LoadAddr, Size);
}
bool finalizeMemory(std::string *ErrMsg = 0) override {
bool finalizeMemory(std::string *ErrMsg = nullptr) override {
return ClientMM->finalizeMemory(ErrMsg);
}

2
llvm/lib/ExecutionEngine/RuntimeDyld/ObjectImageCommon.h
View File

@ -48,7 +48,7 @@ public:
object::ObjectFile::createObjectFile(Buffer->getMemBuffer()).get();
}
ObjectImageCommon(object::ObjectFile* Input)
: ObjectImage(NULL), ObjFile(Input) {}
: ObjectImage(nullptr), ObjFile(Input) {}
virtual ~ObjectImageCommon() { delete ObjFile; }
object::symbol_iterator begin_symbols() const override

5
llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h
View File

@ -121,7 +121,8 @@ public:
uint64_t Offset;
int64_t Addend;
const char *SymbolName;
RelocationValueRef() : SectionID(0), Offset(0), Addend(0), SymbolName(0) {}
RelocationValueRef() : SectionID(0), Offset(0), Addend(0),
SymbolName(nullptr) {}
inline bool operator==(const RelocationValueRef &Other) const {
return SectionID == Other.SectionID && Offset == Other.Offset &&
@ -335,7 +336,7 @@ public:
// Work in progress.
SymbolTableMap::const_iterator pos = GlobalSymbolTable.find(Name);
if (pos == GlobalSymbolTable.end())
return 0;
return nullptr;
SymbolLoc Loc = pos->second;
return getSectionAddress(Loc.first) + Loc.second;
}

4
llvm/lib/IR/ConstantsContext.h
View File

@ -586,7 +586,7 @@ public:
/// necessary.
ConstantClass *getOrCreate(TypeClass *Ty, ValRefType V) {
MapKey Lookup(Ty, V);
ConstantClass* Result = 0;
ConstantClass* Result = nullptr;
typename MapTy::iterator I = Map.find(Lookup);
// Is it in the map?
@ -722,7 +722,7 @@ public:
/// necessary.
ConstantClass *getOrCreate(TypeClass *Ty, Operands V) {
LookupKey Lookup(Ty, V);
ConstantClass* Result = 0;
ConstantClass* Result = nullptr;
typename MapTy::iterator I = Map.find_as(Lookup);
// Is it in the map?

4
llvm/lib/IR/LLVMContextImpl.h
View File

@ -56,8 +56,8 @@ struct DenseMapAPIntKeyInfo {
return hash_combine(Key.type, Key.val);
}
};
static inline KeyTy getEmptyKey() { return KeyTy(APInt(1,0), 0); }
static inline KeyTy getTombstoneKey() { return KeyTy(APInt(1,1), 0); }
static inline KeyTy getEmptyKey() { return KeyTy(APInt(1,0), nullptr); }
static inline KeyTy getTombstoneKey() { return KeyTy(APInt(1,1), nullptr); }
static unsigned getHashValue(const KeyTy &Key) {
return static_cast<unsigned>(hash_value(Key));
}

10
llvm/lib/IR/LeaksContext.h
View File

@ -34,10 +34,10 @@ struct PrinterTrait<Value> {
template <typename T>
struct LeakDetectorImpl {
explicit LeakDetectorImpl(const char* const name = "") :
Cache(0), Name(name) { }
Cache(nullptr), Name(name) { }
void clear() {
Cache = 0;
Cache = nullptr;
Ts.clear();
}
@ -61,15 +61,15 @@ struct LeakDetectorImpl {
void removeGarbage(const T* o) {
if (o == Cache)
Cache = 0; // Cache hit
Cache = nullptr; // Cache hit
else
Ts.erase(o);
}
bool hasGarbage(const std::string& Message) {
addGarbage(0); // Flush the Cache
addGarbage(nullptr); // Flush the Cache
assert(Cache == 0 && "No value should be cached anymore!");
assert(!Cache && "No value should be cached anymore!");
if (!Ts.empty()) {
errs() << "Leaked " << Name << " objects found: " << Message << ":\n";

4
llvm/lib/IR/SymbolTableListTraitsImpl.h
View File

@ -65,7 +65,7 @@ void SymbolTableListTraits<ValueSubClass,ItemParentClass>
template<typename ValueSubClass, typename ItemParentClass>
void SymbolTableListTraits<ValueSubClass,ItemParentClass>
::addNodeToList(ValueSubClass *V) {
assert(V->getParent() == 0 && "Value already in a container!!");
assert(!V->getParent() && "Value already in a container!!");
ItemParentClass *Owner = getListOwner();
V->setParent(Owner);
if (V->hasName())
@ -76,7 +76,7 @@ void SymbolTableListTraits<ValueSubClass,ItemParentClass>
template<typename ValueSubClass, typename ItemParentClass>
void SymbolTableListTraits<ValueSubClass,ItemParentClass>
::removeNodeFromList(ValueSubClass *V) {
V->setParent(0);
V->setParent(nullptr);
if (V->hasName())
if (ValueSymbolTable *ST = TraitsClass::getSymTab(getListOwner()))
ST->removeValueName(V->getValueName());

14
llvm/lib/Support/Unix/Memory.inc
View File

@ -121,7 +121,7 @@ Memory::allocateMappedMemory(size_t NumBytes,
Protect, MMFlags, fd, 0);
if (Addr == MAP_FAILED) {
if (NearBlock) //Try again without a near hint
return allocateMappedMemory(NumBytes, 0, PFlags, EC);
return allocateMappedMemory(NumBytes, nullptr, PFlags, EC);
EC = error_code(errno, system_category());
return MemoryBlock();
@ -139,13 +139,13 @@ Memory::allocateMappedMemory(size_t NumBytes,
error_code
Memory::releaseMappedMemory(MemoryBlock &M) {
if (M.Address == 0 || M.Size == 0)
if (M.Address == nullptr || M.Size == 0)
return error_code::success();
if (0 != ::munmap(M.Address, M.Size))
return error_code(errno, system_category());
M.Address = 0;
M.Address = nullptr;
M.Size = 0;
return error_code::success();
@ -153,7 +153,7 @@ Memory::releaseMappedMemory(MemoryBlock &M) {
error_code
Memory::protectMappedMemory(const MemoryBlock &M, unsigned Flags) {
if (M.Address == 0 || M.Size == 0)
if (M.Address == nullptr || M.Size == 0)
return error_code::success();
if (!Flags)
@ -203,7 +203,7 @@ Memory::AllocateRWX(size_t NumBytes, const MemoryBlock* NearBlock,
;
void* start = NearBlock ? (unsigned char*)NearBlock->base() +
NearBlock->size() : 0;
NearBlock->size() : nullptr;
#if defined(__APPLE__) && (defined(__arm__) || defined(__arm64__))
void *pa = ::mmap(start, PageSize*NumPages, PROT_READ|PROT_EXEC,
@ -214,7 +214,7 @@ Memory::AllocateRWX(size_t NumBytes, const MemoryBlock* NearBlock,
#endif
if (pa == MAP_FAILED) {
if (NearBlock) //Try again without a near hint
return AllocateRWX(NumBytes, 0);
return AllocateRWX(NumBytes, nullptr);
MakeErrMsg(ErrMsg, "Can't allocate RWX Memory");
return MemoryBlock();
@ -246,7 +246,7 @@ Memory::AllocateRWX(size_t NumBytes, const MemoryBlock* NearBlock,
}
bool Memory::ReleaseRWX(MemoryBlock &M, std::string *ErrMsg) {
if (M.Address == 0 || M.Size == 0) return false;
if (M.Address == nullptr || M.Size == 0) return false;
if (0 != ::munmap(M.Address, M.Size))
return MakeErrMsg(ErrMsg, "Can't release RWX Memory");
return false;

22
llvm/lib/Support/Unix/Path.inc
View File

@ -89,7 +89,7 @@ namespace {
static error_code TempDir(SmallVectorImpl<char> &result) {
// FIXME: Don't use TMPDIR if program is SUID or SGID enabled.
const char *dir = 0;
const char *dir = nullptr;
(dir = std::getenv("TMPDIR")) || (dir = std::getenv("TMP")) ||
(dir = std::getenv("TEMP")) || (dir = std::getenv("TEMPDIR")) ||
#ifdef P_tmpdir
@ -246,7 +246,7 @@ error_code current_path(SmallVectorImpl<char> &result) {
#endif
while (true) {
if (::getcwd(result.data(), result.capacity()) == 0) {
if (::getcwd(result.data(), result.capacity()) == nullptr) {
// See if there was a real error.
if (errno != errc::not_enough_memory)
return error_code(errno, system_category());
@ -494,7 +494,7 @@ error_code mapped_file_region::init(int FD, bool CloseFD, uint64_t Offset) {
#ifdef MAP_FILE
flags |= MAP_FILE;
#endif
Mapping = ::mmap(0, Size, prot, flags, FD, Offset);
Mapping = ::mmap(nullptr, Size, prot, flags, FD, Offset);
if (Mapping == MAP_FAILED)
return error_code(errno, system_category());
return error_code::success();
@ -525,7 +525,7 @@ mapped_file_region::mapped_file_region(const Twine &path,
ec = init(ofd, true, offset);
if (ec)
Mapping = 0;
Mapping = nullptr;
}
mapped_file_region::mapped_file_region(int fd,
@ -545,7 +545,7 @@ mapped_file_region::mapped_file_region(int fd,
ec = init(fd, closefd, offset);
if (ec)
Mapping = 0;
Mapping = nullptr;
}
mapped_file_region::~mapped_file_region() {
@ -555,7 +555,7 @@ mapped_file_region::~mapped_file_region() {
mapped_file_region::mapped_file_region(mapped_file_region &&other)
: Mode(other.Mode), Size(other.Size), Mapping(other.Mapping) {
other.Mapping = 0;
other.Mapping = nullptr;
}
mapped_file_region::mapmode mapped_file_region::flags() const {
@ -587,7 +587,7 @@ error_code detail::directory_iterator_construct(detail::DirIterState &it,
StringRef path){
SmallString<128> path_null(path);
DIR *directory = ::opendir(path_null.c_str());
if (directory == 0)
if (!directory)
return error_code(errno, system_category());
it.IterationHandle = reinterpret_cast<intptr_t>(directory);
@ -608,9 +608,9 @@ error_code detail::directory_iterator_destruct(detail::DirIterState &it) {
error_code detail::directory_iterator_increment(detail::DirIterState &it) {
errno = 0;
dirent *cur_dir = ::readdir(reinterpret_cast<DIR *>(it.IterationHandle));
if (cur_dir == 0 && errno != 0) {
if (cur_dir == nullptr && errno != 0) {
return error_code(errno, system_category());
} else if (cur_dir != 0) {
} else if (cur_dir != nullptr) {
StringRef name(cur_dir->d_name, NAMLEN(cur_dir));
if ((name.size() == 1 && name[0] == '.') ||
(name.size() == 2 && name[0] == '.' && name[1] == '.'))
@ -630,7 +630,7 @@ error_code get_magic(const Twine &path, uint32_t len,
// Open path.
std::FILE *file = std::fopen(Path.data(), "rb");
if (file == 0)
if (!file)
return error_code(errno, system_category());
// Reserve storage.
@ -667,7 +667,7 @@ error_code map_file_pages(const Twine &path, off_t file_offset, size_t size,
#ifdef MAP_FILE
flags |= MAP_FILE;
#endif
result = ::mmap(0, size, prot, flags, fd, file_offset);
result = ::mmap(nullptr, size, prot, flags, fd, file_offset);
if (result == MAP_FAILED) {
return error_code(errno, system_category());
}

4
llvm/lib/Support/Unix/Process.inc
View File

@ -270,7 +270,7 @@ static bool terminalHasColors(int fd) {
MutexGuard G(M);
int errret = 0;
if (setupterm((char *)0, fd, &errret) != 0)
if (setupterm((char *)nullptr, fd, &errret) != 0)
// Regardless of why, if we can't get terminfo, we shouldn't try to print
// colors.
return false;
@ -292,7 +292,7 @@ static bool terminalHasColors(int fd) {
// Now extract the structure allocated by setupterm and free its memory
// through a really silly dance.
struct term *termp = set_curterm((struct term *)0);
struct term *termp = set_curterm((struct term *)nullptr);
(void)del_curterm(termp); // Drop any errors here.
// Return true if we found a color capabilities for the current terminal.

23
llvm/lib/Support/Unix/Program.inc
View File

@ -70,7 +70,7 @@ sys::FindProgramByName(const std::string& progName) {
// Get the path. If its empty, we can't do anything to find it.
const char *PathStr = getenv("PATH");
if (PathStr == 0)
if (!PathStr)
return "";
// Now we have a colon separated list of directories to search; try them.
@ -99,7 +99,7 @@ sys::FindProgramByName(const std::string& progName) {
}
static bool RedirectIO(const StringRef *Path, int FD, std::string* ErrMsg) {
if (Path == 0) // Noop
if (!Path) // Noop
return false;
std::string File;
if (Path->empty())
@ -129,7 +129,7 @@ static bool RedirectIO(const StringRef *Path, int FD, std::string* ErrMsg) {
#ifdef HAVE_POSIX_SPAWN
static bool RedirectIO_PS(const std::string *Path, int FD, std::string *ErrMsg,
posix_spawn_file_actions_t *FileActions) {
if (Path == 0) // Noop
if (!Path) // Noop
return false;
const char *File;
if (Path->empty())
@ -195,7 +195,7 @@ static bool Execute(ProcessInfo &PI, StringRef Program, const char **args,
#ifdef HAVE_POSIX_SPAWN
if (memoryLimit == 0) {
posix_spawn_file_actions_t FileActionsStore;
posix_spawn_file_actions_t *FileActions = 0;
posix_spawn_file_actions_t *FileActions = nullptr;
// If we call posix_spawn_file_actions_addopen we have to make sure the
// c strings we pass to it stay alive until the call to posix_spawn,
@ -203,7 +203,7 @@ static bool Execute(ProcessInfo &PI, StringRef Program, const char **args,
std::string RedirectsStorage[3];
if (redirects) {
std::string *RedirectsStr[3] = {0, 0, 0};
std::string *RedirectsStr[3] = {nullptr, nullptr, nullptr};
for (int I = 0; I < 3; ++I) {
if (redirects[I]) {
RedirectsStorage[I] = *redirects[I];
@ -218,7 +218,7 @@ static bool Execute(ProcessInfo &PI, StringRef Program, const char **args,
if (RedirectIO_PS(RedirectsStr[0], 0, ErrMsg, FileActions) ||
RedirectIO_PS(RedirectsStr[1], 1, ErrMsg, FileActions))
return false;
if (redirects[1] == 0 || redirects[2] == 0 ||
if (redirects[1] == nullptr || redirects[2] == nullptr ||
*redirects[1] != *redirects[2]) {
// Just redirect stderr
if (RedirectIO_PS(RedirectsStr[2], 2, ErrMsg, FileActions))
@ -242,8 +242,9 @@ static bool Execute(ProcessInfo &PI, StringRef Program, const char **args,
// Explicitly initialized to prevent what appears to be a valgrind false
// positive.
pid_t PID = 0;
int Err = posix_spawn(&PID, Program.str().c_str(), FileActions, /*attrp*/0,
const_cast<char **>(args), const_cast<char **>(envp));
int Err = posix_spawn(&PID, Program.str().c_str(), FileActions,
/*attrp*/nullptr, const_cast<char **>(args),
const_cast<char **>(envp));
if (FileActions)
posix_spawn_file_actions_destroy(FileActions);
@ -294,7 +295,7 @@ static bool Execute(ProcessInfo &PI, StringRef Program, const char **args,
// Execute!
std::string PathStr = Program;
if (envp != 0)
if (envp != nullptr)
execve(PathStr.c_str(),
const_cast<char **>(args),
const_cast<char **>(envp));
@ -360,7 +361,7 @@ ProcessInfo sys::Wait(const ProcessInfo &PI, unsigned SecondsToWait,
// Turn off the alarm and restore the signal handler
alarm(0);
sigaction(SIGALRM, &Old, 0);
sigaction(SIGALRM, &Old, nullptr);
// Wait for child to die
if (wait(&status) != ChildPid)
@ -381,7 +382,7 @@ ProcessInfo sys::Wait(const ProcessInfo &PI, unsigned SecondsToWait,
// We exited normally without timeout, so turn off the timer.
if (SecondsToWait && !WaitUntilTerminates) {
alarm(0);
sigaction(SIGALRM, &Old, 0);
sigaction(SIGALRM, &Old, nullptr);
}
// Return the proper exit status. Detect error conditions

28
llvm/lib/Support/Unix/Signals.inc
View File

@ -44,7 +44,7 @@ static RETSIGTYPE SignalHandler(int Sig); // defined below.
static SmartMutex<true> SignalsMutex;
/// InterruptFunction - The function to call if ctrl-c is pressed.
static void (*InterruptFunction)() = 0;
static void (*InterruptFunction)() = nullptr;
static std::vector<std::string> FilesToRemove;
static std::vector<std::pair<void(*)(void*), void*> > CallBacksToRun;
@ -113,7 +113,7 @@ static void UnregisterHandlers() {
// Restore all of the signal handlers to how they were before we showed up.
for (unsigned i = 0, e = NumRegisteredSignals; i != e; ++i)
sigaction(RegisteredSignalInfo[i].SigNo,
&RegisteredSignalInfo[i].SA, 0);
&RegisteredSignalInfo[i].SA, nullptr);
NumRegisteredSignals = 0;
}
@ -160,7 +160,7 @@ static RETSIGTYPE SignalHandler(int Sig) {
// Unmask all potentially blocked kill signals.
sigset_t SigMask;
sigfillset(&SigMask);
sigprocmask(SIG_UNBLOCK, &SigMask, 0);
sigprocmask(SIG_UNBLOCK, &SigMask, nullptr);
SignalsMutex.acquire();
RemoveFilesToRemove();
@ -169,7 +169,7 @@ static RETSIGTYPE SignalHandler(int Sig) {
if (InterruptFunction) {
void (*IF)() = InterruptFunction;
SignalsMutex.release();
InterruptFunction = 0;
InterruptFunction = nullptr;
IF(); // run the interrupt function.
return;
}
@ -212,7 +212,7 @@ void llvm::sys::SetInterruptFunction(void (*IF)()) {
bool llvm::sys::RemoveFileOnSignal(StringRef Filename,
std::string* ErrMsg) {
SignalsMutex.acquire();
std::string *OldPtr = FilesToRemove.empty() ? 0 : &FilesToRemove[0];
std::string *OldPtr = FilesToRemove.empty() ? nullptr : &FilesToRemove[0];
FilesToRemove.push_back(Filename);
// We want to call 'c_str()' on every std::string in this vector so that if
@ -279,8 +279,8 @@ void llvm::sys::PrintStackTrace(FILE *FD) {
const char* name = strrchr(dlinfo.dli_fname, '/');
int nwidth;
if (name == NULL) nwidth = strlen(dlinfo.dli_fname);
else nwidth = strlen(name) - 1;
if (!name) nwidth = strlen(dlinfo.dli_fname);
else nwidth = strlen(name) - 1;
if (nwidth > width) width = nwidth;
}
@ -292,22 +292,22 @@ void llvm::sys::PrintStackTrace(FILE *FD) {
fprintf(FD, "%-2d", i);
const char* name = strrchr(dlinfo.dli_fname, '/');
if (name == NULL) fprintf(FD, " %-*s", width, dlinfo.dli_fname);
else fprintf(FD, " %-*s", width, name+1);
if (!name) fprintf(FD, " %-*s", width, dlinfo.dli_fname);
else fprintf(FD, " %-*s", width, name+1);
fprintf(FD, " %#0*lx",
(int)(sizeof(void*) * 2) + 2, (unsigned long)StackTrace[i]);
if (dlinfo.dli_sname != NULL) {
if (dlinfo.dli_sname != nullptr) {
fputc(' ', FD);
# if HAVE_CXXABI_H
int res;
char* d = abi::__cxa_demangle(dlinfo.dli_sname, NULL, NULL, &res);
char* d = abi::__cxa_demangle(dlinfo.dli_sname, nullptr, nullptr, &res);
# else
char* d = NULL;
# endif
if (d == NULL) fputs(dlinfo.dli_sname, FD);
else fputs(d, FD);
if (!d) fputs(dlinfo.dli_sname, FD);
else fputs(d, FD);
free(d);
// FIXME: When we move to C++11, use %t length modifier. It's not in
@ -331,7 +331,7 @@ static void PrintStackTraceSignalHandler(void *) {
/// PrintStackTraceOnErrorSignal - When an error signal (such as SIGABRT or
/// SIGSEGV) is delivered to the process, print a stack trace and then exit.
void llvm::sys::PrintStackTraceOnErrorSignal() {
AddSignalHandler(PrintStackTraceSignalHandler, 0);
AddSignalHandler(PrintStackTraceSignalHandler, nullptr);
#if defined(__APPLE__) && defined(ENABLE_CRASH_OVERRIDES)
// Environment variable to disable any kind of crash dialog.

2
llvm/lib/Support/Unix/TimeValue.inc
View File

@ -36,7 +36,7 @@ std::string TimeValue::str() const {
TimeValue TimeValue::now() {
struct timeval the_time;
timerclear(&the_time);
if (0 != ::gettimeofday(&the_time,0)) {
if (0 != ::gettimeofday(&the_time,nullptr)) {
// This is *really* unlikely to occur because the only gettimeofday
// errors concern the timezone parameter which we're passing in as 0.
// In the unlikely case it does happen, just return MinTime, no error

2
llvm/lib/TableGen/TGParser.cpp
View File

@ -115,7 +115,7 @@ bool TGParser::SetValue(Record *CurRec, SMLoc Loc, Init *ValName,
// We should have a BitsInit type now.
BitsInit *BInit = dyn_cast<BitsInit>(BI);
assert(BInit != 0);
assert(BInit != nullptr);
SmallVector<Init *, 16> NewBits(CurVal->getNumBits());

12
llvm/lib/TableGen/TGParser.h
View File

@ -85,7 +85,7 @@ class TGParser {
public:
TGParser(SourceMgr &SrcMgr, RecordKeeper &records)
: Lex(SrcMgr), CurMultiClass(0), Records(records), AnonCounter(0) {}
: Lex(SrcMgr), CurMultiClass(nullptr), Records(records), AnonCounter(0) {}
/// ParseFile - Main entrypoint for parsing a tblgen file. These parser
/// routines return true on error, or false on success.
@ -131,7 +131,7 @@ private: // Semantic analysis methods.
bool ProcessForeachDefs(Record *CurRec, SMLoc Loc, IterSet &IterVals);
private: // Parser methods.
bool ParseObjectList(MultiClass *MC = 0);
bool ParseObjectList(MultiClass *MC = nullptr);
bool ParseObject(MultiClass *MC);
bool ParseClass();
bool ParseMultiClass();
@ -169,12 +169,12 @@ private: // Parser methods.
Init *ParseIDValue(Record *CurRec, const std::string &Name, SMLoc NameLoc,
IDParseMode Mode = ParseValueMode);
Init *ParseSimpleValue(Record *CurRec, RecTy *ItemType = 0,
Init *ParseSimpleValue(Record *CurRec, RecTy *ItemType = nullptr,
IDParseMode Mode = ParseValueMode);
Init *ParseValue(Record *CurRec, RecTy *ItemType = 0,
Init *ParseValue(Record *CurRec, RecTy *ItemType = nullptr,
IDParseMode Mode = ParseValueMode);
std::vector<Init*> ParseValueList(Record *CurRec, Record *ArgsRec = 0,
RecTy *EltTy = 0);
std::vector<Init*> ParseValueList(Record *CurRec, Record *ArgsRec = nullptr,
RecTy *EltTy = nullptr);
std::vector<std::pair<llvm::Init*, std::string> > ParseDagArgList(Record *);
bool ParseOptionalRangeList(std::vector<unsigned> &Ranges);
bool ParseOptionalBitList(std::vector<unsigned> &Ranges);

2
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
View File

@ -1559,7 +1559,7 @@ SDNode *AArch64DAGToDAGISel::Select(SDNode *Node) {
SDNode *ResNode = SelectCode(Node);
DEBUG(dbgs() << "=> ";
if (ResNode == NULL || ResNode == Node)
if (ResNode == nullptr || ResNode == Node)
Node->dump(CurDAG);
else
ResNode->dump(CurDAG);

4
llvm/lib/Target/AArch64/AArch64RegisterInfo.h
View File

@ -27,7 +27,7 @@ class AArch64Subtarget;
struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
AArch64RegisterInfo();
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF =nullptr) const;
const uint32_t *getCallPreservedMask(CallingConv::ID) const;
unsigned getCSRFirstUseCost() const {
@ -44,7 +44,7 @@ struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
unsigned FIOperandNum,
RegScavenger *Rs = NULL) const;
RegScavenger *Rs = nullptr) const;
/// getCrossCopyRegClass - Returns a legal register class to copy a register
/// in the specified class to or from. Returns original class if it is

9
llvm/lib/Target/ARM/ARMAsmPrinter.h
View File

@ -47,16 +47,17 @@ class LLVM_LIBRARY_VISIBILITY ARMAsmPrinter : public AsmPrinter {
bool InConstantPool;
public:
explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
: AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL), InConstantPool(false) {
Subtarget = &TM.getSubtarget<ARMSubtarget>();
}
: AsmPrinter(TM, Streamer), AFI(nullptr), MCP(nullptr),
InConstantPool(false) {
Subtarget = &TM.getSubtarget<ARMSubtarget>();
}
const char *getPassName() const override {
return "ARM Assembly / Object Emitter";
}
void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
const char *Modifier = 0);
const char *Modifier = nullptr);
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant, const char *ExtraCode,

2
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -624,7 +624,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
unsigned JTI = JTOP.getIndex();
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
assert(MJTI != 0);
assert(MJTI != nullptr);
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
assert(JTI < JT.size());
// Thumb instructions are 2 byte aligned, but JT entries are 4 byte

2
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -261,7 +261,7 @@ private:
unsigned getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,
unsigned *PredCost = 0) const override;
unsigned *PredCost = nullptr) const override;
int getInstrLatency(const InstrItineraryData *ItinData,
SDNode *Node) const override;

4
llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
View File

@ -101,7 +101,7 @@ protected:
public:
/// Code Generation virtual methods...
const MCPhysReg *
getCalleeSavedRegs(const MachineFunction *MF = 0) const override;
getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
const uint32_t *getNoPreservedMask() const;
@ -186,7 +186,7 @@ public:
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = NULL) const override;
RegScavenger *RS = nullptr) const override;
};
} // end namespace llvm

2
llvm/lib/Target/ARM/ARMHazardRecognizer.h
View File

@ -35,7 +35,7 @@ public:
ARMHazardRecognizer(const InstrItineraryData *ItinData,
const ScheduleDAG *DAG)
: ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"),
LastMI(0) {}
LastMI(nullptr) {}
HazardType getHazardType(SUnit *SU, int Stalls) override;
void Reset() override;

2
llvm/lib/Target/ARM/ARMTargetObjectFile.h
View File

@ -23,7 +23,7 @@ protected:
public:
ARMElfTargetObjectFile() :
TargetLoweringObjectFileELF(),
AttributesSection(NULL)
AttributesSection(nullptr)
{}
void Initialize(MCContext &Ctx, const TargetMachine &TM) override;

2
llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
View File

@ -1102,7 +1102,7 @@ void ARMELFStreamer::Reset() {
}
void ARMELFStreamer::emitFnStart() {
assert(FnStart == 0);
assert(FnStart == nullptr);
FnStart = getContext().CreateTempSymbol();
EmitLabel(FnStart);
}

2
llvm/lib/Target/ARM/Thumb1RegisterInfo.h
View File

@ -56,7 +56,7 @@ public:
unsigned Reg) const override;
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = NULL) const override;
RegScavenger *RS = nullptr) const override;
};
}

2
llvm/lib/Target/ARM64/ARM64ISelLowering.h
View File

@ -190,7 +190,7 @@ public:
/// allowsUnalignedMemoryAccesses - Returns true if the target allows
/// unaligned memory accesses. of the specified type.
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
bool *Fast = 0) const override {
bool *Fast = nullptr) const override {
if (RequireStrictAlign)
return false;
// FIXME: True for Cyclone, but not necessary others.

6
llvm/lib/Target/ARM64/ARM64InstrInfo.h
View File

@ -193,9 +193,9 @@ enum ARM64FrameOffsetStatus {
/// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
/// is a legal offset.
int isARM64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
bool *OutUseUnscaledOp = NULL,
unsigned *OutUnscaledOp = NULL,
int *EmittableOffset = NULL);
bool *OutUseUnscaledOp = nullptr,
unsigned *OutUnscaledOp = nullptr,
int *EmittableOffset = nullptr);
static inline bool isUncondBranchOpcode(int Opc) { return Opc == ARM64::B; }

4
llvm/lib/Target/ARM64/ARM64RegisterInfo.h
View File

@ -37,7 +37,7 @@ public:
/// Code Generation virtual methods...
const MCPhysReg *
getCalleeSavedRegs(const MachineFunction *MF = 0) const override;
getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
unsigned getCSRFirstUseCost() const {
@ -82,7 +82,7 @@ public:
int64_t Offset) const override;
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS = NULL) const override;
RegScavenger *RS = nullptr) const override;
bool cannotEliminateFrame(const MachineFunction &MF) const;
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;

4
llvm/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h
View File

@ -48,7 +48,7 @@ static inline const char *getShiftName(ARM64_AM::ShiftType ST) {
case ARM64_AM::ROR: return "ror";
case ARM64_AM::MSL: return "msl";
}
return 0;
return nullptr;
}
/// getShiftType - Extract the shift type.
@ -104,7 +104,7 @@ static inline const char *getExtendName(ARM64_AM::ExtendType ET) {
case ARM64_AM::SXTW: return "sxtw";
case ARM64_AM::SXTX: return "sxtx";
}
return 0;
return nullptr;
}
/// getArithShiftValue - get the arithmetic shift value.

2
llvm/lib/Target/CppBackend/CPPTargetMachine.h
View File

@ -35,7 +35,7 @@ struct CPPTargetMachine : public TargetMachine {
AnalysisID StartAfter,
AnalysisID StopAfter);
virtual const DataLayout *getDataLayout() const { return 0; }
virtual const DataLayout *getDataLayout() const { return nullptr; }
};
extern Target TheCppBackendTarget;

2
llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
View File

@ -333,7 +333,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
// Check for an exact kill (registers match).
if (I1UseReg && I->killsRegister(I1UseReg)) {
assert(KillingInstr == 0 && "Should only see one killing instruction");
assert(!KillingInstr && "Should only see one killing instruction");
KilledOperand = I1UseReg;
KillingInstr = &*I;
}

2
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -137,7 +137,7 @@ CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
return false;
}
llvm_unreachable(0);
llvm_unreachable(nullptr);
}

2
llvm/lib/Target/Hexagon/HexagonInstrInfo.h
View File

@ -111,7 +111,7 @@ public:
MachineInstr* MI,
const SmallVectorImpl<unsigned> &Ops,
MachineInstr* LoadMI) const {
return 0;
return nullptr;
}
unsigned createVR(MachineFunction* MF, MVT VT) const;

13
llvm/lib/Target/Hexagon/HexagonMachineScheduler.h
View File

@ -56,7 +56,7 @@ class VLIWResourceModel {
public:
VLIWResourceModel(const TargetMachine &TM, const TargetSchedModel *SM) :
SchedModel(SM), TotalPackets(0) {
ResourcesModel = TM.getInstrInfo()->CreateTargetScheduleState(&TM,NULL);
ResourcesModel = TM.getInstrInfo()->CreateTargetScheduleState(&TM, nullptr);
// This hard requirement could be relaxed,
// but for now do not let it proceed.
@ -120,7 +120,7 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy {
// Best scheduling cost.
int SCost;
SchedCandidate(): SU(NULL), SCost(0) {}
SchedCandidate(): SU(nullptr), SCost(0) {}
};
/// Represent the type of SchedCandidate found within a single queue.
enum CandResult {
@ -153,9 +153,9 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy {
/// Pending queues extend the ready queues with the same ID and the
/// PendingFlag set.
VLIWSchedBoundary(unsigned ID, const Twine &Name):
DAG(0), SchedModel(0), Available(ID, Name+".A"),
DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"),
Pending(ID << ConvergingVLIWScheduler::LogMaxQID, Name+".P"),
CheckPending(false), HazardRec(0), ResourceModel(0),
CheckPending(false), HazardRec(nullptr), ResourceModel(nullptr),
CurrCycle(0), IssueCount(0),
MinReadyCycle(UINT_MAX), MaxMinLatency(0) {}
@ -203,8 +203,9 @@ public:
LogMaxQID = 2
};
ConvergingVLIWScheduler():
DAG(0), SchedModel(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
ConvergingVLIWScheduler()
: DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"),
Bot(BotQID, "BotQ") {}
virtual void initialize(ScheduleDAGMI *dag) override;

9
llvm/lib/Target/Hexagon/HexagonRegisterInfo.h
View File

@ -48,16 +48,17 @@ struct HexagonRegisterInfo : public HexagonGenRegisterInfo {
HexagonRegisterInfo(HexagonSubtarget &st);
/// Code Generation virtual methods...
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const MCPhysReg *
getCalleeSavedRegs(const MachineFunction *MF = nullptr) const;
const TargetRegisterClass* const* getCalleeSavedRegClasses(
const MachineFunction *MF = 0) const;
const TargetRegisterClass* const*
getCalleeSavedRegClasses(const MachineFunction *MF = nullptr) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = NULL) const;
RegScavenger *RS = nullptr) const;
/// determineFrameLayout - Determine the size of the frame and maximum call
/// frame size.

2
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h
View File

@ -31,7 +31,7 @@ namespace llvm {
public:
explicit HexagonMCInst():
MCInst(), MCID(0), packetStart(0), packetEnd(0) {};
MCInst(), MCID(nullptr), packetStart(0), packetEnd(0) {};
HexagonMCInst(const MCInstrDesc& mcid):
MCInst(), MCID(&mcid), packetStart(0), packetEnd(0) {};

2
llvm/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.cpp
View File

@ -45,7 +45,7 @@ void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo,
void MSP430InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O, const char *Modifier) {
assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
assert((Modifier == nullptr || Modifier[0] == 0) && "No modifiers supported");
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
O << getRegisterName(Op.getReg());

4
llvm/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h
View File

@ -32,10 +32,10 @@ namespace llvm {
static const char *getRegisterName(unsigned RegNo);
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
const char *Modifier = 0);
const char *Modifier = nullptr);
void printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printSrcMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
const char *Modifier = 0);
const char *Modifier = nullptr);
void printCCOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
};

2
llvm/lib/Target/MSP430/MSP430FrameLowering.h
View File

@ -51,7 +51,7 @@ public:
bool hasFP(const MachineFunction &MF) const;
bool hasReservedCallFrame(const MachineFunction &MF) const;
void processFunctionBeforeFrameFinalized(MachineFunction &MF,
RegScavenger *RS = NULL) const;
RegScavenger *RS = nullptr) const;
};
} // End llvm namespace

2
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -462,7 +462,7 @@ MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
errs() << "LowerFormalArguments Unhandled argument type: "
<< RegVT.getSimpleVT().SimpleTy << "\n";
#endif
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
case MVT::i16:
unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);

5
llvm/lib/Target/MSP430/MSP430RegisterInfo.h
View File

@ -35,7 +35,8 @@ public:
MSP430RegisterInfo(MSP430TargetMachine &tm);
/// Code Generation virtual methods...
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const MCPhysReg *
getCalleeSavedRegs(const MachineFunction *MF = nullptr) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
const TargetRegisterClass*
@ -43,7 +44,7 @@ public:
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = NULL) const;
RegScavenger *RS = nullptr) const;
// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const;

2
llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
View File

@ -18,7 +18,7 @@ namespace llvm {
static const unsigned MIPS_NACL_BUNDLE_ALIGN = 4u;
bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
bool *IsStore = NULL);
bool *IsStore = nullptr);
bool baseRegNeedsLoadStoreMask(unsigned Reg);
// This function creates an MCELFStreamer for Mips NaCl.

4
llvm/lib/Target/Mips/MipsAsmPrinter.h
View File

@ -82,7 +82,7 @@ public:
MipsMCInstLower MCInstLowering;
explicit MipsAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
: AsmPrinter(TM, Streamer), MCP(0), InConstantPool(false),
: AsmPrinter(TM, Streamer), MCP(nullptr), InConstantPool(false),
MCInstLowering(*this) {
Subtarget = &TM.getSubtarget<MipsSubtarget>();
}
@ -122,7 +122,7 @@ public:
void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O);
void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
const char *Modifier = 0);
const char *Modifier = nullptr);
void EmitStartOfAsmFile(Module &M);
void EmitEndOfAsmFile(Module &M);
void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);

6
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -3268,7 +3268,7 @@ analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
dbgs() << "Call operand #" << I << " has unhandled type "
<< EVT(ArgVT).getEVTString();
#endif
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
}
}
@ -3300,7 +3300,7 @@ analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
dbgs() << "Formal Arg #" << I << " has unhandled type "
<< EVT(ArgVT).getEVTString();
#endif
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
}
@ -3325,7 +3325,7 @@ analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
dbgs() << "Call result #" << I << " has unhandled type "
<< EVT(VT).getEVTString() << '\n';
#endif
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
}
}

2
llvm/lib/Target/Mips/MipsMachineFunction.cpp
View File

@ -27,7 +27,7 @@ FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
MipsCallEntry::MipsCallEntry(const StringRef &N) {
#ifndef NDEBUG
Name = N;
Val = 0;
Val = nullptr;
#endif
}

2
llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
View File

@ -155,7 +155,7 @@ static void eraseGPOpnd(MachineInstr &MI) {
}
}
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
MBBInfo::MBBInfo(MachineDomTreeNode *N) : Node(N), HTScope(nullptr) {}

6
llvm/lib/Target/Mips/MipsRegisterInfo.h
View File

@ -47,7 +47,7 @@ public:
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const;
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF =nullptr) const;
const uint32_t *getCallPreservedMask(CallingConv::ID) const;
static const uint32_t *getMips16RetHelperMask();
@ -60,10 +60,10 @@ public:
/// Stack Frame Processing Methods
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = NULL) const;
RegScavenger *RS = nullptr) const;
void processFunctionBeforeFrameFinalized(MachineFunction &MF,
RegScavenger *RS = NULL) const;
RegScavenger *RS = nullptr) const;
/// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const;

4
llvm/lib/Target/Mips/MipsSEISelLowering.h
View File

@ -30,8 +30,8 @@ namespace llvm {
void addMSAFloatType(MVT::SimpleValueType Ty,
const TargetRegisterClass *RC);
virtual bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS = 0,
bool *Fast = 0) const override;
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS = 0,
bool *Fast = nullptr) const override;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;

2
llvm/lib/Target/Mips/MipsTargetMachine.h
View File

@ -67,7 +67,7 @@ public:
{ return &DL;}
virtual const InstrItineraryData *getInstrItineraryData() const {
return Subtarget.inMips16Mode() ? 0 : &InstrItins;
return Subtarget.inMips16Mode() ? nullptr : &InstrItins;
}
virtual MipsJITInfo *getJITInfo()

10
llvm/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.h
View File

@ -37,15 +37,15 @@ public:
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printCvtMode(const MCInst *MI, int OpNum, raw_ostream &O,
const char *Modifier = 0);
const char *Modifier = nullptr);
void printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O,
const char *Modifier = 0);
const char *Modifier = nullptr);
void printLdStCode(const MCInst *MI, int OpNum,
raw_ostream &O, const char *Modifier = 0);
raw_ostream &O, const char *Modifier = nullptr);
void printMemOperand(const MCInst *MI, int OpNum,
raw_ostream &O, const char *Modifier = 0);
raw_ostream &O, const char *Modifier = nullptr);
void printProtoIdent(const MCInst *MI, int OpNum,
raw_ostream &O, const char *Modifier = 0);
raw_ostream &O, const char *Modifier = nullptr);
};
}

8
llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
View File

@ -208,12 +208,12 @@ private:
MCOperand GetSymbolRef(const MCSymbol *Symbol);
unsigned encodeVirtualRegister(unsigned Reg);
void EmitAlignment(unsigned NumBits, const GlobalValue *GV = 0) const {}
void EmitAlignment(unsigned NumBits, const GlobalValue *GV = nullptr) const {}
void printVecModifiedImmediate(const MachineOperand &MO, const char *Modifier,
raw_ostream &O);
void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
const char *Modifier = 0);
const char *Modifier = nullptr);
void printImplicitDef(const MachineInstr *MI, raw_ostream &O) const;
void printModuleLevelGV(const GlobalVariable *GVar, raw_ostream &O,
bool = false);
@ -236,7 +236,7 @@ private:
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &);
void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
const char *Modifier = 0);
const char *Modifier = nullptr);
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &);
@ -312,7 +312,7 @@ public:
: AsmPrinter(TM, Streamer),
nvptxSubtarget(TM.getSubtarget<NVPTXSubtarget>()) {
CurrentBankselLabelInBasicBlock = "";
reader = NULL;
reader = nullptr;
EmitGeneric = (nvptxSubtarget.getDrvInterface() == NVPTX::CUDA);
}

2
llvm/lib/Target/NVPTX/NVPTXMCExpr.h
View File

@ -68,7 +68,7 @@ public:
}
void AddValueSymbols(MCAssembler *) const {};
const MCSection *FindAssociatedSection() const {
return NULL;
return nullptr;
}
// There are no TLS NVPTXMCExprs at the moment.

4
llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h
View File

@ -42,7 +42,7 @@ public:
// NVPTX callee saved registers
virtual const MCPhysReg *
getCalleeSavedRegs(const MachineFunction *MF = 0) const;
getCalleeSavedRegs(const MachineFunction *MF = nullptr) const;
// NVPTX callee saved register classes
virtual const TargetRegisterClass *const *
@ -52,7 +52,7 @@ public:
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS = NULL) const;
RegScavenger *RS = nullptr) const;
virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const;
virtual unsigned getFrameRegister(const MachineFunction &MF) const;

38
llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h
View File

@ -22,26 +22,26 @@ class NVPTXTargetObjectFile : public TargetLoweringObjectFile {
public:
NVPTXTargetObjectFile() {
TextSection = 0;
DataSection = 0;
BSSSection = 0;
ReadOnlySection = 0;
TextSection = nullptr;
DataSection = nullptr;
BSSSection = nullptr;
ReadOnlySection = nullptr;
StaticCtorSection = 0;
StaticDtorSection = 0;
LSDASection = 0;
EHFrameSection = 0;
DwarfAbbrevSection = 0;
DwarfInfoSection = 0;
DwarfLineSection = 0;
DwarfFrameSection = 0;
DwarfPubTypesSection = 0;
DwarfDebugInlineSection = 0;
DwarfStrSection = 0;
DwarfLocSection = 0;
DwarfARangesSection = 0;
DwarfRangesSection = 0;
DwarfMacroInfoSection = 0;
StaticCtorSection = nullptr;
StaticDtorSection = nullptr;
LSDASection = nullptr;
EHFrameSection = nullptr;
DwarfAbbrevSection = nullptr;
DwarfInfoSection = nullptr;
DwarfLineSection = nullptr;
DwarfFrameSection = nullptr;
DwarfPubTypesSection = nullptr;
DwarfDebugInlineSection = nullptr;
DwarfStrSection = nullptr;
DwarfLocSection = nullptr;
DwarfARangesSection = nullptr;
DwarfRangesSection = nullptr;
DwarfMacroInfoSection = nullptr;
}
virtual ~NVPTXTargetObjectFile();

2
llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
View File

@ -41,7 +41,7 @@ public:
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printPredicateOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O, const char *Modifier = 0);
raw_ostream &O, const char *Modifier = nullptr);
void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);

6
llvm/lib/Target/PowerPC/PPCFrameLowering.h
View File

@ -46,9 +46,9 @@ public:
void replaceFPWithRealFP(MachineFunction &MF) const;
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS = NULL) const;
RegScavenger *RS = nullptr) const;
void processFunctionBeforeFrameFinalized(MachineFunction &MF,
RegScavenger *RS = NULL) const;
RegScavenger *RS = nullptr) const;
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
@ -156,7 +156,7 @@ public:
// Early exit if not using the SVR4 ABI.
if (!Subtarget.isSVR4ABI()) {
NumEntries = 0;
return 0;
return nullptr;
}
// Note that the offsets here overlap, but this is fixed up in

4
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -3801,7 +3801,7 @@ PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
errs() << "Call operand #" << i << " has unhandled type "
<< EVT(ArgVT).getEVTString() << "\n";
#endif
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
}
} else {
@ -5487,7 +5487,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
SelectionDAG &DAG) const {
SDLoc dl(Op);
BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
// Check if this is a splat of a constant value.
APInt APSplatBits, APSplatUndef;

2
llvm/lib/Target/PowerPC/PPCISelLowering.h
View File

@ -492,7 +492,7 @@ namespace llvm {
/// relative to software emulation.
virtual bool allowsUnalignedMemoryAccesses(EVT VT,
unsigned AddrSpace,
bool *Fast = 0) const;
bool *Fast = nullptr) const;
/// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
/// than a pair of fmul and fadd instructions. fmuladd intrinsics will be

4
llvm/lib/Target/PowerPC/PPCRegisterInfo.h
View File

@ -44,7 +44,7 @@ public:
getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
/// Code Generation virtual methods...
const MCPhysReg *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
const MCPhysReg *getCalleeSavedRegs(const MachineFunction* MF =nullptr) const;
const uint32_t *getCallPreservedMask(CallingConv::ID CC) const;
const uint32_t *getNoPreservedMask() const;
@ -85,7 +85,7 @@ public:
int &FrameIdx) const;
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = NULL) const;
RegScavenger *RS = nullptr) const;
// Support for virtual base registers.
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;

2
llvm/lib/Target/R600/AMDGPUInstrInfo.h
View File

@ -118,7 +118,7 @@ public:
SmallVectorImpl<SDNode *> &NewNodes) const;
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
bool UnfoldLoad, bool UnfoldStore,
unsigned *LoadRegIndex = 0) const;
unsigned *LoadRegIndex = nullptr) const;
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
int64_t Offset1, int64_t Offset2,
unsigned NumLoads) const;

4
llvm/lib/Target/R600/AMDGPURegisterInfo.h
View File

@ -43,11 +43,11 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
/// \returns The ISA reg class that is equivalent to \p RC.
virtual const TargetRegisterClass * getISARegClass(
const TargetRegisterClass * RC) const {
assert(!"Unimplemented"); return NULL;
assert(!"Unimplemented"); return nullptr;
}
virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
assert(!"Unimplemented"); return NULL;
assert(!"Unimplemented"); return nullptr;
}
virtual unsigned getHWRegIndex(unsigned Reg) const {

2
llvm/lib/Target/R600/AMDILCFGStructurizer.cpp
View File

@ -168,7 +168,7 @@ public:
MLI = &getAnalysis<MachineLoopInfo>();
DEBUG(dbgs() << "LoopInfo:\n"; PrintLoopinfo(*MLI););
MDT = &getAnalysis<MachineDominatorTree>();
DEBUG(MDT->print(dbgs(), (const llvm::Module*)0););
DEBUG(MDT->print(dbgs(), (const llvm::Module*)nullptr););
PDT = &getAnalysis<MachinePostDominatorTree>();
DEBUG(PDT->print(dbgs()););
prepare();

4
llvm/lib/Target/R600/AMDILIntrinsicInfo.h
View File

@ -34,12 +34,12 @@ enum ID {
class AMDGPUIntrinsicInfo : public TargetIntrinsicInfo {
public:
AMDGPUIntrinsicInfo(TargetMachine *tm);
std::string getName(unsigned int IntrId, Type **Tys = 0,
std::string getName(unsigned int IntrId, Type **Tys = nullptr,
unsigned int numTys = 0) const;
unsigned int lookupName(const char *Name, unsigned int Len) const;
bool isOverloaded(unsigned int IID) const;
Function *getDeclaration(Module *M, unsigned int ID,
Type **Tys = 0,
Type **Tys = nullptr,
unsigned int numTys = 0) const;
};

2
llvm/lib/Target/R600/R600InstrInfo.h
View File

@ -192,7 +192,7 @@ namespace llvm {
unsigned int getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,
unsigned *PredCost = 0) const;
unsigned *PredCost = nullptr) const;
virtual int getInstrLatency(const InstrItineraryData *ItinData,
SDNode *Node) const { return 1;}

2
llvm/lib/Target/R600/R600MachineScheduler.h
View File

@ -68,7 +68,7 @@ class R600SchedStrategy : public MachineSchedStrategy {
public:
R600SchedStrategy() :
DAG(0), TII(0), TRI(0), MRI(0) {
DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
}
virtual ~R600SchedStrategy() {

2
llvm/lib/Target/R600/SIInstrInfo.h
View File

@ -79,7 +79,7 @@ public:
bool NewMI=false) const;
bool isTriviallyReMaterializable(const MachineInstr *MI,
AliasAnalysis *AA = 0) const;
AliasAnalysis *AA = nullptr) const;
virtual unsigned getIEQOpcode() const {
llvm_unreachable("Unimplemented");

2
llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
View File

@ -245,7 +245,7 @@ public:
case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
<< getMemOffsetReg() << "\n"; break;
case k_MemoryImm: assert(getMemOff() != 0);
case k_MemoryImm: assert(getMemOff() != nullptr);
OS << "Mem: " << getMemBase()
<< "+" << *getMemOff()
<< "\n"; break;

2
llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.h
View File

@ -42,7 +42,7 @@ public:
void printOperand(const MCInst *MI, int opNum, raw_ostream &OS);
void printMemOperand(const MCInst *MI, int opNum, raw_ostream &OS,
const char *Modifier = 0);
const char *Modifier = nullptr);
void printCCOperand(const MCInst *MI, int opNum, raw_ostream &OS);
bool printGetPCX(const MCInst *MI, unsigned OpNo, raw_ostream &OS);

2
llvm/lib/Target/Sparc/SparcFrameLowering.h
View File

@ -41,7 +41,7 @@ public:
bool hasReservedCallFrame(const MachineFunction &MF) const;
bool hasFP(const MachineFunction &MF) const;
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS = NULL) const;
RegScavenger *RS = nullptr) const;
private:
// Remap input registers to output registers for leaf procedure.

6
llvm/lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -31,7 +31,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
SparcRegisterInfo(SparcSubtarget &st);
/// Code Generation virtual methods...
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF =nullptr) const;
const uint32_t* getCallPreservedMask(CallingConv::ID CC) const;
const uint32_t* getRTCallPreservedMask(CallingConv::ID CC) const;
@ -43,10 +43,10 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = NULL) const;
RegScavenger *RS = nullptr) const;
void processFunctionBeforeFrameFinalized(MachineFunction &MF,
RegScavenger *RS = NULL) const;
RegScavenger *RS = nullptr) const;
// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const;

2
llvm/lib/Target/SystemZ/SystemZInstrInfo.h
View File

@ -229,7 +229,7 @@ public:
// BRANCH exists, return the opcode for the latter, otherwise return 0.
// MI, if nonnull, is the compare instruction.
unsigned getCompareAndBranch(unsigned Opcode,
const MachineInstr *MI = 0) const;
const MachineInstr *MI = nullptr) const;
// Emit code before MBBI in MI to move immediate value Value into
// physical register Reg.

2
llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
View File

@ -49,7 +49,7 @@ public:
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
return true;
}
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = nullptr) const
override;
BitVector getReservedRegs(const MachineFunction &MF) const override;
void eliminateFrameIndex(MachineBasicBlock::iterator MI,

6
llvm/lib/Target/X86/AsmParser/X86Operand.h
View File

@ -422,7 +422,7 @@ struct X86Operand : public MCParsedAsmOperand {
bool AddressOf = false,
SMLoc OffsetOfLoc = SMLoc(),
StringRef SymName = StringRef(),
void *OpDecl = 0) {
void *OpDecl = nullptr) {
X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
Res->Reg.RegNo = RegNo;
Res->AddressOf = AddressOf;
@ -441,7 +441,7 @@ struct X86Operand : public MCParsedAsmOperand {
/// Create an absolute memory operand.
static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
unsigned Size = 0, StringRef SymName = StringRef(),
void *OpDecl = 0) {
void *OpDecl = nullptr) {
X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
Res->Mem.SegReg = 0;
Res->Mem.Disp = Disp;
@ -461,7 +461,7 @@ struct X86Operand : public MCParsedAsmOperand {
unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
unsigned Size = 0,
StringRef SymName = StringRef(),
void *OpDecl = 0) {
void *OpDecl = nullptr) {
// We should never just have a displacement, that should be parsed as an
// absolute memory operand.
assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");

4
llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
View File

@ -80,7 +80,7 @@ static InstructionContext contextForAttrs(uint16_t attrMask) {
static int modRMRequired(OpcodeType type,
InstructionContext insnContext,
uint16_t opcode) {
const struct ContextDecision* decision = 0;
const struct ContextDecision* decision = nullptr;
switch (type) {
case ONEBYTE:
@ -124,7 +124,7 @@ static InstrUID decode(OpcodeType type,
InstructionContext insnContext,
uint8_t opcode,
uint8_t modRM) {
const struct ModRMDecision* dec = 0;
const struct ModRMDecision* dec = nullptr;
switch (type) {
case ONEBYTE:

2
llvm/lib/Target/X86/X86CodeEmitter.cpp
View File

@ -1476,7 +1476,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
#ifndef NDEBUG
dbgs() << "Cannot encode all operands of: " << MI << "\n";
#endif
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
MCE.processDebugLoc(MI.getDebugLoc(), false);

2
llvm/lib/Target/X86/X86FrameLowering.h
View File

@ -47,7 +47,7 @@ public:
void adjustForHiPEPrologue(MachineFunction &MF) const override;
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS = NULL) const override;
RegScavenger *RS = nullptr) const override;
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,

6
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -104,14 +104,14 @@ namespace {
void dump() {
dbgs() << "X86ISelAddressMode " << this << '\n';
dbgs() << "Base_Reg ";
if (Base_Reg.getNode() != 0)
if (Base_Reg.getNode())
Base_Reg.getNode()->dump();
else
dbgs() << "nul";
dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
<< " Scale" << Scale << '\n'
<< "IndexReg ";
if (IndexReg.getNode() != 0)
if (IndexReg.getNode())
IndexReg.getNode()->dump();
else
dbgs() << "nul";
@ -2773,7 +2773,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
SDNode *ResNode = SelectCode(Node);
DEBUG(dbgs() << "=> ";
if (ResNode == NULL || ResNode == Node)
if (ResNode == nullptr || ResNode == Node)
Node->dump(CurDAG);
else
ResNode->dump(CurDAG);

2
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -11515,7 +11515,7 @@ static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
ConstantSDNode *ND;
switch(Opc) {
default: llvm_unreachable(0);
default: llvm_unreachable(nullptr);
case X86ISD::VSHLI:
for (unsigned i=0; i!=NumElts; ++i) {
SDValue CurrentOp = SrcOp->getOperand(i);

2
llvm/lib/Target/X86/X86ISelLowering.h
View File

@ -783,7 +783,7 @@ namespace llvm {
/// Intel processors have a unified instruction and data cache
const char * getClearCacheBuiltinName() const {
return 0; // nothing to do, move along.
return nullptr; // nothing to do, move along.
}
/// createFastISel - This method returns a target specific FastISel object,

3
llvm/lib/Target/X86/X86InstrBuilder.h
View File

@ -52,7 +52,8 @@ struct X86AddressMode {
unsigned GVOpFlags;
X86AddressMode()
: BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) {
: BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
GVOpFlags(0) {
Base.Reg = 0;
}

2
llvm/lib/Target/X86/X86InstrInfo.h
View File

@ -325,7 +325,7 @@ public:
/// value.
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
bool UnfoldLoad, bool UnfoldStore,
unsigned *LoadRegIndex = 0) const override;
unsigned *LoadRegIndex = nullptr) const override;
/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
/// to determine if two loads are loading from the same base address. It

2
llvm/lib/Target/X86/X86RegisterInfo.h
View File

@ -122,7 +122,7 @@ public:
void eliminateFrameIndex(MachineBasicBlock::iterator MI,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = NULL) const override;
RegScavenger *RS = nullptr) const override;
// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const override;

2
llvm/lib/Target/XCore/XCoreFrameLowering.cpp
View File

@ -495,7 +495,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
errs() << "eliminateCallFramePseudoInstr size too big: "
<< Amount << "\n";
#endif
llvm_unreachable(0);
llvm_unreachable(nullptr);
}
MachineInstr *New;

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