forked from OSchip/llvm-project
[Hexagon] Pick the right branch opcode depending on branch probabilities
Specifically, pick the opcode with the correct branch prediction, i.e. jump:t or jump:nt. llvm-svn: 296821
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@ -3470,20 +3470,75 @@ int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {
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int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,
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const MachineBranchProbabilityInfo *MBPI) const {
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// We assume that block can have at most two successors.
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bool taken = false;
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const MachineBasicBlock *Src = MI.getParent();
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const MachineOperand &BrTarget = MI.getOperand(1);
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const MachineBasicBlock *Dst = BrTarget.getMBB();
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bool Taken = false;
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const BranchProbability OneHalf(1, 2);
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const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
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if (Prediction >= BranchProbability(1,2))
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taken = true;
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if (BrTarget.isMBB()) {
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const MachineBasicBlock *Dst = BrTarget.getMBB();
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Taken = MBPI->getEdgeProbability(Src, Dst) >= OneHalf;
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} else {
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// The branch target is not a basic block (most likely a function).
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// Since BPI only gives probabilities for targets that are basic blocks,
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// try to identify another target of this branch (potentially a fall-
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// -through) and check the probability of that target.
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//
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// The only handled branch combinations are:
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// - one conditional branch,
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// - one conditional branch followed by one unconditional branch.
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// Otherwise, assume not-taken.
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assert(MI.isConditionalBranch());
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const MachineBasicBlock &B = *MI.getParent();
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bool SawCond = false, Bad = false;
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for (const MachineInstr &I : B) {
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if (!I.isBranch())
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continue;
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if (I.isConditionalBranch()) {
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SawCond = true;
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if (&I != &MI) {
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Bad = true;
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break;
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}
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}
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if (I.isUnconditionalBranch() && !SawCond) {
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Bad = true;
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break;
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}
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}
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if (!Bad) {
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MachineBasicBlock::const_instr_iterator It(MI);
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MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
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if (NextIt == B.instr_end()) {
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// If this branch is the last, look for the fall-through block.
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for (const MachineBasicBlock *SB : B.successors()) {
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if (!B.isLayoutSuccessor(SB))
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continue;
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Taken = MBPI->getEdgeProbability(Src, SB) < OneHalf;
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break;
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}
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} else {
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assert(NextIt->isUnconditionalBranch());
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// Find the first MBB operand and assume it's the target.
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const MachineBasicBlock *BT = nullptr;
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for (const MachineOperand &Op : NextIt->operands()) {
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if (!Op.isMBB())
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continue;
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BT = Op.getMBB();
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break;
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}
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Taken = BT && MBPI->getEdgeProbability(Src, BT) < OneHalf;
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}
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} // if (!Bad)
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}
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// The Taken flag should be set to something reasonable by this point.
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switch (MI.getOpcode()) {
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case Hexagon::J2_jumpt:
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return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
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return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
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case Hexagon::J2_jumpf:
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return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
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return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
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default:
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llvm_unreachable("Unexpected jump instruction.");
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@ -3493,20 +3548,19 @@ int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,
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// Return .new predicate version for an instruction.
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int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
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const MachineBranchProbabilityInfo *MBPI) const {
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int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
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if (NewOpcode >= 0) // Valid predicate new instruction
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return NewOpcode;
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switch (MI.getOpcode()) {
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// Condtional Jumps
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case Hexagon::J2_jumpt:
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case Hexagon::J2_jumpf:
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return getDotNewPredJumpOp(MI, MBPI);
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default:
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assert(0 && "Unknown .new type");
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}
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return 0;
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int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
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if (NewOpcode >= 0)
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return NewOpcode;
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dbgs() << "Cannot convert to .new: " << getName(MI.getOpcode()) << '\n';
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llvm_unreachable(nullptr);
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}
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int HexagonInstrInfo::getDotOldOp(const int opc) const {
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@ -0,0 +1,44 @@
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; RUN: llc -march=hexagon -disable-block-placement < %s | FileCheck %s
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; Check that the branch to the block b10 is marked as taken (i.e. ":t").
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; CHECK-LABEL: foo
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; CHECK: if ({{.*}}) jump:t .LBB0_[[LAB:[0-9]+]]
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; CHECK: [[LAB]]:
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; CHECK: add({{.*}},#65)
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target triple = "hexagon"
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define i32 @foo(i32 %a0) local_unnamed_addr #0 {
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b1:
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%v2 = icmp eq i32 %a0, 0
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br i1 %v2, label %b3, label %b10, !prof !0
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b3: ; preds = %b1
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br label %b4
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b4: ; preds = %b4, %b3
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%v5 = phi i32 [ %v6, %b4 ], [ 0, %b3 ]
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%v6 = add nuw nsw i32 %v5, 1
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%v7 = mul nuw nsw i32 %v5, 67
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%v8 = tail call i32 @bar(i32 %v7) #0
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%v9 = icmp eq i32 %v6, 10
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br i1 %v9, label %b13, label %b4
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b10: ; preds = %b1
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%v11 = add nsw i32 %a0, 65
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%v12 = tail call i32 @bar(i32 %v11) #0
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br label %b14
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b13: ; preds = %b4
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br label %b14
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b14: ; preds = %b13, %b10
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%v15 = phi i32 [ %v12, %b10 ], [ 0, %b13 ]
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ret i32 %v15
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}
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declare i32 @bar(i32) local_unnamed_addr #0
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" }
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!0 = !{!"branch_weights", i32 1, i32 2000}
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