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[RISCV] Bump rvv-related extensions from 0.10 to 1.0 

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D112987
This commit is contained in:
eopXD 2022-01-20 02:24:10 -08:00
parent 7f0f4cab18
commit e6de53b4de
5 changed files with 98 additions and 98 deletions
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12
clang/test/Driver/riscv-arch.c
View File

@ -412,20 +412,20 @@
// RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
// RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension 'v'
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvl32b0p10 -### %s -c 2>&1 | \
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-NOFLAG %s
// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32iv0p10_zvl32b0p10'
// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32iv1p0_zvl32b1p0'
// RV32-EXPERIMENTAL-ZVL-NOFLAG: requires '-menable-experimental-extensions'
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvl32b0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-BADVERS %s
// RV32-EXPERIMENTAL-ZVL-BADVERS: error: invalid arch name 'rv32iv0p10_zvl32b0p1'
// RV32-EXPERIMENTAL-ZVL-BADVERS: error: invalid arch name 'rv32iv1p0_zvl32b0p1'
// RV32-EXPERIMENTAL-ZVL-BADVERS: unsupported version number 0.1 for experimental extension
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvl32b0p10 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-GOODVERS %s
// RV32-EXPERIMENTAL-ZVL-GOODVERS: "-target-feature" "+experimental-zvl32b"

64
clang/test/Preprocessor/riscv-target-features.c
View File

@ -212,12 +212,12 @@
// CHECK-ZBT-EXT: __riscv_zbt 93000{{$}}
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv32iv0p10 -x c -E -dM %s \
// RUN: -march=rv32iv1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64iv0p10 -x c -E -dM %s \
// RUN: -march=rv64iv1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
// CHECK-V-EXT: __riscv_v 10000{{$}}
// CHECK-V-EXT: __riscv_v 1000000{{$}}
// CHECK-V-EXT: __riscv_vector 1
// RUN: %clang -target riscv32-unknown-linux-gnu \
@ -237,107 +237,107 @@
// CHECK-ZFH-EXT: __riscv_zfh 1000000{{$}}
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64iv0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64iv1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-V-MINVLEN %s
// CHECK-V-MINVLEN: __riscv_v_elen 64
// CHECK-V-MINVLEN: __riscv_v_elen_fp 64
// CHECK-V-MINVLEN: __riscv_v_min_vlen 128
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64iv0p10_zvl256b0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64iv1p0_zvl256b1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVL256b %s
// CHECK-ZVL256b: __riscv_v_min_vlen 256
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64iv0p10_zvl512b0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64iv1p0_zvl512b1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVL512b %s
// CHECK-ZVL512b: __riscv_v_min_vlen 512
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64iv0p10_zvl1024b0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64iv1p0_zvl1024b1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVL1024b %s
// CHECK-ZVL1024b: __riscv_v_min_vlen 1024
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64iv0p10_zvl2048b0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64iv1p0_zvl2048b1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVL2048b %s
// CHECK-ZVL2048b: __riscv_v_min_vlen 2048
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64iv0p10_zvl4096b0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64iv1p0_zvl4096b1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVL4096b %s
// CHECK-ZVL4096b: __riscv_v_min_vlen 4096
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64iv0p10_zvl8192b0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64iv1p0_zvl8192b1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVL8192b %s
// CHECK-ZVL8192b: __riscv_v_min_vlen 8192
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64iv0p10_zvl16384b0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64iv1p0_zvl16384b1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVL16384b %s
// CHECK-ZVL16384b: __riscv_v_min_vlen 16384
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64iv0p10_zvl32768b0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64iv1p0_zvl32768b1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVL32768b %s
// CHECK-ZVL32768b: __riscv_v_min_vlen 32768
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64iv0p10_zvl65536b0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64iv1p0_zvl65536b1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVL65536b %s
// CHECK-ZVL65536b: __riscv_v_min_vlen 65536
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64ifdzve64d0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64ifdzve64d1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVE64D-EXT %s
// CHECK-ZVE64D-EXT: __riscv_v_elen 64
// CHECK-ZVE64D-EXT: __riscv_v_elen_fp 64
// CHECK-ZVE64D-EXT: __riscv_v_min_vlen 64
// CHECK-ZVE64D-EXT: __riscv_vector 1
// CHECK-ZVE64D-EXT: __riscv_zve32f 10000{{$}}
// CHECK-ZVE64D-EXT: __riscv_zve32x 10000{{$}}
// CHECK-ZVE64D-EXT: __riscv_zve64d 10000{{$}}
// CHECK-ZVE64D-EXT: __riscv_zve64f 10000{{$}}
// CHECK-ZVE64D-EXT: __riscv_zve64x 10000{{$}}
// CHECK-ZVE64D-EXT: __riscv_zve32f 1000000{{$}}
// CHECK-ZVE64D-EXT: __riscv_zve32x 1000000{{$}}
// CHECK-ZVE64D-EXT: __riscv_zve64d 1000000{{$}}
// CHECK-ZVE64D-EXT: __riscv_zve64f 1000000{{$}}
// CHECK-ZVE64D-EXT: __riscv_zve64x 1000000{{$}}
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64ifzve64f0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64ifzve64f1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVE64F-EXT %s
// CHECK-ZVE64F-EXT: __riscv_v_elen 64
// CHECK-ZVE64F-EXT: __riscv_v_elen_fp 32
// CHECK-ZVE64F-EXT: __riscv_v_min_vlen 64
// CHECK-ZVE64F-EXT: __riscv_vector 1
// CHECK-ZVE64F-EXT: __riscv_zve32f 10000{{$}}
// CHECK-ZVE64F-EXT: __riscv_zve32x 10000{{$}}
// CHECK-ZVE64F-EXT: __riscv_zve64f 10000{{$}}
// CHECK-ZVE64F-EXT: __riscv_zve64x 10000{{$}}
// CHECK-ZVE64F-EXT: __riscv_zve32f 1000000{{$}}
// CHECK-ZVE64F-EXT: __riscv_zve32x 1000000{{$}}
// CHECK-ZVE64F-EXT: __riscv_zve64f 1000000{{$}}
// CHECK-ZVE64F-EXT: __riscv_zve64x 1000000{{$}}
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64izve64x0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64izve64x1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVE64X-EXT %s
// CHECK-ZVE64X-EXT: __riscv_v_elen 64
// CHECK-ZVE64X-EXT: __riscv_v_elen_fp 0
// CHECK-ZVE64X-EXT: __riscv_v_min_vlen 64
// CHECK-ZVE64X-EXT: __riscv_vector 1
// CHECK-ZVE64X-EXT: __riscv_zve32x 10000{{$}}
// CHECK-ZVE64X-EXT: __riscv_zve64x 10000{{$}}
// CHECK-ZVE64X-EXT: __riscv_zve32x 1000000{{$}}
// CHECK-ZVE64X-EXT: __riscv_zve64x 1000000{{$}}
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64ifzve32f0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64ifzve32f1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVE32F-EXT %s
// CHECK-ZVE32F-EXT: __riscv_v_elen 32
// CHECK-ZVE32F-EXT: __riscv_v_elen_fp 32
// CHECK-ZVE32F-EXT: __riscv_v_min_vlen 32
// CHECK-ZVE32F-EXT: __riscv_vector 1
// CHECK-ZVE32F-EXT: __riscv_zve32f 10000{{$}}
// CHECK-ZVE32F-EXT: __riscv_zve32x 10000{{$}}
// CHECK-ZVE32F-EXT: __riscv_zve32f 1000000{{$}}
// CHECK-ZVE32F-EXT: __riscv_zve32x 1000000{{$}}
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64izve32x0p10 -x c -E -dM %s -o - \
// RUN: -march=rv64izve32x1p0 -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-ZVE32X-EXT %s
// CHECK-ZVE32X-EXT: __riscv_v_elen 32
// CHECK-ZVE32X-EXT: __riscv_v_elen_fp 0
// CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
// CHECK-ZVE32X-EXT: __riscv_vector 1
// CHECK-ZVE32X-EXT: __riscv_zve32x 10000{{$}}
// CHECK-ZVE32X-EXT: __riscv_zve32x 1000000{{$}}

36
llvm/lib/Support/RISCVISAInfo.cpp
View File

@ -60,7 +60,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
};
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"v", RISCVExtensionVersion{0, 10}},
{"v", RISCVExtensionVersion{1, 0}},
{"zbe", RISCVExtensionVersion{0, 93}},
{"zbf", RISCVExtensionVersion{0, 93}},
{"zbm", RISCVExtensionVersion{0, 93}},
@ -68,23 +68,23 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zbr", RISCVExtensionVersion{0, 93}},
{"zbt", RISCVExtensionVersion{0, 93}},
{"zvl32b", RISCVExtensionVersion{0, 10}},
{"zvl64b", RISCVExtensionVersion{0, 10}},
{"zvl128b", RISCVExtensionVersion{0, 10}},
{"zvl256b", RISCVExtensionVersion{0, 10}},
{"zvl512b", RISCVExtensionVersion{0, 10}},
{"zvl1024b", RISCVExtensionVersion{0, 10}},
{"zvl2048b", RISCVExtensionVersion{0, 10}},
{"zvl4096b", RISCVExtensionVersion{0, 10}},
{"zvl8192b", RISCVExtensionVersion{0, 10}},
{"zvl16384b", RISCVExtensionVersion{0, 10}},
{"zvl32768b", RISCVExtensionVersion{0, 10}},
{"zvl65536b", RISCVExtensionVersion{0, 10}},
{"zve32x", RISCVExtensionVersion{0, 10}},
{"zve32f", RISCVExtensionVersion{0, 10}},
{"zve64x", RISCVExtensionVersion{0, 10}},
{"zve64f", RISCVExtensionVersion{0, 10}},
{"zve64d", RISCVExtensionVersion{0, 10}},
{"zvl32b", RISCVExtensionVersion{1, 0}},
{"zvl64b", RISCVExtensionVersion{1, 0}},
{"zvl128b", RISCVExtensionVersion{1, 0}},
{"zvl256b", RISCVExtensionVersion{1, 0}},
{"zvl512b", RISCVExtensionVersion{1, 0}},
{"zvl1024b", RISCVExtensionVersion{1, 0}},
{"zvl2048b", RISCVExtensionVersion{1, 0}},
{"zvl4096b", RISCVExtensionVersion{1, 0}},
{"zvl8192b", RISCVExtensionVersion{1, 0}},
{"zvl16384b", RISCVExtensionVersion{1, 0}},
{"zvl32768b", RISCVExtensionVersion{1, 0}},
{"zvl65536b", RISCVExtensionVersion{1, 0}},
{"zve32x", RISCVExtensionVersion{1, 0}},
{"zve32f", RISCVExtensionVersion{1, 0}},
{"zve64x", RISCVExtensionVersion{1, 0}},
{"zve64f", RISCVExtensionVersion{1, 0}},
{"zve64d", RISCVExtensionVersion{1, 0}},
};
static bool stripExperimentalPrefix(StringRef &Ext) {

8
llvm/test/CodeGen/RISCV/attributes.ll
View File

@ -59,8 +59,8 @@
; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zfhmin1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
@ -80,8 +80,8 @@
; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zfhmin1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"
define i32 @addi(i32 %a) {

76
llvm/test/MC/RISCV/attribute-arch.s
View File

@ -35,8 +35,8 @@
## Experimental extensions require version string to be explicitly specified
.attribute arch, "rv32iv0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32izba1p0"
# CHECK: attribute 5, "rv32i2p0_zba1p0"
@ -74,59 +74,59 @@
.attribute arch, "rv32ifzfh1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
.attribute arch, "rv32iv0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32iv0p10zvl32b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv1p0zvl32b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32iv0p10zvl64b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv1p0zvl64b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32iv0p10zvl128b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv1p0zvl128b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32iv0p10zvl256b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv1p0zvl256b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32iv0p10zvl512b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
.attribute arch, "rv32iv1p0zvl512b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
.attribute arch, "rv32iv0p10zvl1024b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
.attribute arch, "rv32iv1p0zvl1024b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
.attribute arch, "rv32iv0p10zvl2048b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
.attribute arch, "rv32iv1p0zvl2048b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
.attribute arch, "rv32iv0p10zvl4096b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10"
.attribute arch, "rv32iv1p0zvl4096b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
.attribute arch, "rv32iv0p10zvl8192b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
.attribute arch, "rv32iv1p0zvl8192b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
.attribute arch, "rv32iv0p10zvl16384b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
.attribute arch, "rv32iv1p0zvl16384b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
.attribute arch, "rv32iv0p10zvl32768b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
.attribute arch, "rv32iv1p0zvl32768b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
.attribute arch, "rv32iv0p10zvl65536b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10"
.attribute arch, "rv32iv1p0zvl65536b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0"
.attribute arch, "rv32i_zve32x0p10"
# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zvl32b0p10"
.attribute arch, "rv32i_zve32x1p0"
# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvl32b1p0"
.attribute arch, "rv32if_zve32f0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zvl32b0p10"
.attribute arch, "rv32if_zve32f1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zvl32b1p0"
.attribute arch, "rv32i_zve64x0p10"
# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zve64x0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32i_zve64x1p0"
# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32if_zve64f0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32if_zve64f1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32ifd_zve64d0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32ifd_zve64d1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zbkb1p0"
# CHECK: attribute 5, "rv32i2p0_zbkb1p0"