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[TableGen] Use range-based for loops (NFC) 

Use range-based for loops in TableGen.

Reviewed By: Paul-C-Anagnostopoulos

Differential Revision: https://reviews.llvm.org/D101994
This commit is contained in:
Coelacanthus 2021-05-06 18:36:52 +08:00
parent e388b9399b
commit e6cf3d6441
No known key found for this signature in database
GPG Key ID: 1F62B42D0D2AE4B6
13 changed files with 214 additions and 263 deletions
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10
llvm/utils/TableGen/AsmMatcherEmitter.cpp
View File

@ -1322,9 +1322,8 @@ buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
}
// Populate the map for individual registers.
for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
ie = RegisterMap.end(); it != ie; ++it)
RegisterClasses[it->first] = RegisterSetClasses[it->second];
for (auto &It : RegisterMap)
RegisterClasses[It.first] = RegisterSetClasses[It.second];
// Name the register classes which correspond to singleton registers.
for (Record *Rec : SingletonRegisters) {
@ -1529,9 +1528,8 @@ void AsmMatcherInfo::buildInfo() {
// matchables.
std::vector<Record*> AllInstAliases =
Records.getAllDerivedDefinitions("InstAlias");
for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
auto Alias = std::make_unique<CodeGenInstAlias>(AllInstAliases[i],
Target);
for (Record *InstAlias : AllInstAliases) {
auto Alias = std::make_unique<CodeGenInstAlias>(InstAlias, Target);
// If the tblgen -match-prefix option is specified (for tblgen hackers),
// filter the set of instruction aliases we consider, based on the target

3
llvm/utils/TableGen/AsmWriterEmitter.cpp
View File

@ -994,8 +994,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
});
}
for (auto I = ReqFeatures.cbegin(); I != ReqFeatures.cend(); I++) {
Record *R = *I;
for (Record *const R : ReqFeatures) {
const DagInit *D = R->getValueAsDag("AssemblerCondDag");
std::string CombineType = D->getOperator()->getAsString();
if (CombineType != "any_of" && CombineType != "all_of")

92
llvm/utils/TableGen/CodeGenRegisters.cpp
View File

@ -311,18 +311,17 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
// Look at the possible compositions of Idx.
// They may not all be supported by SR.
for (CodeGenSubRegIndex::CompMap::const_iterator I = Comps.begin(),
E = Comps.end(); I != E; ++I) {
SubRegMap::const_iterator SRI = Map.find(I->first);
for (auto Comp : Comps) {
SubRegMap::const_iterator SRI = Map.find(Comp.first);
if (SRI == Map.end())
continue; // Idx + I->first doesn't exist in SR.
// Add I->second as a name for the subreg SRI->second, assuming it is
// orphaned, and the name isn't already used for something else.
if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
if (SubRegs.count(Comp.second) || !Orphans.erase(SRI->second))
continue;
// We found a new name for the orphaned sub-register.
SubRegs.insert(std::make_pair(I->second, SRI->second));
Indices.push_back(I->second);
SubRegs.insert(std::make_pair(Comp.second, SRI->second));
Indices.push_back(Comp.second);
}
}
@ -528,13 +527,13 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) {
CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first;
CodeGenRegister *NewSubReg = NewSubRegs[i].second;
for (SubRegMap::const_iterator SI = NewSubReg->SubRegs.begin(),
SE = NewSubReg->SubRegs.end(); SI != SE; ++SI) {
CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second);
for (auto SubReg : NewSubReg->SubRegs) {
CodeGenSubRegIndex *SubIdx = getSubRegIndex(SubReg.second);
if (!SubIdx)
PrintFatalError(TheDef->getLoc(), "No SubRegIndex for " +
SI->second->getName() + " in " + getName());
NewIdx->addComposite(SI->first, SubIdx);
SubReg.second->getName() +
" in " + getName());
NewIdx->addComposite(SubReg.first, SubIdx);
}
}
}
@ -547,24 +546,23 @@ void CodeGenRegister::computeSuperRegs(CodeGenRegBank &RegBank) {
// Make sure all sub-registers have been visited first, so the super-reg
// lists will be topologically ordered.
for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
I != E; ++I)
I->second->computeSuperRegs(RegBank);
for (auto SubReg : SubRegs)
SubReg.second->computeSuperRegs(RegBank);
// Now add this as a super-register on all sub-registers.
// Also compute the TopoSigId in post-order.
TopoSigId Id;
for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
I != E; ++I) {
for (auto SubReg : SubRegs) {
// Topological signature computed from SubIdx, TopoId(SubReg).
// Loops and idempotent indices have TopoSig = ~0u.
Id.push_back(I->first->EnumValue);
Id.push_back(I->second->TopoSig);
Id.push_back(SubReg.first->EnumValue);
Id.push_back(SubReg.second->TopoSig);
// Don't add duplicate entries.
if (!I->second->SuperRegs.empty() && I->second->SuperRegs.back() == this)
if (!SubReg.second->SuperRegs.empty() &&
SubReg.second->SuperRegs.back() == this)
continue;
I->second->SuperRegs.push_back(this);
SubReg.second->SuperRegs.push_back(this);
}
TopoSig = RegBank.getTopoSig(Id);
}
@ -579,17 +577,15 @@ CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
SR->addSubRegsPreOrder(OSet, RegBank);
}
// Add any secondary sub-registers that weren't part of the explicit tree.
for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
I != E; ++I)
OSet.insert(I->second);
for (auto SubReg : SubRegs)
OSet.insert(SubReg.second);
}
// Get the sum of this register's unit weights.
unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const {
unsigned Weight = 0;
for (RegUnitList::iterator I = RegUnits.begin(), E = RegUnits.end();
I != E; ++I) {
Weight += RegBank.getRegUnit(*I).Weight;
for (unsigned RegUnit : RegUnits) {
Weight += RegBank.getRegUnit(RegUnit).Weight;
}
return Weight;
}
@ -1395,19 +1391,17 @@ void CodeGenRegBank::computeComposites() {
TopoSigs.set(Reg1.getTopoSig());
const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs();
for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
e1 = SRM1.end(); i1 != e1; ++i1) {
CodeGenSubRegIndex *Idx1 = i1->first;
CodeGenRegister *Reg2 = i1->second;
for (auto I1 : SRM1) {
CodeGenSubRegIndex *Idx1 = I1.first;
CodeGenRegister *Reg2 = I1.second;
// Ignore identity compositions.
if (&Reg1 == Reg2)
continue;
const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
// Try composing Idx1 with another SubRegIndex.
for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
e2 = SRM2.end(); i2 != e2; ++i2) {
CodeGenSubRegIndex *Idx2 = i2->first;
CodeGenRegister *Reg3 = i2->second;
for (auto I2 : SRM2) {
CodeGenSubRegIndex *Idx2 = I2.first;
CodeGenRegister *Reg3 = I2.second;
// Ignore identity compositions.
if (Reg2 == Reg3)
continue;
@ -1727,13 +1721,12 @@ static bool normalizeWeight(CodeGenRegister *Reg,
bool Changed = false;
const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(),
SRE = SRM.end(); SRI != SRE; ++SRI) {
if (SRI->second == Reg)
for (auto SRI : SRM) {
if (SRI.second == Reg)
continue; // self-cycles happen
Changed |= normalizeWeight(SRI->second, UberSets, RegSets,
NormalRegs, NormalUnits, RegBank);
Changed |= normalizeWeight(SRI.second, UberSets, RegSets, NormalRegs,
NormalUnits, RegBank);
}
// Postorder register normalization.
@ -2063,15 +2056,14 @@ void CodeGenRegBank::computeRegUnitLaneMasks() {
// Iterate through SubRegisters.
typedef CodeGenRegister::SubRegMap SubRegMap;
const SubRegMap &SubRegs = Register.getSubRegs();
for (SubRegMap::const_iterator S = SubRegs.begin(),
SE = SubRegs.end(); S != SE; ++S) {
CodeGenRegister *SubReg = S->second;
for (auto S : SubRegs) {
CodeGenRegister *SubReg = S.second;
// Ignore non-leaf subregisters, their lane masks are fully covered by
// the leaf subregisters anyway.
if (!SubReg->getSubRegs().empty())
continue;
CodeGenSubRegIndex *SubRegIndex = S->first;
const CodeGenRegister *SubRegister = S->second;
CodeGenSubRegIndex *SubRegIndex = S.first;
const CodeGenRegister *SubRegister = S.second;
LaneBitmask LaneMask = SubRegIndex->LaneMask;
// Distribute LaneMask to Register Units touched.
for (unsigned SUI : SubRegister->getRegUnits()) {
@ -2193,10 +2185,9 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
if (R->Artificial)
continue;
const CodeGenRegister::SubRegMap &SRM = R->getSubRegs();
for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
E = SRM.end(); I != E; ++I) {
if (!I->first->Artificial)
SRSets[I->first].push_back(R);
for (auto I : SRM) {
if (!I.first->Artificial)
SRSets[I.first].push_back(R);
}
}
@ -2421,9 +2412,8 @@ BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
// This new super-register is covered by its sub-registers.
bool AllSubsInSet = true;
const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs();
for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
E = SRM.end(); I != E; ++I)
if (!Set.count(I->second)) {
for (auto I : SRM)
if (!Set.count(I.second)) {
AllSubsInSet = false;
break;
}

129
llvm/utils/TableGen/CodeGenSchedule.cpp
View File

@ -921,11 +921,10 @@ void CodeGenSchedModels::collectSchedClasses() {
ProcIndices.push_back(0);
LLVM_DEBUG({
dbgs() << "SchedRW machine model for " << InstName;
for (IdxIter WI = SC.Writes.begin(), WE = SC.Writes.end(); WI != WE;
++WI)
dbgs() << " " << SchedWrites[*WI].Name;
for (IdxIter RI = SC.Reads.begin(), RE = SC.Reads.end(); RI != RE; ++RI)
dbgs() << " " << SchedReads[*RI].Name;
for (unsigned int Write : SC.Writes)
dbgs() << " " << SchedWrites[Write].Name;
for (unsigned int Read : SC.Reads)
dbgs() << " " << SchedReads[Read].Name;
dbgs() << '\n';
});
}
@ -1557,12 +1556,11 @@ pushVariant(const TransVariant &VInfo, bool IsRead) {
// sequence (add to the current operand's sequence).
SmallVectorImpl<unsigned> &Seq = RWSequences.back();
IdxVec ExpandedRWs;
for (IdxIter RWI = SelectedRWs.begin(), RWE = SelectedRWs.end();
RWI != RWE; ++RWI) {
for (unsigned int SelectedRW : SelectedRWs) {
if (IsRead)
ExpandedRWs.push_back(*RWI);
ExpandedRWs.push_back(SelectedRW);
else
SchedModels.expandRWSequence(*RWI, ExpandedRWs, IsRead);
SchedModels.expandRWSequence(SelectedRW, ExpandedRWs, IsRead);
}
llvm::append_range(Seq, ExpandedRWs);
}
@ -1576,9 +1574,8 @@ bool PredTransitions::substituteVariantOperand(
const SmallVectorImpl<unsigned> &RWSeq, bool IsRead, unsigned StartIdx) {
bool Subst = false;
// Visit each original RW within the current sequence.
for (SmallVectorImpl<unsigned>::const_iterator
RWI = RWSeq.begin(), RWE = RWSeq.end(); RWI != RWE; ++RWI) {
const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(*RWI, IsRead);
for (unsigned int RWI : RWSeq) {
const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(RWI, IsRead);
// Push this RW on all partial PredTransitions or distribute variants.
// New PredTransitions may be pushed within this loop which should not be
// revisited (TransEnd must be loop invariant).
@ -1593,9 +1590,9 @@ bool PredTransitions::substituteVariantOperand(
pushVariant(IV, IsRead);
if (IntersectingVariants.empty()) {
if (IsRead)
TransVec[TransIdx].ReadSequences.back().push_back(*RWI);
TransVec[TransIdx].ReadSequences.back().push_back(RWI);
else
TransVec[TransIdx].WriteSequences.back().push_back(*RWI);
TransVec[TransIdx].WriteSequences.back().push_back(RWI);
continue;
} else {
Subst = true;
@ -1620,26 +1617,23 @@ bool PredTransitions::substituteVariants(const PredTransition &Trans) {
TransVec.emplace_back(Trans.PredTerm, Trans.ProcIndex);
// Visit each original write sequence.
for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
WSI = Trans.WriteSequences.begin(), WSE = Trans.WriteSequences.end();
WSI != WSE; ++WSI) {
for (const auto &WriteSequence : Trans.WriteSequences) {
// Push a new (empty) write sequence onto all partial Transitions.
for (std::vector<PredTransition>::iterator I =
TransVec.begin() + StartIdx, E = TransVec.end(); I != E; ++I) {
I->WriteSequences.emplace_back();
}
Subst |= substituteVariantOperand(*WSI, /*IsRead=*/false, StartIdx);
Subst |=
substituteVariantOperand(WriteSequence, /*IsRead=*/false, StartIdx);
}
// Visit each original read sequence.
for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
RSI = Trans.ReadSequences.begin(), RSE = Trans.ReadSequences.end();
RSI != RSE; ++RSI) {
for (const auto &ReadSequence : Trans.ReadSequences) {
// Push a new (empty) read sequence onto all partial Transitions.
for (std::vector<PredTransition>::iterator I =
TransVec.begin() + StartIdx, E = TransVec.end(); I != E; ++I) {
I->ReadSequences.emplace_back();
}
Subst |= substituteVariantOperand(*RSI, /*IsRead=*/true, StartIdx);
Subst |= substituteVariantOperand(ReadSequence, /*IsRead=*/true, StartIdx);
}
return Subst;
}
@ -1676,33 +1670,32 @@ static void inferFromTransitions(ArrayRef<PredTransition> LastTransitions,
CodeGenSchedModels &SchedModels) {
// For each PredTransition, create a new CodeGenSchedTransition, which usually
// requires creating a new SchedClass.
for (ArrayRef<PredTransition>::iterator
I = LastTransitions.begin(), E = LastTransitions.end(); I != E; ++I) {
for (const auto &LastTransition : LastTransitions) {
// Variant expansion (substituteVariants) may create unconditional
// transitions. We don't need to build sched classes for them.
if (I->PredTerm.empty())
if (LastTransition.PredTerm.empty())
continue;
IdxVec OperWritesVariant, OperReadsVariant;
addSequences(SchedModels, I->WriteSequences, OperWritesVariant, false);
addSequences(SchedModels, I->ReadSequences, OperReadsVariant, true);
addSequences(SchedModels, LastTransition.WriteSequences, OperWritesVariant,
false);
addSequences(SchedModels, LastTransition.ReadSequences, OperReadsVariant,
true);
CodeGenSchedTransition SCTrans;
// Transition should not contain processor indices already assigned to
// InstRWs in this scheduling class.
const CodeGenSchedClass &FromSC = SchedModels.getSchedClass(FromClassIdx);
if (FromSC.InstRWProcIndices.count(I->ProcIndex))
if (FromSC.InstRWProcIndices.count(LastTransition.ProcIndex))
continue;
SCTrans.ProcIndex = I->ProcIndex;
SCTrans.ProcIndex = LastTransition.ProcIndex;
SCTrans.ToClassIdx =
SchedModels.addSchedClass(/*ItinClassDef=*/nullptr, OperWritesVariant,
OperReadsVariant, I->ProcIndex);
OperReadsVariant, LastTransition.ProcIndex);
// The final PredTerm is unique set of predicates guarding the transition.
RecVec Preds;
transform(I->PredTerm, std::back_inserter(Preds),
[](const PredCheck &P) {
return P.Predicate;
});
transform(LastTransition.PredTerm, std::back_inserter(Preds),
[](const PredCheck &P) { return P.Predicate; });
Preds.erase(std::unique(Preds.begin(), Preds.end()), Preds.end());
dumpTransition(SchedModels, FromSC, SCTrans, Preds);
SCTrans.PredTerm = std::move(Preds);
@ -1791,11 +1784,10 @@ void CodeGenSchedModels::inferFromRW(ArrayRef<unsigned> OperWrites,
// Check if any processor resource group contains all resource records in
// SubUnits.
bool CodeGenSchedModels::hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM) {
for (unsigned i = 0, e = PM.ProcResourceDefs.size(); i < e; ++i) {
if (!PM.ProcResourceDefs[i]->isSubClassOf("ProcResGroup"))
for (Record *ProcResourceDef : PM.ProcResourceDefs) {
if (!ProcResourceDef->isSubClassOf("ProcResGroup"))
continue;
RecVec SuperUnits =
PM.ProcResourceDefs[i]->getValueAsListOfDefs("Resources");
RecVec SuperUnits = ProcResourceDef->getValueAsListOfDefs("Resources");
RecIter RI = SubUnits.begin(), RE = SubUnits.end();
for ( ; RI != RE; ++RI) {
if (!is_contained(SuperUnits, *RI)) {
@ -1951,27 +1943,26 @@ void CodeGenSchedModels::collectProcResources() {
llvm::sort(PM.ReadAdvanceDefs, LessRecord());
llvm::sort(PM.ProcResourceDefs, LessRecord());
LLVM_DEBUG(
PM.dump();
dbgs() << "WriteResDefs: "; for (RecIter RI = PM.WriteResDefs.begin(),
RE = PM.WriteResDefs.end();
RI != RE; ++RI) {
if ((*RI)->isSubClassOf("WriteRes"))
dbgs() << (*RI)->getValueAsDef("WriteType")->getName() << " ";
PM.dump(); dbgs() << "WriteResDefs: "; for (auto WriteResDef
: PM.WriteResDefs) {
if (WriteResDef->isSubClassOf("WriteRes"))
dbgs() << WriteResDef->getValueAsDef("WriteType")->getName() << " ";
else
dbgs() << (*RI)->getName() << " ";
dbgs() << WriteResDef->getName() << " ";
} dbgs() << "\nReadAdvanceDefs: ";
for (RecIter RI = PM.ReadAdvanceDefs.begin(),
RE = PM.ReadAdvanceDefs.end();
RI != RE; ++RI) {
if ((*RI)->isSubClassOf("ReadAdvance"))
dbgs() << (*RI)->getValueAsDef("ReadType")->getName() << " ";
for (Record *ReadAdvanceDef
: PM.ReadAdvanceDefs) {
if (ReadAdvanceDef->isSubClassOf("ReadAdvance"))
dbgs() << ReadAdvanceDef->getValueAsDef("ReadType")->getName()
<< " ";
else
dbgs() << (*RI)->getName() << " ";
dbgs() << ReadAdvanceDef->getName() << " ";
} dbgs()
<< "\nProcResourceDefs: ";
for (RecIter RI = PM.ProcResourceDefs.begin(),
RE = PM.ProcResourceDefs.end();
RI != RE; ++RI) { dbgs() << (*RI)->getName() << " "; } dbgs()
for (Record *ProcResourceDef
: PM.ProcResourceDefs) {
dbgs() << ProcResourceDef->getName() << " ";
} dbgs()
<< '\n');
verifyProcResourceGroups(PM);
}
@ -2073,23 +2064,20 @@ void CodeGenSchedModels::collectRWResources(unsigned RWIdx, bool IsRead,
addReadAdvance(SchedRW.TheDef, Idx);
}
}
for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
AI != AE; ++AI) {
for (auto *Alias : SchedRW.Aliases) {
IdxVec AliasProcIndices;
if ((*AI)->getValueInit("SchedModel")->isComplete()) {
if (Alias->getValueInit("SchedModel")->isComplete()) {
AliasProcIndices.push_back(
getProcModel((*AI)->getValueAsDef("SchedModel")).Index);
}
else
getProcModel(Alias->getValueAsDef("SchedModel")).Index);
} else
AliasProcIndices = ProcIndices;
const CodeGenSchedRW &AliasRW = getSchedRW((*AI)->getValueAsDef("AliasRW"));
const CodeGenSchedRW &AliasRW = getSchedRW(Alias->getValueAsDef("AliasRW"));
assert(AliasRW.IsRead == IsRead && "cannot alias reads to writes");
IdxVec ExpandedRWs;
expandRWSequence(AliasRW.Index, ExpandedRWs, IsRead);
for (IdxIter SI = ExpandedRWs.begin(), SE = ExpandedRWs.end();
SI != SE; ++SI) {
collectRWResources(*SI, IsRead, AliasProcIndices);
for (unsigned int ExpandedRW : ExpandedRWs) {
collectRWResources(ExpandedRW, IsRead, AliasProcIndices);
}
}
}
@ -2179,9 +2167,8 @@ void CodeGenSchedModels::addWriteRes(Record *ProcWriteResDef, unsigned PIdx) {
// Visit ProcResourceKinds referenced by the newly discovered WriteRes.
RecVec ProcResDefs = ProcWriteResDef->getValueAsListOfDefs("ProcResources");
for (RecIter WritePRI = ProcResDefs.begin(), WritePRE = ProcResDefs.end();
WritePRI != WritePRE; ++WritePRI) {
addProcResource(*WritePRI, ProcModels[PIdx], ProcWriteResDef->getLoc());
for (auto *ProcResDef : ProcResDefs) {
addProcResource(ProcResDef, ProcModels[PIdx], ProcWriteResDef->getLoc());
}
}
@ -2259,16 +2246,16 @@ void CodeGenSchedClass::dump(const CodeGenSchedModels* SchedModels) const {
void PredTransitions::dump() const {
dbgs() << "Expanded Variants:\n";
for (std::vector<PredTransition>::const_iterator
TI = TransVec.begin(), TE = TransVec.end(); TI != TE; ++TI) {
for (const auto &TI : TransVec) {
dbgs() << "{";
ListSeparator LS;
for (const PredCheck &PC : TI->PredTerm)
for (const PredCheck &PC : TI.PredTerm)
dbgs() << LS << SchedModels.getSchedRW(PC.RWIdx, PC.IsRead).Name << ":"
<< PC.Predicate->getName();
dbgs() << "},\n => {";
for (SmallVectorImpl<SmallVector<unsigned, 4>>::const_iterator
WSI = TI->WriteSequences.begin(), WSE = TI->WriteSequences.end();
WSI = TI.WriteSequences.begin(),
WSE = TI.WriteSequences.end();
WSI != WSE; ++WSI) {
dbgs() << "(";
ListSeparator LS;

4
llvm/utils/TableGen/DFAPacketizerEmitter.cpp
View File

@ -157,8 +157,8 @@ int DFAPacketizerEmitter::collectAllComboFuncs(ArrayRef<Record *> ComboFuncList)
uint64_t ComboResources = ComboBit;
LLVM_DEBUG(dbgs() << " combo: " << ComboFuncName << ":0x"
<< Twine::utohexstr(ComboResources) << "\n");
for (unsigned k = 0, M = FuncList.size(); k < M; ++k) {
std::string FuncName = std::string(FuncList[k]->getName());
for (auto *K : FuncList) {
std::string FuncName = std::string(K->getName());
uint64_t FuncResources = FUNameToBitsMap[FuncName];
LLVM_DEBUG(dbgs() << " " << FuncName << ":0x"
<< Twine::utohexstr(FuncResources) << "\n");

51
llvm/utils/TableGen/FastISelEmitter.cpp
View File

@ -616,10 +616,10 @@ void FastISelMap::printImmediatePredicates(raw_ostream &OS) {
return;
OS << "\n// FastEmit Immediate Predicate functions.\n";
for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(),
E = ImmediatePredicates.end(); I != E; ++I) {
OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n";
OS << I->getImmediatePredicateCode() << "\n}\n";
for (auto ImmediatePredicate : ImmediatePredicates) {
OS << "static bool " << ImmediatePredicate.getFnName()
<< "(int64_t Imm) {\n";
OS << ImmediatePredicate.getImmediatePredicateCode() << "\n}\n";
}
OS << "\n\n";
@ -691,29 +691,25 @@ void FastISelMap::emitInstructionCode(raw_ostream &OS,
void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
// Now emit code for all the patterns that we collected.
for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
OE = SimplePatterns.end(); OI != OE; ++OI) {
const OperandsSignature &Operands = OI->first;
const OpcodeTypeRetPredMap &OTM = OI->second;
for (const auto &SimplePattern : SimplePatterns) {
const OperandsSignature &Operands = SimplePattern.first;
const OpcodeTypeRetPredMap &OTM = SimplePattern.second;
for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
I != E; ++I) {
const std::string &Opcode = I->first;
const TypeRetPredMap &TM = I->second;
for (const auto &I : OTM) {
const std::string &Opcode = I.first;
const TypeRetPredMap &TM = I.second;
OS << "// FastEmit functions for " << Opcode << ".\n";
OS << "\n";
// Emit one function for each opcode,type pair.
for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
TI != TE; ++TI) {
MVT::SimpleValueType VT = TI->first;
const RetPredMap &RM = TI->second;
for (const auto &TI : TM) {
MVT::SimpleValueType VT = TI.first;
const RetPredMap &RM = TI.second;
if (RM.size() != 1) {
for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
RI != RE; ++RI) {
MVT::SimpleValueType RetVT = RI->first;
const PredMap &PM = RI->second;
for (const auto &RI : RM) {
MVT::SimpleValueType RetVT = RI.first;
const PredMap &PM = RI.second;
OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_"
<< getLegalCName(std::string(getName(VT))) << "_"
@ -735,9 +731,8 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
OS << ", ";
Operands.PrintParameters(OS);
OS << ") {\nswitch (RetVT.SimpleTy) {\n";
for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
RI != RE; ++RI) {
MVT::SimpleValueType RetVT = RI->first;
for (const auto &RI : RM) {
MVT::SimpleValueType RetVT = RI.first;
OS << " case " << getName(RetVT) << ": return fastEmit_"
<< getLegalCName(Opcode) << "_"
<< getLegalCName(std::string(getName(VT))) << "_"
@ -779,9 +774,8 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
Operands.PrintParameters(OS);
OS << ") {\n";
OS << " switch (VT.SimpleTy) {\n";
for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
TI != TE; ++TI) {
MVT::SimpleValueType VT = TI->first;
for (const auto &TI : TM) {
MVT::SimpleValueType VT = TI.first;
std::string TypeName = std::string(getName(VT));
OS << " case " << TypeName << ": return fastEmit_"
<< getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
@ -846,9 +840,8 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
}
OS << " switch (Opcode) {\n";
for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
I != E; ++I) {
const std::string &Opcode = I->first;
for (const auto &I : OTM) {
const std::string &Opcode = I.first;
OS << " case " << Opcode << ": return fastEmit_"
<< getLegalCName(Opcode) << "_";

10
llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
View File

@ -1506,13 +1506,13 @@ bool FilterChooser::filterProcessor(bool AllowMixed, bool Greedy) {
if (AllowMixed && !Greedy) {
assert(numInstructions == 3);
for (unsigned i = 0; i < Opcodes.size(); ++i) {
for (auto Opcode : Opcodes) {
std::vector<unsigned> StartBits;
std::vector<unsigned> EndBits;
std::vector<uint64_t> FieldVals;
insn_t Insn;
insnWithID(Insn, Opcodes[i].EncodingID);
insnWithID(Insn, Opcode.EncodingID);
// Look for islands of undecoded bits of any instruction.
if (getIslands(StartBits, EndBits, FieldVals, Insn) > 0) {
@ -1774,13 +1774,13 @@ void FilterChooser::emitTableEntries(DecoderTableInfo &TableInfo) const {
dumpStack(errs(), "\t\t");
for (unsigned i = 0; i < Opcodes.size(); ++i) {
for (auto Opcode : Opcodes) {
errs() << '\t';
emitNameWithID(errs(), Opcodes[i].EncodingID);
emitNameWithID(errs(), Opcode.EncodingID);
errs() << " ";
dumpBits(
errs(),
getBitsField(*AllInstructions[Opcodes[i].EncodingID].EncodingDef, "Inst"));
getBitsField(*AllInstructions[Opcode.EncodingID].EncodingDef, "Inst"));
errs() << '\n';
}
}

11
llvm/utils/TableGen/GICombinerEmitter.cpp
View File

@ -242,13 +242,12 @@ public:
bool Progressed = false;
SmallSet<GIMatchDagEdge *, 20> EdgesToRemove;
while (!EdgesRemaining.empty()) {
for (auto EI = EdgesRemaining.begin(), EE = EdgesRemaining.end();
EI != EE; ++EI) {
if (Visited.count((*EI)->getFromMI())) {
if (Roots.count((*EI)->getToMI()))
for (auto *EI : EdgesRemaining) {
if (Visited.count(EI->getFromMI())) {
if (Roots.count(EI->getToMI()))
PrintError(TheDef.getLoc(), "One or more roots are unnecessary");
Visited.insert((*EI)->getToMI());
EdgesToRemove.insert(*EI);
Visited.insert(EI->getToMI());
EdgesToRemove.insert(EI);
Progressed = true;
}
}

4
llvm/utils/TableGen/InstrInfoEmitter.cpp
View File

@ -494,8 +494,8 @@ void InstrInfoEmitter::emitLogicalOperandSizeMappings(
}
OS << " static const unsigned SizeMap[][" << LogicalOpListSize
<< "] = {\n";
for (int r = 0, rs = LogicalOpSizeList.size(); r < rs; ++r) {
const auto &Row = *LogicalOpSizeList[r];
for (auto &R : LogicalOpSizeList) {
const auto &Row = *R;
OS << " {";
int i;
for (i = 0; i < static_cast<int>(Row.size()); ++i) {

85
llvm/utils/TableGen/IntrinsicEmitter.cpp
View File

@ -662,28 +662,27 @@ void IntrinsicEmitter::EmitAttributes(const CodeGenIntrinsicTable &Ints,
OS << " if (id != 0) {\n";
OS << " switch(IntrinsicsToAttributesMap[id - 1]) {\n";
OS << " default: llvm_unreachable(\"Invalid attribute number\");\n";
for (UniqAttrMapTy::const_iterator I = UniqAttributes.begin(),
E = UniqAttributes.end(); I != E; ++I) {
OS << " case " << I->second << ": {\n";
for (auto UniqAttribute : UniqAttributes) {
OS << " case " << UniqAttribute.second << ": {\n";
const CodeGenIntrinsic &intrinsic = *(I->first);
const CodeGenIntrinsic &Intrinsic = *(UniqAttribute.first);
// Keep track of the number of attributes we're writing out.
unsigned numAttrs = 0;
// The argument attributes are alreadys sorted by argument index.
unsigned ai = 0, ae = intrinsic.ArgumentAttributes.size();
if (ae) {
while (ai != ae) {
unsigned attrIdx = intrinsic.ArgumentAttributes[ai].Index;
unsigned Ai = 0, Ae = Intrinsic.ArgumentAttributes.size();
if (Ae) {
while (Ai != Ae) {
unsigned AttrIdx = Intrinsic.ArgumentAttributes[Ai].Index;
OS << " const Attribute::AttrKind AttrParam" << attrIdx << "[]= {";
OS << " const Attribute::AttrKind AttrParam" << AttrIdx << "[]= {";
ListSeparator LS(",");
bool AllValuesAreZero = true;
SmallVector<uint64_t, 8> Values;
do {
switch (intrinsic.ArgumentAttributes[ai].Kind) {
switch (Intrinsic.ArgumentAttributes[Ai].Kind) {
case CodeGenIntrinsic::NoCapture:
OS << LS << "Attribute::NoCapture";
break;
@ -712,17 +711,17 @@ void IntrinsicEmitter::EmitAttributes(const CodeGenIntrinsicTable &Ints,
OS << LS << "Attribute::Alignment";
break;
}
uint64_t V = intrinsic.ArgumentAttributes[ai].Value;
uint64_t V = Intrinsic.ArgumentAttributes[Ai].Value;
Values.push_back(V);
AllValuesAreZero &= (V == 0);
++ai;
} while (ai != ae && intrinsic.ArgumentAttributes[ai].Index == attrIdx);
++Ai;
} while (Ai != Ae && Intrinsic.ArgumentAttributes[Ai].Index == AttrIdx);
OS << "};\n";
// Generate attribute value array if not all attribute values are zero.
if (!AllValuesAreZero) {
OS << " const uint64_t AttrValParam" << attrIdx << "[]= {";
OS << " const uint64_t AttrValParam" << AttrIdx << "[]= {";
ListSeparator LSV(",");
for (const auto V : Values)
OS << LSV << V;
@ -730,46 +729,46 @@ void IntrinsicEmitter::EmitAttributes(const CodeGenIntrinsicTable &Ints,
}
OS << " AS[" << numAttrs++ << "] = AttributeList::get(C, "
<< attrIdx << ", AttrParam" << attrIdx;
<< AttrIdx << ", AttrParam" << AttrIdx;
if (!AllValuesAreZero)
OS << ", AttrValParam" << attrIdx;
OS << ", AttrValParam" << AttrIdx;
OS << ");\n";
}
}
if (!intrinsic.canThrow ||
(intrinsic.ModRef != CodeGenIntrinsic::ReadWriteMem &&
!intrinsic.hasSideEffects) ||
intrinsic.isNoReturn || intrinsic.isNoSync || intrinsic.isNoFree ||
intrinsic.isWillReturn || intrinsic.isCold || intrinsic.isNoDuplicate ||
intrinsic.isNoMerge || intrinsic.isConvergent ||
intrinsic.isSpeculatable) {
if (!Intrinsic.canThrow ||
(Intrinsic.ModRef != CodeGenIntrinsic::ReadWriteMem &&
!Intrinsic.hasSideEffects) ||
Intrinsic.isNoReturn || Intrinsic.isNoSync || Intrinsic.isNoFree ||
Intrinsic.isWillReturn || Intrinsic.isCold || Intrinsic.isNoDuplicate ||
Intrinsic.isNoMerge || Intrinsic.isConvergent ||
Intrinsic.isSpeculatable) {
OS << " const Attribute::AttrKind Atts[] = {";
ListSeparator LS(",");
if (!intrinsic.canThrow)
if (!Intrinsic.canThrow)
OS << LS << "Attribute::NoUnwind";
if (intrinsic.isNoReturn)
if (Intrinsic.isNoReturn)
OS << LS << "Attribute::NoReturn";
if (intrinsic.isNoSync)
if (Intrinsic.isNoSync)
OS << LS << "Attribute::NoSync";
if (intrinsic.isNoFree)
if (Intrinsic.isNoFree)
OS << LS << "Attribute::NoFree";
if (intrinsic.isWillReturn)
if (Intrinsic.isWillReturn)
OS << LS << "Attribute::WillReturn";
if (intrinsic.isCold)
if (Intrinsic.isCold)
OS << LS << "Attribute::Cold";
if (intrinsic.isNoDuplicate)
if (Intrinsic.isNoDuplicate)
OS << LS << "Attribute::NoDuplicate";
if (intrinsic.isNoMerge)
if (Intrinsic.isNoMerge)
OS << LS << "Attribute::NoMerge";
if (intrinsic.isConvergent)
if (Intrinsic.isConvergent)
OS << LS << "Attribute::Convergent";
if (intrinsic.isSpeculatable)
if (Intrinsic.isSpeculatable)
OS << LS << "Attribute::Speculatable";
switch (intrinsic.ModRef) {
switch (Intrinsic.ModRef) {
case CodeGenIntrinsic::NoMem:
if (intrinsic.hasSideEffects)
if (Intrinsic.hasSideEffects)
break;
OS << LS;
OS << "Attribute::ReadNone";
@ -906,25 +905,25 @@ void IntrinsicEmitter::EmitIntrinsicToBuiltinMap(
OS << " StringRef TargetPrefix(TargetPrefixStr);\n\n";
// Note: this could emit significantly better code if we cared.
for (BIMTy::iterator I = BuiltinMap.begin(), E = BuiltinMap.end();I != E;++I){
for (auto &I : BuiltinMap) {
OS << " ";
if (!I->first.empty())
OS << "if (TargetPrefix == \"" << I->first << "\") ";
if (!I.first.empty())
OS << "if (TargetPrefix == \"" << I.first << "\") ";
else
OS << "/* Target Independent Builtins */ ";
OS << "{\n";
// Emit the comparisons for this target prefix.
OS << " static const BuiltinEntry " << I->first << "Names[] = {\n";
for (const auto &P : I->second) {
OS << " static const BuiltinEntry " << I.first << "Names[] = {\n";
for (const auto &P : I.second) {
OS << " {Intrinsic::" << P.second << ", "
<< Table.GetOrAddStringOffset(P.first) << "}, // " << P.first << "\n";
}
OS << " };\n";
OS << " auto I = std::lower_bound(std::begin(" << I->first << "Names),\n";
OS << " std::end(" << I->first << "Names),\n";
OS << " auto I = std::lower_bound(std::begin(" << I.first << "Names),\n";
OS << " std::end(" << I.first << "Names),\n";
OS << " BuiltinNameStr);\n";
OS << " if (I != std::end(" << I->first << "Names) &&\n";
OS << " if (I != std::end(" << I.first << "Names) &&\n";
OS << " I->getName() == BuiltinNameStr)\n";
OS << " return I->IntrinID;\n";
OS << " }\n";

4
llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
View File

@ -273,8 +273,8 @@ static bool verifyDagOpCount(CodeGenInstruction &Inst, DagInit *Dag,
// The Instruction might have tied operands so the Dag might have
// a fewer operand count.
unsigned RealCount = Inst.Operands.size();
for (unsigned i = 0; i < Inst.Operands.size(); i++)
if (Inst.Operands[i].getTiedRegister() != -1)
for (const auto &Operand : Inst.Operands)
if (Operand.getTiedRegister() != -1)
--RealCount;
if (Dag->getNumArgs() != RealCount)

41
llvm/utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -305,9 +305,8 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) {
ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
PSets[i].reserve(PSetIDs.size());
for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order);
for (unsigned PSetID : PSetIDs) {
PSets[i].push_back(RegBank.getRegPressureSet(PSetID).Order);
}
llvm::sort(PSets[i]);
PSetsSeqs.add(PSets[i]);
@ -399,11 +398,9 @@ void RegisterInfoEmitter::EmitRegMappingTables(
return;
// Now we know maximal length of number list. Append -1's, where needed
for (DwarfRegNumsVecTy::iterator I = DwarfRegNums.begin(),
E = DwarfRegNums.end();
I != E; ++I)
for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
I->second.push_back(-1);
for (auto &DwarfRegNum : DwarfRegNums)
for (unsigned I = DwarfRegNum.second.size(), E = maxLength; I != E; ++I)
DwarfRegNum.second.push_back(-1);
StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");
@ -411,10 +408,10 @@ void RegisterInfoEmitter::EmitRegMappingTables(
// Emit reverse information about the dwarf register numbers.
for (unsigned j = 0; j < 2; ++j) {
for (unsigned i = 0, e = maxLength; i != e; ++i) {
for (unsigned I = 0, E = maxLength; I != E; ++I) {
OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
OS << i << "Dwarf2L[]";
OS << I << "Dwarf2L[]";
if (!isCtor) {
OS << " = {\n";
@ -422,17 +419,15 @@ void RegisterInfoEmitter::EmitRegMappingTables(
// Store the mapping sorted by the LLVM reg num so lookup can be done
// with a binary search.
std::map<uint64_t, Record*> Dwarf2LMap;
for (DwarfRegNumsVecTy::iterator
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
int DwarfRegNo = I->second[i];
for (auto &DwarfRegNum : DwarfRegNums) {
int DwarfRegNo = DwarfRegNum.second[I];
if (DwarfRegNo < 0)
continue;
Dwarf2LMap[DwarfRegNo] = I->first;
Dwarf2LMap[DwarfRegNo] = DwarfRegNum.first;
}
for (std::map<uint64_t, Record*>::iterator
I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
OS << " { " << I->first << "U, " << getQualifiedName(I->second)
for (auto &I : Dwarf2LMap)
OS << " { " << I.first << "U, " << getQualifiedName(I.second)
<< " },\n";
OS << "};\n";
@ -443,11 +438,10 @@ void RegisterInfoEmitter::EmitRegMappingTables(
// We have to store the size in a const global, it's used in multiple
// places.
OS << "extern const unsigned " << Namespace
<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2LSize";
if (!isCtor)
OS << " = array_lengthof(" << Namespace
<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
<< "Dwarf2L);\n\n";
<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2L);\n\n";
else
OS << ";\n\n";
}
@ -486,13 +480,12 @@ void RegisterInfoEmitter::EmitRegMappingTables(
OS << " = {\n";
// Store the mapping sorted by the Dwarf reg num so lookup can be done
// with a binary search.
for (DwarfRegNumsVecTy::iterator
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
int RegNo = I->second[i];
for (auto &DwarfRegNum : DwarfRegNums) {
int RegNo = DwarfRegNum.second[i];
if (RegNo == -1) // -1 is the default value, don't emit a mapping.
continue;
OS << " { " << getQualifiedName(I->first) << ", " << RegNo
OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo
<< "U },\n";
}
OS << "};\n";

29
llvm/utils/TableGen/X86DisassemblerTables.cpp
View File

@ -698,8 +698,8 @@ void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
ModRMDecision.push_back(decision.instructionIDs[index]);
break;
case MODRM_FULL:
for (unsigned index = 0; index < 256; ++index)
ModRMDecision.push_back(decision.instructionIDs[index]);
for (unsigned short InstructionID : decision.instructionIDs)
ModRMDecision.push_back(InstructionID);
break;
}
@ -710,10 +710,9 @@ void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
ModRMTableNum += ModRMDecision.size();
o1 << "/*Table" << EntryNumber << "*/\n";
i1++;
for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
E = ModRMDecision.end(); I != E; ++I) {
o1.indent(i1 * 2) << format("0x%hx", *I) << ", /*"
<< InstructionSpecifiers[*I].name << "*/\n";
for (unsigned I : ModRMDecision) {
o1.indent(i1 * 2) << format("0x%hx", I) << ", /*"
<< InstructionSpecifiers[I].name << "*/\n";
}
i1--;
}
@ -823,12 +822,9 @@ void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
for (unsigned Index = 0; Index < NumInstructions; ++Index) {
OperandListTy OperandList;
for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
++OperandIndex) {
OperandEncoding Encoding = (OperandEncoding)InstructionSpecifiers[Index]
.operands[OperandIndex].encoding;
OperandType Type = (OperandType)InstructionSpecifiers[Index]
.operands[OperandIndex].type;
for (auto Operand : InstructionSpecifiers[Index].operands) {
OperandEncoding Encoding = (OperandEncoding)Operand.encoding;
OperandType Type = (OperandType)Operand.type;
OperandList.push_back(std::make_pair(Encoding, Type));
}
unsigned &N = OperandSets[OperandList];
@ -856,12 +852,9 @@ void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
i++;
OperandListTy OperandList;
for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
++OperandIndex) {
OperandEncoding Encoding = (OperandEncoding)InstructionSpecifiers[index]
.operands[OperandIndex].encoding;
OperandType Type = (OperandType)InstructionSpecifiers[index]
.operands[OperandIndex].type;
for (auto Operand : InstructionSpecifiers[index].operands) {
OperandEncoding Encoding = (OperandEncoding)Operand.encoding;
OperandType Type = (OperandType)Operand.type;
OperandList.push_back(std::make_pair(Encoding, Type));
}
o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";