forked from OSchip/llvm-project
[ARM] Add fptosi.sat variants of the fixed point vcvt tests. NFC
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David Green
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36cb7477d1
commit
e6cca3125d
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@ -1024,3 +1024,120 @@ define arm_aapcs_vfpcc <4 x i32> @vcvt_negative2(<4 x float> %0) {
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%3 = fptosi <4 x float> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_s16_1(<8 x half> %0) {
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; CHECK-LABEL: vcvt_sat_s16_1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vadd.f16 q0, q0, q0
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; CHECK-NEXT: vcvt.s16.f16 q0, q0
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; CHECK-NEXT: bx lr
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%2 = fmul fast <8 x half> %0, <half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000>
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%3 = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2)
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ret <8 x i16> %3
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}
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define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_u16_1(<8 x half> %0) {
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; CHECK-LABEL: vcvt_sat_u16_1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vadd.f16 q0, q0, q0
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; CHECK-NEXT: vcvt.u16.f16 q0, q0
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; CHECK-NEXT: bx lr
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%2 = fmul fast <8 x half> %0, <half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000>
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%3 = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2)
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ret <8 x i16> %3
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}
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define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_s16_6(<8 x half> %0) {
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; CHECK-LABEL: vcvt_sat_s16_6:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i16 q1, #0x5400
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; CHECK-NEXT: vmul.f16 q0, q0, q1
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; CHECK-NEXT: vcvt.s16.f16 q0, q0
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; CHECK-NEXT: bx lr
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%2 = fmul fast <8 x half> %0, <half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400>
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%3 = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2)
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ret <8 x i16> %3
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}
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define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_u16_7(<8 x half> %0) {
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; CHECK-LABEL: vcvt_sat_u16_7:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i16 q1, #0x5800
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; CHECK-NEXT: vmul.f16 q0, q0, q1
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; CHECK-NEXT: vcvt.u16.f16 q0, q0
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; CHECK-NEXT: bx lr
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%2 = fmul fast <8 x half> %0, <half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800>
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%3 = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2)
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ret <8 x i16> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_s32_1(<4 x float> %0) {
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; CHECK-LABEL: vcvt_sat_s32_1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vadd.f32 q0, q0, q0
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; CHECK-NEXT: vcvt.s32.f32 q0, q0
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; CHECK-NEXT: bx lr
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%2 = fmul fast <4 x float> %0, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
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%3 = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %2)
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_1(<4 x float> %0) {
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; CHECK-LABEL: vcvt_sat_u32_1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vadd.f32 q0, q0, q0
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; CHECK-NEXT: vcvt.u32.f32 q0, q0
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; CHECK-NEXT: bx lr
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%2 = fmul fast <4 x float> %0, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
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%3 = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %2)
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_11(<4 x float> %0) {
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; CHECK-LABEL: vcvt_sat_u32_11:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i32 q1, #0x45000000
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; CHECK-NEXT: vmul.f32 q0, q0, q1
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; CHECK-NEXT: vcvt.s32.f32 q0, q0
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; CHECK-NEXT: bx lr
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%2 = fmul fast <4 x float> %0, <float 2.048000e+03, float 2.048000e+03, float 2.048000e+03, float 2.048000e+03>
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%3 = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %2)
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_7(<4 x float> %0) {
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; CHECK-LABEL: vcvt_sat_u32_7:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i32 q1, #0x4b000000
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; CHECK-NEXT: vmul.f32 q0, q0, q1
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; CHECK-NEXT: vcvt.u32.f32 q0, q0
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; CHECK-NEXT: bx lr
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%2 = fmul fast <4 x float> %0, <float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000>
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%3 = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %2)
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_7_24(<4 x float> %0) {
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; CHECK-LABEL: vcvt_sat_u32_7_24:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i32 q2, #0x4b000000
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; CHECK-NEXT: vmov.i32 q1, #0xffffff
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; CHECK-NEXT: vmul.f32 q0, q0, q2
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; CHECK-NEXT: vcvt.u32.f32 q0, q0
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; CHECK-NEXT: vmin.u32 q0, q0, q1
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; CHECK-NEXT: vbic.i32 q0, #0xff000000
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; CHECK-NEXT: bx lr
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%2 = fmul fast <4 x float> %0, <float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000>
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%3 = call <4 x i24> @llvm.fptoui.sat.v4i24.v4f32(<4 x float> %2)
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%4 = zext <4 x i24> %3 to <4 x i32>
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ret <4 x i32> %4
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}
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declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float>)
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declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float>)
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declare <4 x i24> @llvm.fptoui.sat.v4i24.v4f32(<4 x float>)
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declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half>)
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declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half>)
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