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[SelectionDAG] Don't apply MinRCSize constraint in InstrEmitter::AddRegisterOperand for IMPLICIT_DEF sources. 

MinRCSize is 4 and prevents constrainRegClass from changing the
register class if the new class has size less than 4.

IMPLICIT_DEF gets a unique vreg for each use and will be removed
by the ProcessImplicitDef pass before register allocation. I don't
think there is any reason to prevent constraining the virtual register
to whatever register class the use needs.

The attached test case was previously creating a copy of IMPLICIT_DEF
because vrm8nov0 has 3 registers in it.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D128005
This commit is contained in:
Craig Topper 2022-06-16 14:45:44 -07:00
parent 011e0604eb
commit e6c7a3a54f
2 changed files with 31 additions and 1 deletions
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9
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -317,8 +317,15 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
if (OpRC) {
unsigned MinNumRegs = MinRCSize;
// Don't apply any RC size limit for IMPLICIT_DEF. Each use has a unique
// virtual register.
if (Op.isMachineOpcode() &&
Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)
MinNumRegs = 0;
const TargetRegisterClass *ConstrainedRC
= MRI->constrainRegClass(VReg, OpRC, MinRCSize);
= MRI->constrainRegClass(VReg, OpRC, MinNumRegs);
if (!ConstrainedRC) {
OpRC = TRI->getAllocatableClass(OpRC);
assert(OpRC && "Constraints cannot be fulfilled for allocation");

23
llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll Normal file
View File

@ -0,0 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc < %s -mtriple=riscv64 -mattr=+v -stop-after=finalize-isel | FileCheck %s
; Make sure we don't create a COPY instruction for IMPLICIT_DEF.
define <vscale x 8 x i64> @vpload_nxv8i64(<vscale x 8 x i64>* %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) #1 {
; CHECK-LABEL: name: vpload_nxv8i64
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $x10, $v0, $x11
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: $v0 = COPY [[COPY1]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE64_V_M8_MASK:%[0-9]+]]:vrm8nov0 = PseudoVLE64_V_M8_MASK [[DEF]], [[COPY2]], $v0, [[COPY]], 6 /* e64 */, 1 :: (load unknown-size from %ir.ptr, align 64)
; CHECK-NEXT: $v8m8 = COPY [[PseudoVLE64_V_M8_MASK]]
; CHECK-NEXT: PseudoRET implicit $v8m8
%load = call <vscale x 8 x i64> @llvm.vp.load.nxv8i64.p0nxv8i64(<vscale x 8 x i64>* %ptr, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %load
}
declare <vscale x 8 x i64> @llvm.vp.load.nxv8i64.p0nxv8i64(<vscale x 8 x i64>*, <vscale x 8 x i1>, i32)