From e6ae6767d9e0f0e2083e4b4e3d731fbedc00a8ed Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Tue, 5 Jul 2016 21:23:04 +0000 Subject: [PATCH] AArch64: TableGenerate system instruction operands. The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. llvm-svn: 274576 --- llvm/include/llvm/TableGen/SearchableTable.td | 41 + llvm/lib/Target/AArch64/AArch64.td | 6 + .../Target/AArch64/AArch64ISelDAGToDAG.cpp | 44 +- .../lib/Target/AArch64/AArch64InstrFormats.td | 5 +- .../Target/AArch64/AArch64SystemOperands.td | 1018 +++++++++++++++++ .../AArch64/AsmParser/AArch64AsmParser.cpp | 87 +- llvm/lib/Target/AArch64/CMakeLists.txt | 2 + .../Disassembler/AArch64Disassembler.cpp | 11 +- .../InstPrinter/AArch64InstPrinter.cpp | 70 +- .../Target/AArch64/Utils/AArch64BaseInfo.cpp | 970 ++-------------- .../Target/AArch64/Utils/AArch64BaseInfo.h | 1011 ++-------------- llvm/test/CodeGen/AArch64/special-reg.ll | 2 +- llvm/test/MC/AArch64/arm64-spsel-sysreg.s | 8 +- llvm/test/MC/AArch64/arm64-system-encoding.s | 6 +- llvm/test/MC/AArch64/basic-a64-instructions.s | 30 +- .../MC/Disassembler/AArch64/arm64-system.txt | 2 +- .../AArch64/basic-a64-instructions.txt | 30 +- llvm/utils/TableGen/CMakeLists.txt | 1 + .../utils/TableGen/SearchableTableEmitter.cpp | 320 ++++++ llvm/utils/TableGen/TableGen.cpp | 8 +- llvm/utils/TableGen/TableGenBackends.h | 1 + 21 files changed, 1669 insertions(+), 2004 deletions(-) create mode 100644 llvm/include/llvm/TableGen/SearchableTable.td create mode 100644 llvm/lib/Target/AArch64/AArch64SystemOperands.td create mode 100644 llvm/utils/TableGen/SearchableTableEmitter.cpp diff --git a/llvm/include/llvm/TableGen/SearchableTable.td b/llvm/include/llvm/TableGen/SearchableTable.td new file mode 100644 index 000000000000..12aaf6000c31 --- /dev/null +++ b/llvm/include/llvm/TableGen/SearchableTable.td @@ -0,0 +1,41 @@ +//===- SearchableTable.td ----------------------------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the key top-level classes needed to produce a reasonably +// generic table that can be binary-searched via int and string entries. +// +// Each table must instantiate "Mappingkind", listing the fields that should be +// included and fields that shoould be searchable. Only two kinds of fields are +// searchable at the moment: "strings" (which are compared case-insensitively), +// and "bits". +// +// For each "MappingKind" the generated header will create GET_MAPPINGKIND_DECL +// and GET_MAPPINGKIND_IMPL guards. +// +// Inside the DECL guard will be a set of function declarations: +// "lookup{InstanceClass}By{SearchableField}", returning "const {InstanceClass} +// *" and accepting either a StringRef or a uintN_t. Additionally, if +// EnumNameField is still defined, there will be an "enum {InstanceClass}Values" +// allowing C++ code to reference either the primary data table's entries (if +// EnumValueField is not defined) or some other field (e.g. encoding) if it is. +// +// Inside the IMPL guard will be a primary data table "{InstanceClass}sList" and +// as many searchable indexes as requested +// ("{InstanceClass}sBy{SearchableField}"). Additionally implementations of the +// lookup function will be provided. +// +// See AArch64SystemOperands.td and its generated header for example uses. +// +//===----------------------------------------------------------------------===// + +class SearchableTable { + list SearchableFields; + string EnumNameField = "Name"; + string EnumValueField; +} diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 760e7e878606..91e8efb655f8 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -131,6 +131,12 @@ include "AArch64InstrInfo.td" def AArch64InstrInfo : InstrInfo; +//===----------------------------------------------------------------------===// +// Named operands for MRS/MSR/TLBI/... +//===----------------------------------------------------------------------===// + +include "AArch64SystemOperands.td" + //===----------------------------------------------------------------------===// // AArch64 Processors supported. // diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 2e98c41f0e72..8d649250f656 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -2438,12 +2438,14 @@ bool AArch64DAGToDAGISel::tryReadRegister(SDNode *N) { // Use the sysreg mapper to map the remaining possible strings to the // value for the register to be used for the instruction operand. - AArch64SysReg::MRSMapper mapper; - bool IsValidSpecialReg; - Reg = mapper.fromString(RegString->getString(), - Subtarget->getFeatureBits(), - IsValidSpecialReg); - if (IsValidSpecialReg) { + auto TheReg = AArch64SysReg::lookupSysRegByName(RegString->getString()); + if (TheReg && TheReg->Readable && + TheReg->haveFeatures(Subtarget->getFeatureBits())) + Reg = TheReg->Encoding; + else + Reg = AArch64SysReg::parseGenericRegister(RegString->getString()); + + if (Reg != -1) { ReplaceNode(N, CurDAG->getMachineNode( AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other, CurDAG->getTargetConstant(Reg, DL, MVT::i32), @@ -2477,14 +2479,11 @@ bool AArch64DAGToDAGISel::tryWriteRegister(SDNode *N) { // pstatefield for the MSR (immediate) instruction, we also require that an // immediate value has been provided as an argument, we know that this is // the case as it has been ensured by semantic checking. - AArch64PState::PStateMapper PMapper; - bool IsValidSpecialReg; - Reg = PMapper.fromString(RegString->getString(), - Subtarget->getFeatureBits(), - IsValidSpecialReg); - if (IsValidSpecialReg) { + auto PMapper = AArch64PState::lookupPStateByName(RegString->getString());; + if (PMapper) { assert (isa(N->getOperand(2)) && "Expected a constant integer expression."); + unsigned Reg = PMapper->Encoding; uint64_t Immed = cast(N->getOperand(2))->getZExtValue(); unsigned State; if (Reg == AArch64PState::PAN || Reg == AArch64PState::UAO) { @@ -2505,16 +2504,17 @@ bool AArch64DAGToDAGISel::tryWriteRegister(SDNode *N) { // Use the sysreg mapper to attempt to map the remaining possible strings // to the value for the register to be used for the MSR (register) // instruction operand. - AArch64SysReg::MSRMapper Mapper; - Reg = Mapper.fromString(RegString->getString(), - Subtarget->getFeatureBits(), - IsValidSpecialReg); - - if (IsValidSpecialReg) { - ReplaceNode( - N, CurDAG->getMachineNode(AArch64::MSR, DL, MVT::Other, - CurDAG->getTargetConstant(Reg, DL, MVT::i32), - N->getOperand(2), N->getOperand(0))); + auto TheReg = AArch64SysReg::lookupSysRegByName(RegString->getString()); + if (TheReg && TheReg->Writeable && + TheReg->haveFeatures(Subtarget->getFeatureBits())) + Reg = TheReg->Encoding; + else + Reg = AArch64SysReg::parseGenericRegister(RegString->getString()); + if (Reg != -1) { + ReplaceNode(N, CurDAG->getMachineNode( + AArch64::MSR, DL, MVT::Other, + CurDAG->getTargetConstant(Reg, DL, MVT::i32), + N->getOperand(2), N->getOperand(0))); return true; } diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 99bd86448c5f..34d35e961210 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -923,10 +923,7 @@ def psbhint_op : Operand { // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields. if (!MCOp.isImm()) return false; - bool ValidNamed; - (void)AArch64PSBHint::PSBHintMapper().toString(MCOp.getImm(), - STI.getFeatureBits(), ValidNamed); - return ValidNamed; + return AArch64PSBHint::lookupPSBByEncoding(MCOp.getImm()) != nullptr; }]; } diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td new file mode 100644 index 000000000000..a3736c0868fb --- /dev/null +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -0,0 +1,1018 @@ +//===- AArch64SystemOperands.td ----------------------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the symbolic operands permitted for various kinds of +// AArch64 system instruction. +// +//===----------------------------------------------------------------------===// + +include "llvm/TableGen/SearchableTable.td" + +//===----------------------------------------------------------------------===// +// AT (address translate) instruction options. +//===----------------------------------------------------------------------===// + +class AT op0, bits<3> op1, bits<4> crn, bits<4> crm, + bits<3> op2> : SearchableTable { + let SearchableFields = ["Name", "Encoding"]; + let EnumValueField = "Encoding"; + + string Name = name; + bits<16> Encoding; + let Encoding{15-14} = op0; + let Encoding{13-11} = op1; + let Encoding{10-7} = crn; + let Encoding{6-3} = crm; + let Encoding{2-0} = op2; +} + +def : AT<"S1E1R", 0b01, 0b000, 0b0111, 0b1000, 0b000>; +def : AT<"S1E2R", 0b01, 0b100, 0b0111, 0b1000, 0b000>; +def : AT<"S1E3R", 0b01, 0b110, 0b0111, 0b1000, 0b000>; +def : AT<"S1E1W", 0b01, 0b000, 0b0111, 0b1000, 0b001>; +def : AT<"S1E2W", 0b01, 0b100, 0b0111, 0b1000, 0b001>; +def : AT<"S1E3W", 0b01, 0b110, 0b0111, 0b1000, 0b001>; +def : AT<"S1E0R", 0b01, 0b000, 0b0111, 0b1000, 0b010>; +def : AT<"S1E0W", 0b01, 0b000, 0b0111, 0b1000, 0b011>; +def : AT<"S12E1R", 0b01, 0b100, 0b0111, 0b1000, 0b100>; +def : AT<"S12E1W", 0b01, 0b100, 0b0111, 0b1000, 0b101>; +def : AT<"S12E0R", 0b01, 0b100, 0b0111, 0b1000, 0b110>; +def : AT<"S12E0W", 0b01, 0b100, 0b0111, 0b1000, 0b111>; +def : AT<"S1E1RP", 0b01, 0b000, 0b0111, 0b1001, 0b000>; +def : AT<"S1E1WP", 0b01, 0b000, 0b0111, 0b1001, 0b001>; + + +//===----------------------------------------------------------------------===// +// DMB/DSB (data barrier) instruction options. +//===----------------------------------------------------------------------===// + +class DB encoding> : SearchableTable { + let SearchableFields = ["Name", "Encoding"]; + let EnumValueField = "Encoding"; + + string Name = name; + bits<4> Encoding = encoding; +} + +def : DB<"oshld", 0x1>; +def : DB<"oshst", 0x2>; +def : DB<"osh", 0x3>; +def : DB<"nshld", 0x5>; +def : DB<"nshst", 0x6>; +def : DB<"nsh", 0x7>; +def : DB<"ishld", 0x9>; +def : DB<"ishst", 0xa>; +def : DB<"ish", 0xb>; +def : DB<"ld", 0xd>; +def : DB<"st", 0xe>; +def : DB<"sy", 0xf>; + +//===----------------------------------------------------------------------===// +// DC (data cache maintenance) instruction options. +//===----------------------------------------------------------------------===// + +class DC op0, bits<3> op1, bits<4> crn, bits<4> crm, + bits<3> op2> : SearchableTable { + let SearchableFields = ["Name", "Encoding"]; + let EnumValueField = "Encoding"; + + string Name = name; + bits<16> Encoding; + let Encoding{15-14} = op0; + let Encoding{13-11} = op1; + let Encoding{10-7} = crn; + let Encoding{6-3} = crm; + let Encoding{2-0} = op2; +} + +def : DC<"ZVA", 0b01, 0b011, 0b0111, 0b0100, 0b001>; +def : DC<"IVAC", 0b01, 0b000, 0b0111, 0b0110, 0b001>; +def : DC<"ISW", 0b01, 0b000, 0b0111, 0b0110, 0b010>; +def : DC<"CVAC", 0b01, 0b011, 0b0111, 0b1010, 0b001>; +def : DC<"CSW", 0b01, 0b000, 0b0111, 0b1010, 0b010>; +def : DC<"CVAU", 0b01, 0b011, 0b0111, 0b1011, 0b001>; +def : DC<"CIVAC", 0b01, 0b011, 0b0111, 0b1110, 0b001>; +def : DC<"CISW", 0b01, 0b000, 0b0111, 0b1110, 0b010>; + +//===----------------------------------------------------------------------===// +// IC (instruction cache maintenance) instruction options. +//===----------------------------------------------------------------------===// + +class IC op1, bits<4> crn, bits<4> crm, bits<3> op2, + bit needsreg> : SearchableTable { + let SearchableFields = ["Name", "Encoding"]; + let EnumValueField = "Encoding"; + + string Name = name; + bits<14> Encoding; + let Encoding{13-11} = op1; + let Encoding{10-7} = crn; + let Encoding{6-3} = crm; + let Encoding{2-0} = op2; + bit NeedsReg = needsreg; +} + +def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>; +def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>; +def : IC<"IVAU", 0b000, 0b0111, 0b0001, 0b000, 1>; + +//===----------------------------------------------------------------------===// +// ISB (instruction-fetch barrier) instruction options. +//===----------------------------------------------------------------------===// + +class ISB encoding> : SearchableTable{ + let SearchableFields = ["Name", "Encoding"]; + let EnumValueField = "Encoding"; + + string Name = name; + bits<4> Encoding; + let Encoding = encoding; +} + +def : ISB<"sy", 0xf>; + +//===----------------------------------------------------------------------===// +// PRFM (prefetch) instruction options. +//===----------------------------------------------------------------------===// + +class PRFM encoding> : SearchableTable { + let SearchableFields = ["Name", "Encoding"]; + let EnumValueField = "Encoding"; + + string Name = name; + bits<5> Encoding; + let Encoding = encoding; +} + +def : PRFM<"pldl1keep", 0x00>; +def : PRFM<"pldl1strm", 0x01>; +def : PRFM<"pldl2keep", 0x02>; +def : PRFM<"pldl2strm", 0x03>; +def : PRFM<"pldl3keep", 0x04>; +def : PRFM<"pldl3strm", 0x05>; +def : PRFM<"plil1keep", 0x08>; +def : PRFM<"plil1strm", 0x09>; +def : PRFM<"plil2keep", 0x0a>; +def : PRFM<"plil2strm", 0x0b>; +def : PRFM<"plil3keep", 0x0c>; +def : PRFM<"plil3strm", 0x0d>; +def : PRFM<"pstl1keep", 0x10>; +def : PRFM<"pstl1strm", 0x11>; +def : PRFM<"pstl2keep", 0x12>; +def : PRFM<"pstl2strm", 0x13>; +def : PRFM<"pstl3keep", 0x14>; +def : PRFM<"pstl3strm", 0x15>; + +//===----------------------------------------------------------------------===// +// PState instruction options. +//===----------------------------------------------------------------------===// + +class PState encoding> : SearchableTable { + let SearchableFields = ["Name", "Encoding"]; + let EnumValueField = "Encoding"; + + string Name = name; + bits<5> Encoding; + let Encoding = encoding; + code Requires = [{ {} }]; +} + +def : PState<"SPSel", 0b00101>; +def : PState<"DAIFSet", 0b11110>; +def : PState<"DAIFClr", 0b11111>; +// v8.1a "Privileged Access Never" extension-specific PStates +let Requires = [{ {AArch64::HasV8_1aOps} }] in +def : PState<"PAN", 0b00100>; +// v8.2a "User Access Override" extension-specific PStates +let Requires = [{ {AArch64::HasV8_2aOps} }] in +def : PState<"UAO", 0b00011>; + + +//===----------------------------------------------------------------------===// +// PSB instruction options. +//===----------------------------------------------------------------------===// + +class PSB encoding> : SearchableTable { + let SearchableFields = ["Name", "Encoding"]; + let EnumValueField = "Encoding"; + + string Name = name; + bits<5> Encoding; + let Encoding = encoding; +} + +def : PSB<"csync", 0x11>; + +//===----------------------------------------------------------------------===// +// TLBI (translation lookaside buffer invalidate) instruction options. +//===----------------------------------------------------------------------===// + +class TLBI op0, bits<3> op1, bits<4> crn, bits<4> crm, + bits<3> op2, bit needsreg = 1> : SearchableTable { + let SearchableFields = ["Name", "Encoding"]; + let EnumValueField = "Encoding"; + + string Name = name; + bits<16> Encoding; + let Encoding{15-14} = op0; + let Encoding{13-11} = op1; + let Encoding{10-7} = crn; + let Encoding{6-3} = crm; + let Encoding{2-0} = op2; + bit NeedsReg = needsreg; +} + +def : TLBI<"IPAS2E1IS", 0b01, 0b100, 0b1000, 0b0000, 0b001>; +def : TLBI<"IPAS2LE1IS", 0b01, 0b100, 0b1000, 0b0000, 0b101>; +def : TLBI<"VMALLE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b000, 0>; +def : TLBI<"ALLE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b000, 0>; +def : TLBI<"ALLE3IS", 0b01, 0b110, 0b1000, 0b0011, 0b000, 0>; +def : TLBI<"VAE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b001>; +def : TLBI<"VAE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b001>; +def : TLBI<"VAE3IS", 0b01, 0b110, 0b1000, 0b0011, 0b001>; +def : TLBI<"ASIDE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b010>; +def : TLBI<"VAAE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b011>; +def : TLBI<"ALLE1IS", 0b01, 0b100, 0b1000, 0b0011, 0b100, 0>; +def : TLBI<"VALE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b101>; +def : TLBI<"VALE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b101>; +def : TLBI<"VALE3IS", 0b01, 0b110, 0b1000, 0b0011, 0b101>; +def : TLBI<"VMALLS12E1IS", 0b01, 0b100, 0b1000, 0b0011, 0b110, 0>; +def : TLBI<"VAALE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b111>; +def : TLBI<"IPAS2E1", 0b01, 0b100, 0b1000, 0b0100, 0b001>; +def : TLBI<"IPAS2LE1", 0b01, 0b100, 0b1000, 0b0100, 0b101>; +def : TLBI<"VMALLE1", 0b01, 0b000, 0b1000, 0b0111, 0b000, 0>; +def : TLBI<"ALLE2", 0b01, 0b100, 0b1000, 0b0111, 0b000, 0>; +def : TLBI<"ALLE3", 0b01, 0b110, 0b1000, 0b0111, 0b000, 0>; +def : TLBI<"VAE1", 0b01, 0b000, 0b1000, 0b0111, 0b001>; +def : TLBI<"VAE2", 0b01, 0b100, 0b1000, 0b0111, 0b001>; +def : TLBI<"VAE3", 0b01, 0b110, 0b1000, 0b0111, 0b001>; +def : TLBI<"ASIDE1", 0b01, 0b000, 0b1000, 0b0111, 0b010>; +def : TLBI<"VAAE1", 0b01, 0b000, 0b1000, 0b0111, 0b011>; +def : TLBI<"ALLE1", 0b01, 0b100, 0b1000, 0b0111, 0b100, 0>; +def : TLBI<"VALE1", 0b01, 0b000, 0b1000, 0b0111, 0b101>; +def : TLBI<"VALE2", 0b01, 0b100, 0b1000, 0b0111, 0b101>; +def : TLBI<"VALE3", 0b01, 0b110, 0b1000, 0b0111, 0b101>; +def : TLBI<"VMALLS12E1", 0b01, 0b100, 0b1000, 0b0111, 0b110, 0>; +def : TLBI<"VAALE1", 0b01, 0b000, 0b1000, 0b0111, 0b111>; + + +//===----------------------------------------------------------------------===// +// MRS/MSR (system register read/write) instruction options. +//===----------------------------------------------------------------------===// + +class SysReg op0, bits<3> op1, bits<4> crn, bits<4> crm, + bits<3> op2> : SearchableTable { + let SearchableFields = ["Name", "Encoding"]; + let EnumValueField = "Encoding"; + + string Name = name; + bits<16> Encoding; + let Encoding{15-14} = op0; + let Encoding{13-11} = op1; + let Encoding{10-7} = crn; + let Encoding{6-3} = crm; + let Encoding{2-0} = op2; + bit Readable = ?; + bit Writeable = ?; + code Requires = [{ {} }]; +} + +class RWSysReg op0, bits<3> op1, bits<4> crn, bits<4> crm, + bits<3> op2> + : SysReg { + let Readable = 1; + let Writeable = 1; +} + +class ROSysReg op0, bits<3> op1, bits<4> crn, bits<4> crm, + bits<3> op2> + : SysReg { + let Readable = 1; + let Writeable = 0; +} + +class WOSysReg op0, bits<3> op1, bits<4> crn, bits<4> crm, + bits<3> op2> + : SysReg { + let Readable = 0; + let Writeable = 1; +} + +//===---------------------- +// Read-only regs +//===---------------------- + +// Op0 Op1 CRn CRm Op2 +def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>; +def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>; +def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>; +def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>; +def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>; +def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>; +def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>; +def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>; +def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>; +def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>; +def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>; +def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>; +def : ROSysReg<"REVIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b110>; +def : ROSysReg<"AIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b111>; +def : ROSysReg<"DCZID_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b111>; +def : ROSysReg<"ID_PFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b000>; +def : ROSysReg<"ID_PFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b001>; +def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>; +def : ROSysReg<"ID_AFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b011>; +def : ROSysReg<"ID_MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b100>; +def : ROSysReg<"ID_MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b101>; +def : ROSysReg<"ID_MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b110>; +def : ROSysReg<"ID_MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b111>; +def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>; +def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>; +def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>; +def : ROSysReg<"ID_ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b011>; +def : ROSysReg<"ID_ISAR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b100>; +def : ROSysReg<"ID_ISAR5_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b101>; +def : ROSysReg<"ID_AA64PFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b000>; +def : ROSysReg<"ID_AA64PFR1_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b001>; +def : ROSysReg<"ID_AA64DFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b000>; +def : ROSysReg<"ID_AA64DFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b001>; +def : ROSysReg<"ID_AA64AFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b100>; +def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>; +def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>; +def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>; +def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>; +def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>; +def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010> { + let Requires = [{ {AArch64::HasV8_2aOps} }]; +} +def : ROSysReg<"MVFR0_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b000>; +def : ROSysReg<"MVFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b001>; +def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>; +def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>; +def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>; +def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>; +def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>; +def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>; +def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>; +def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>; + +// Trace registers +// Op0 Op1 CRn CRm Op2 +def : ROSysReg<"TRCSTATR", 0b10, 0b001, 0b0000, 0b0011, 0b000>; +def : ROSysReg<"TRCIDR8", 0b10, 0b001, 0b0000, 0b0000, 0b110>; +def : ROSysReg<"TRCIDR9", 0b10, 0b001, 0b0000, 0b0001, 0b110>; +def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>; +def : ROSysReg<"TRCIDR11", 0b10, 0b001, 0b0000, 0b0011, 0b110>; +def : ROSysReg<"TRCIDR12", 0b10, 0b001, 0b0000, 0b0100, 0b110>; +def : ROSysReg<"TRCIDR13", 0b10, 0b001, 0b0000, 0b0101, 0b110>; +def : ROSysReg<"TRCIDR0", 0b10, 0b001, 0b0000, 0b1000, 0b111>; +def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>; +def : ROSysReg<"TRCIDR2", 0b10, 0b001, 0b0000, 0b1010, 0b111>; +def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>; +def : ROSysReg<"TRCIDR4", 0b10, 0b001, 0b0000, 0b1100, 0b111>; +def : ROSysReg<"TRCIDR5", 0b10, 0b001, 0b0000, 0b1101, 0b111>; +def : ROSysReg<"TRCIDR6", 0b10, 0b001, 0b0000, 0b1110, 0b111>; +def : ROSysReg<"TRCIDR7", 0b10, 0b001, 0b0000, 0b1111, 0b111>; +def : ROSysReg<"TRCOSLSR", 0b10, 0b001, 0b0001, 0b0001, 0b100>; +def : ROSysReg<"TRCPDSR", 0b10, 0b001, 0b0001, 0b0101, 0b100>; +def : ROSysReg<"TRCDEVAFF0", 0b10, 0b001, 0b0111, 0b1010, 0b110>; +def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>; +def : ROSysReg<"TRCLSR", 0b10, 0b001, 0b0111, 0b1101, 0b110>; +def : ROSysReg<"TRCAUTHSTATUS", 0b10, 0b001, 0b0111, 0b1110, 0b110>; +def : ROSysReg<"TRCDEVARCH", 0b10, 0b001, 0b0111, 0b1111, 0b110>; +def : ROSysReg<"TRCDEVID", 0b10, 0b001, 0b0111, 0b0010, 0b111>; +def : ROSysReg<"TRCDEVTYPE", 0b10, 0b001, 0b0111, 0b0011, 0b111>; +def : ROSysReg<"TRCPIDR4", 0b10, 0b001, 0b0111, 0b0100, 0b111>; +def : ROSysReg<"TRCPIDR5", 0b10, 0b001, 0b0111, 0b0101, 0b111>; +def : ROSysReg<"TRCPIDR6", 0b10, 0b001, 0b0111, 0b0110, 0b111>; +def : ROSysReg<"TRCPIDR7", 0b10, 0b001, 0b0111, 0b0111, 0b111>; +def : ROSysReg<"TRCPIDR0", 0b10, 0b001, 0b0111, 0b1000, 0b111>; +def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>; +def : ROSysReg<"TRCPIDR2", 0b10, 0b001, 0b0111, 0b1010, 0b111>; +def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>; +def : ROSysReg<"TRCCIDR0", 0b10, 0b001, 0b0111, 0b1100, 0b111>; +def : ROSysReg<"TRCCIDR1", 0b10, 0b001, 0b0111, 0b1101, 0b111>; +def : ROSysReg<"TRCCIDR2", 0b10, 0b001, 0b0111, 0b1110, 0b111>; +def : ROSysReg<"TRCCIDR3", 0b10, 0b001, 0b0111, 0b1111, 0b111>; + +// GICv3 registers +// Op0 Op1 CRn CRm Op2 +def : ROSysReg<"ICC_IAR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b000>; +def : ROSysReg<"ICC_IAR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b000>; +def : ROSysReg<"ICC_HPPIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b010>; +def : ROSysReg<"ICC_HPPIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b010>; +def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>; +def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>; +def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>; +def : ROSysReg<"ICH_ELSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>; + +// v8.1a "Limited Ordering Regions" extension-specific system register +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::HasV8_1aOps} }] in +def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>; + +// v8.2a "RAS extension" registers +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeatureRAS} }] in { +def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b000>; +def : ROSysReg<"ERXFR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b000>; +} + +//===---------------------- +// Write-only regs +//===---------------------- + +// Op0 Op1 CRn CRm Op2 +def : WOSysReg<"DBGDTRTX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>; +def : WOSysReg<"OSLAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b100>; +def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>; + +// Trace Registers +// Op0 Op1 CRn CRm Op2 +def : WOSysReg<"TRCOSLAR", 0b10, 0b001, 0b0001, 0b0000, 0b100>; +def : WOSysReg<"TRCLAR", 0b10, 0b001, 0b0111, 0b1100, 0b110>; + +// GICv3 registers +// Op0 Op1 CRn CRm Op2 +def : WOSysReg<"ICC_EOIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b001>; +def : WOSysReg<"ICC_EOIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b001>; +def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>; +def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>; +def : WOSysReg<"ICC_ASGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b110>; +def : WOSysReg<"ICC_SGI0R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b111>; + +//===---------------------- +// Read-write regs +//===---------------------- + +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"OSDTRRX_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b010>; +def : RWSysReg<"OSDTRTX_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b010>; +def : RWSysReg<"TEECR32_EL1", 0b10, 0b010, 0b0000, 0b0000, 0b000>; +def : RWSysReg<"MDCCINT_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b000>; +def : RWSysReg<"MDSCR_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b010>; +def : RWSysReg<"DBGDTR_EL0", 0b10, 0b011, 0b0000, 0b0100, 0b000>; +def : RWSysReg<"OSECCR_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b010>; +def : RWSysReg<"DBGVCR32_EL2", 0b10, 0b100, 0b0000, 0b0111, 0b000>; +def : RWSysReg<"DBGBVR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b100>; +def : RWSysReg<"DBGBVR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b100>; +def : RWSysReg<"DBGBVR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b100>; +def : RWSysReg<"DBGBVR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b100>; +def : RWSysReg<"DBGBVR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b100>; +def : RWSysReg<"DBGBVR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b100>; +def : RWSysReg<"DBGBVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b100>; +def : RWSysReg<"DBGBVR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b100>; +def : RWSysReg<"DBGBVR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b100>; +def : RWSysReg<"DBGBVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b100>; +def : RWSysReg<"DBGBVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b100>; +def : RWSysReg<"DBGBVR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b100>; +def : RWSysReg<"DBGBVR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b100>; +def : RWSysReg<"DBGBVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b100>; +def : RWSysReg<"DBGBVR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b100>; +def : RWSysReg<"DBGBVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b100>; +def : RWSysReg<"DBGBCR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b101>; +def : RWSysReg<"DBGBCR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b101>; +def : RWSysReg<"DBGBCR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b101>; +def : RWSysReg<"DBGBCR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b101>; +def : RWSysReg<"DBGBCR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b101>; +def : RWSysReg<"DBGBCR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b101>; +def : RWSysReg<"DBGBCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b101>; +def : RWSysReg<"DBGBCR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b101>; +def : RWSysReg<"DBGBCR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b101>; +def : RWSysReg<"DBGBCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b101>; +def : RWSysReg<"DBGBCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b101>; +def : RWSysReg<"DBGBCR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b101>; +def : RWSysReg<"DBGBCR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b101>; +def : RWSysReg<"DBGBCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b101>; +def : RWSysReg<"DBGBCR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b101>; +def : RWSysReg<"DBGBCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b101>; +def : RWSysReg<"DBGWVR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b110>; +def : RWSysReg<"DBGWVR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b110>; +def : RWSysReg<"DBGWVR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b110>; +def : RWSysReg<"DBGWVR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b110>; +def : RWSysReg<"DBGWVR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b110>; +def : RWSysReg<"DBGWVR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b110>; +def : RWSysReg<"DBGWVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b110>; +def : RWSysReg<"DBGWVR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b110>; +def : RWSysReg<"DBGWVR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b110>; +def : RWSysReg<"DBGWVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b110>; +def : RWSysReg<"DBGWVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b110>; +def : RWSysReg<"DBGWVR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b110>; +def : RWSysReg<"DBGWVR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b110>; +def : RWSysReg<"DBGWVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b110>; +def : RWSysReg<"DBGWVR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b110>; +def : RWSysReg<"DBGWVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b110>; +def : RWSysReg<"DBGWCR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b111>; +def : RWSysReg<"DBGWCR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b111>; +def : RWSysReg<"DBGWCR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b111>; +def : RWSysReg<"DBGWCR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b111>; +def : RWSysReg<"DBGWCR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b111>; +def : RWSysReg<"DBGWCR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b111>; +def : RWSysReg<"DBGWCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b111>; +def : RWSysReg<"DBGWCR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b111>; +def : RWSysReg<"DBGWCR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b111>; +def : RWSysReg<"DBGWCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b111>; +def : RWSysReg<"DBGWCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b111>; +def : RWSysReg<"DBGWCR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b111>; +def : RWSysReg<"DBGWCR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b111>; +def : RWSysReg<"DBGWCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b111>; +def : RWSysReg<"DBGWCR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b111>; +def : RWSysReg<"DBGWCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b111>; +def : RWSysReg<"TEEHBR32_EL1", 0b10, 0b010, 0b0001, 0b0000, 0b000>; +def : RWSysReg<"OSDLR_EL1", 0b10, 0b000, 0b0001, 0b0011, 0b100>; +def : RWSysReg<"DBGPRCR_EL1", 0b10, 0b000, 0b0001, 0b0100, 0b100>; +def : RWSysReg<"DBGCLAIMSET_EL1", 0b10, 0b000, 0b0111, 0b1000, 0b110>; +def : RWSysReg<"DBGCLAIMCLR_EL1", 0b10, 0b000, 0b0111, 0b1001, 0b110>; +def : RWSysReg<"CSSELR_EL1", 0b11, 0b010, 0b0000, 0b0000, 0b000>; +def : RWSysReg<"VPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b000>; +def : RWSysReg<"VMPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b101>; +def : RWSysReg<"CPACR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b010>; +def : RWSysReg<"SCTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b000>; +def : RWSysReg<"SCTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b000>; +def : RWSysReg<"SCTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b000>; +def : RWSysReg<"ACTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b001>; +def : RWSysReg<"ACTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b001>; +def : RWSysReg<"ACTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b001>; +def : RWSysReg<"HCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b000>; +def : RWSysReg<"SCR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b000>; +def : RWSysReg<"MDCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b001>; +def : RWSysReg<"SDER32_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b001>; +def : RWSysReg<"CPTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b010>; +def : RWSysReg<"CPTR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b010>; +def : RWSysReg<"HSTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b011>; +def : RWSysReg<"HACR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b111>; +def : RWSysReg<"MDCR_EL3", 0b11, 0b110, 0b0001, 0b0011, 0b001>; +def : RWSysReg<"TTBR0_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b000>; +def : RWSysReg<"TTBR0_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000>; +def : RWSysReg<"TTBR0_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b000>; +def : RWSysReg<"TTBR1_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b001>; +def : RWSysReg<"TCR_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b010>; +def : RWSysReg<"TCR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b010>; +def : RWSysReg<"TCR_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b010>; +def : RWSysReg<"VTTBR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b000>; +def : RWSysReg<"VTCR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b010>; +def : RWSysReg<"DACR32_EL2", 0b11, 0b100, 0b0011, 0b0000, 0b000>; +def : RWSysReg<"SPSR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b000>; +def : RWSysReg<"SPSR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b000>; +def : RWSysReg<"SPSR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b000>; +def : RWSysReg<"ELR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b001>; +def : RWSysReg<"ELR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b001>; +def : RWSysReg<"ELR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b001>; +def : RWSysReg<"SP_EL0", 0b11, 0b000, 0b0100, 0b0001, 0b000>; +def : RWSysReg<"SP_EL1", 0b11, 0b100, 0b0100, 0b0001, 0b000>; +def : RWSysReg<"SP_EL2", 0b11, 0b110, 0b0100, 0b0001, 0b000>; +def : RWSysReg<"SPSel", 0b11, 0b000, 0b0100, 0b0010, 0b000>; +def : RWSysReg<"NZCV", 0b11, 0b011, 0b0100, 0b0010, 0b000>; +def : RWSysReg<"DAIF", 0b11, 0b011, 0b0100, 0b0010, 0b001>; +def : RWSysReg<"CurrentEL", 0b11, 0b000, 0b0100, 0b0010, 0b010>; +def : RWSysReg<"SPSR_irq", 0b11, 0b100, 0b0100, 0b0011, 0b000>; +def : RWSysReg<"SPSR_abt", 0b11, 0b100, 0b0100, 0b0011, 0b001>; +def : RWSysReg<"SPSR_und", 0b11, 0b100, 0b0100, 0b0011, 0b010>; +def : RWSysReg<"SPSR_fiq", 0b11, 0b100, 0b0100, 0b0011, 0b011>; +def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>; +def : RWSysReg<"FPSR", 0b11, 0b011, 0b0100, 0b0100, 0b001>; +def : RWSysReg<"DSPSR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b000>; +def : RWSysReg<"DLR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b001>; +def : RWSysReg<"IFSR32_EL2", 0b11, 0b100, 0b0101, 0b0000, 0b001>; +def : RWSysReg<"AFSR0_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b000>; +def : RWSysReg<"AFSR0_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b000>; +def : RWSysReg<"AFSR0_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b000>; +def : RWSysReg<"AFSR1_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b001>; +def : RWSysReg<"AFSR1_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b001>; +def : RWSysReg<"AFSR1_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b001>; +def : RWSysReg<"ESR_EL1", 0b11, 0b000, 0b0101, 0b0010, 0b000>; +def : RWSysReg<"ESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b000>; +def : RWSysReg<"ESR_EL3", 0b11, 0b110, 0b0101, 0b0010, 0b000>; +def : RWSysReg<"FPEXC32_EL2", 0b11, 0b100, 0b0101, 0b0011, 0b000>; +def : RWSysReg<"FAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b000>; +def : RWSysReg<"FAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b000>; +def : RWSysReg<"FAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b000>; +def : RWSysReg<"HPFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b100>; +def : RWSysReg<"PAR_EL1", 0b11, 0b000, 0b0111, 0b0100, 0b000>; +def : RWSysReg<"PMCR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b000>; +def : RWSysReg<"PMCNTENSET_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b001>; +def : RWSysReg<"PMCNTENCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b010>; +def : RWSysReg<"PMOVSCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b011>; +def : RWSysReg<"PMSELR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b101>; +def : RWSysReg<"PMCCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b000>; +def : RWSysReg<"PMXEVTYPER_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b001>; +def : RWSysReg<"PMXEVCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b010>; +def : RWSysReg<"PMUSERENR_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b000>; +def : RWSysReg<"PMINTENSET_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b001>; +def : RWSysReg<"PMINTENCLR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b010>; +def : RWSysReg<"PMOVSSET_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b011>; +def : RWSysReg<"MAIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b000>; +def : RWSysReg<"MAIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b000>; +def : RWSysReg<"MAIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b000>; +def : RWSysReg<"AMAIR_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b000>; +def : RWSysReg<"AMAIR_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b000>; +def : RWSysReg<"AMAIR_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b000>; +def : RWSysReg<"VBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b000>; +def : RWSysReg<"VBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b000>; +def : RWSysReg<"VBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b000>; +def : RWSysReg<"RMR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b010>; +def : RWSysReg<"RMR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b010>; +def : RWSysReg<"RMR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b010>; +def : RWSysReg<"CONTEXTIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b001>; +def : RWSysReg<"TPIDR_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b010>; +def : RWSysReg<"TPIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b010>; +def : RWSysReg<"TPIDR_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b010>; +def : RWSysReg<"TPIDRRO_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b011>; +def : RWSysReg<"TPIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b100>; +def : RWSysReg<"CNTFRQ_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b000>; +def : RWSysReg<"CNTVOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b011>; +def : RWSysReg<"CNTKCTL_EL1", 0b11, 0b000, 0b1110, 0b0001, 0b000>; +def : RWSysReg<"CNTHCTL_EL2", 0b11, 0b100, 0b1110, 0b0001, 0b000>; +def : RWSysReg<"CNTP_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b000>; +def : RWSysReg<"CNTHP_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b000>; +def : RWSysReg<"CNTPS_TVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b000>; +def : RWSysReg<"CNTP_CTL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b001>; +def : RWSysReg<"CNTHP_CTL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b001>; +def : RWSysReg<"CNTPS_CTL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b001>; +def : RWSysReg<"CNTP_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b010>; +def : RWSysReg<"CNTHP_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b010>; +def : RWSysReg<"CNTPS_CVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b010>; +def : RWSysReg<"CNTV_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b000>; +def : RWSysReg<"CNTV_CTL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b001>; +def : RWSysReg<"CNTV_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b010>; +def : RWSysReg<"PMEVCNTR0_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b000>; +def : RWSysReg<"PMEVCNTR1_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b001>; +def : RWSysReg<"PMEVCNTR2_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b010>; +def : RWSysReg<"PMEVCNTR3_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b011>; +def : RWSysReg<"PMEVCNTR4_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b100>; +def : RWSysReg<"PMEVCNTR5_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b101>; +def : RWSysReg<"PMEVCNTR6_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b110>; +def : RWSysReg<"PMEVCNTR7_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b111>; +def : RWSysReg<"PMEVCNTR8_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b000>; +def : RWSysReg<"PMEVCNTR9_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b001>; +def : RWSysReg<"PMEVCNTR10_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b010>; +def : RWSysReg<"PMEVCNTR11_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b011>; +def : RWSysReg<"PMEVCNTR12_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b100>; +def : RWSysReg<"PMEVCNTR13_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b101>; +def : RWSysReg<"PMEVCNTR14_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b110>; +def : RWSysReg<"PMEVCNTR15_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b111>; +def : RWSysReg<"PMEVCNTR16_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b000>; +def : RWSysReg<"PMEVCNTR17_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b001>; +def : RWSysReg<"PMEVCNTR18_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b010>; +def : RWSysReg<"PMEVCNTR19_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b011>; +def : RWSysReg<"PMEVCNTR20_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b100>; +def : RWSysReg<"PMEVCNTR21_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b101>; +def : RWSysReg<"PMEVCNTR22_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b110>; +def : RWSysReg<"PMEVCNTR23_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b111>; +def : RWSysReg<"PMEVCNTR24_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b000>; +def : RWSysReg<"PMEVCNTR25_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b001>; +def : RWSysReg<"PMEVCNTR26_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b010>; +def : RWSysReg<"PMEVCNTR27_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b011>; +def : RWSysReg<"PMEVCNTR28_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b100>; +def : RWSysReg<"PMEVCNTR29_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b101>; +def : RWSysReg<"PMEVCNTR30_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b110>; +def : RWSysReg<"PMCCFILTR_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b111>; +def : RWSysReg<"PMEVTYPER0_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b000>; +def : RWSysReg<"PMEVTYPER1_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b001>; +def : RWSysReg<"PMEVTYPER2_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b010>; +def : RWSysReg<"PMEVTYPER3_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b011>; +def : RWSysReg<"PMEVTYPER4_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b100>; +def : RWSysReg<"PMEVTYPER5_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b101>; +def : RWSysReg<"PMEVTYPER6_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b110>; +def : RWSysReg<"PMEVTYPER7_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b111>; +def : RWSysReg<"PMEVTYPER8_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b000>; +def : RWSysReg<"PMEVTYPER9_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b001>; +def : RWSysReg<"PMEVTYPER10_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b010>; +def : RWSysReg<"PMEVTYPER11_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b011>; +def : RWSysReg<"PMEVTYPER12_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b100>; +def : RWSysReg<"PMEVTYPER13_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b101>; +def : RWSysReg<"PMEVTYPER14_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b110>; +def : RWSysReg<"PMEVTYPER15_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b111>; +def : RWSysReg<"PMEVTYPER16_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b000>; +def : RWSysReg<"PMEVTYPER17_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b001>; +def : RWSysReg<"PMEVTYPER18_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b010>; +def : RWSysReg<"PMEVTYPER19_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b011>; +def : RWSysReg<"PMEVTYPER20_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b100>; +def : RWSysReg<"PMEVTYPER21_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b101>; +def : RWSysReg<"PMEVTYPER22_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b110>; +def : RWSysReg<"PMEVTYPER23_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b111>; +def : RWSysReg<"PMEVTYPER24_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b000>; +def : RWSysReg<"PMEVTYPER25_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b001>; +def : RWSysReg<"PMEVTYPER26_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b010>; +def : RWSysReg<"PMEVTYPER27_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b011>; +def : RWSysReg<"PMEVTYPER28_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b100>; +def : RWSysReg<"PMEVTYPER29_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b101>; +def : RWSysReg<"PMEVTYPER30_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b110>; + +// Trace registers +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"TRCPRGCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b000>; +def : RWSysReg<"TRCPROCSELR", 0b10, 0b001, 0b0000, 0b0010, 0b000>; +def : RWSysReg<"TRCCONFIGR", 0b10, 0b001, 0b0000, 0b0100, 0b000>; +def : RWSysReg<"TRCAUXCTLR", 0b10, 0b001, 0b0000, 0b0110, 0b000>; +def : RWSysReg<"TRCEVENTCTL0R", 0b10, 0b001, 0b0000, 0b1000, 0b000>; +def : RWSysReg<"TRCEVENTCTL1R", 0b10, 0b001, 0b0000, 0b1001, 0b000>; +def : RWSysReg<"TRCSTALLCTLR", 0b10, 0b001, 0b0000, 0b1011, 0b000>; +def : RWSysReg<"TRCTSCTLR", 0b10, 0b001, 0b0000, 0b1100, 0b000>; +def : RWSysReg<"TRCSYNCPR", 0b10, 0b001, 0b0000, 0b1101, 0b000>; +def : RWSysReg<"TRCCCCTLR", 0b10, 0b001, 0b0000, 0b1110, 0b000>; +def : RWSysReg<"TRCBBCTLR", 0b10, 0b001, 0b0000, 0b1111, 0b000>; +def : RWSysReg<"TRCTRACEIDR", 0b10, 0b001, 0b0000, 0b0000, 0b001>; +def : RWSysReg<"TRCQCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b001>; +def : RWSysReg<"TRCVICTLR", 0b10, 0b001, 0b0000, 0b0000, 0b010>; +def : RWSysReg<"TRCVIIECTLR", 0b10, 0b001, 0b0000, 0b0001, 0b010>; +def : RWSysReg<"TRCVISSCTLR", 0b10, 0b001, 0b0000, 0b0010, 0b010>; +def : RWSysReg<"TRCVIPCSSCTLR", 0b10, 0b001, 0b0000, 0b0011, 0b010>; +def : RWSysReg<"TRCVDCTLR", 0b10, 0b001, 0b0000, 0b1000, 0b010>; +def : RWSysReg<"TRCVDSACCTLR", 0b10, 0b001, 0b0000, 0b1001, 0b010>; +def : RWSysReg<"TRCVDARCCTLR", 0b10, 0b001, 0b0000, 0b1010, 0b010>; +def : RWSysReg<"TRCSEQEVR0", 0b10, 0b001, 0b0000, 0b0000, 0b100>; +def : RWSysReg<"TRCSEQEVR1", 0b10, 0b001, 0b0000, 0b0001, 0b100>; +def : RWSysReg<"TRCSEQEVR2", 0b10, 0b001, 0b0000, 0b0010, 0b100>; +def : RWSysReg<"TRCSEQRSTEVR", 0b10, 0b001, 0b0000, 0b0110, 0b100>; +def : RWSysReg<"TRCSEQSTR", 0b10, 0b001, 0b0000, 0b0111, 0b100>; +def : RWSysReg<"TRCEXTINSELR", 0b10, 0b001, 0b0000, 0b1000, 0b100>; +def : RWSysReg<"TRCCNTRLDVR0", 0b10, 0b001, 0b0000, 0b0000, 0b101>; +def : RWSysReg<"TRCCNTRLDVR1", 0b10, 0b001, 0b0000, 0b0001, 0b101>; +def : RWSysReg<"TRCCNTRLDVR2", 0b10, 0b001, 0b0000, 0b0010, 0b101>; +def : RWSysReg<"TRCCNTRLDVR3", 0b10, 0b001, 0b0000, 0b0011, 0b101>; +def : RWSysReg<"TRCCNTCTLR0", 0b10, 0b001, 0b0000, 0b0100, 0b101>; +def : RWSysReg<"TRCCNTCTLR1", 0b10, 0b001, 0b0000, 0b0101, 0b101>; +def : RWSysReg<"TRCCNTCTLR2", 0b10, 0b001, 0b0000, 0b0110, 0b101>; +def : RWSysReg<"TRCCNTCTLR3", 0b10, 0b001, 0b0000, 0b0111, 0b101>; +def : RWSysReg<"TRCCNTVR0", 0b10, 0b001, 0b0000, 0b1000, 0b101>; +def : RWSysReg<"TRCCNTVR1", 0b10, 0b001, 0b0000, 0b1001, 0b101>; +def : RWSysReg<"TRCCNTVR2", 0b10, 0b001, 0b0000, 0b1010, 0b101>; +def : RWSysReg<"TRCCNTVR3", 0b10, 0b001, 0b0000, 0b1011, 0b101>; +def : RWSysReg<"TRCIMSPEC0", 0b10, 0b001, 0b0000, 0b0000, 0b111>; +def : RWSysReg<"TRCIMSPEC1", 0b10, 0b001, 0b0000, 0b0001, 0b111>; +def : RWSysReg<"TRCIMSPEC2", 0b10, 0b001, 0b0000, 0b0010, 0b111>; +def : RWSysReg<"TRCIMSPEC3", 0b10, 0b001, 0b0000, 0b0011, 0b111>; +def : RWSysReg<"TRCIMSPEC4", 0b10, 0b001, 0b0000, 0b0100, 0b111>; +def : RWSysReg<"TRCIMSPEC5", 0b10, 0b001, 0b0000, 0b0101, 0b111>; +def : RWSysReg<"TRCIMSPEC6", 0b10, 0b001, 0b0000, 0b0110, 0b111>; +def : RWSysReg<"TRCIMSPEC7", 0b10, 0b001, 0b0000, 0b0111, 0b111>; +def : RWSysReg<"TRCRSCTLR2", 0b10, 0b001, 0b0001, 0b0010, 0b000>; +def : RWSysReg<"TRCRSCTLR3", 0b10, 0b001, 0b0001, 0b0011, 0b000>; +def : RWSysReg<"TRCRSCTLR4", 0b10, 0b001, 0b0001, 0b0100, 0b000>; +def : RWSysReg<"TRCRSCTLR5", 0b10, 0b001, 0b0001, 0b0101, 0b000>; +def : RWSysReg<"TRCRSCTLR6", 0b10, 0b001, 0b0001, 0b0110, 0b000>; +def : RWSysReg<"TRCRSCTLR7", 0b10, 0b001, 0b0001, 0b0111, 0b000>; +def : RWSysReg<"TRCRSCTLR8", 0b10, 0b001, 0b0001, 0b1000, 0b000>; +def : RWSysReg<"TRCRSCTLR9", 0b10, 0b001, 0b0001, 0b1001, 0b000>; +def : RWSysReg<"TRCRSCTLR10", 0b10, 0b001, 0b0001, 0b1010, 0b000>; +def : RWSysReg<"TRCRSCTLR11", 0b10, 0b001, 0b0001, 0b1011, 0b000>; +def : RWSysReg<"TRCRSCTLR12", 0b10, 0b001, 0b0001, 0b1100, 0b000>; +def : RWSysReg<"TRCRSCTLR13", 0b10, 0b001, 0b0001, 0b1101, 0b000>; +def : RWSysReg<"TRCRSCTLR14", 0b10, 0b001, 0b0001, 0b1110, 0b000>; +def : RWSysReg<"TRCRSCTLR15", 0b10, 0b001, 0b0001, 0b1111, 0b000>; +def : RWSysReg<"TRCRSCTLR16", 0b10, 0b001, 0b0001, 0b0000, 0b001>; +def : RWSysReg<"TRCRSCTLR17", 0b10, 0b001, 0b0001, 0b0001, 0b001>; +def : RWSysReg<"TRCRSCTLR18", 0b10, 0b001, 0b0001, 0b0010, 0b001>; +def : RWSysReg<"TRCRSCTLR19", 0b10, 0b001, 0b0001, 0b0011, 0b001>; +def : RWSysReg<"TRCRSCTLR20", 0b10, 0b001, 0b0001, 0b0100, 0b001>; +def : RWSysReg<"TRCRSCTLR21", 0b10, 0b001, 0b0001, 0b0101, 0b001>; +def : RWSysReg<"TRCRSCTLR22", 0b10, 0b001, 0b0001, 0b0110, 0b001>; +def : RWSysReg<"TRCRSCTLR23", 0b10, 0b001, 0b0001, 0b0111, 0b001>; +def : RWSysReg<"TRCRSCTLR24", 0b10, 0b001, 0b0001, 0b1000, 0b001>; +def : RWSysReg<"TRCRSCTLR25", 0b10, 0b001, 0b0001, 0b1001, 0b001>; +def : RWSysReg<"TRCRSCTLR26", 0b10, 0b001, 0b0001, 0b1010, 0b001>; +def : RWSysReg<"TRCRSCTLR27", 0b10, 0b001, 0b0001, 0b1011, 0b001>; +def : RWSysReg<"TRCRSCTLR28", 0b10, 0b001, 0b0001, 0b1100, 0b001>; +def : RWSysReg<"TRCRSCTLR29", 0b10, 0b001, 0b0001, 0b1101, 0b001>; +def : RWSysReg<"TRCRSCTLR30", 0b10, 0b001, 0b0001, 0b1110, 0b001>; +def : RWSysReg<"TRCRSCTLR31", 0b10, 0b001, 0b0001, 0b1111, 0b001>; +def : RWSysReg<"TRCSSCCR0", 0b10, 0b001, 0b0001, 0b0000, 0b010>; +def : RWSysReg<"TRCSSCCR1", 0b10, 0b001, 0b0001, 0b0001, 0b010>; +def : RWSysReg<"TRCSSCCR2", 0b10, 0b001, 0b0001, 0b0010, 0b010>; +def : RWSysReg<"TRCSSCCR3", 0b10, 0b001, 0b0001, 0b0011, 0b010>; +def : RWSysReg<"TRCSSCCR4", 0b10, 0b001, 0b0001, 0b0100, 0b010>; +def : RWSysReg<"TRCSSCCR5", 0b10, 0b001, 0b0001, 0b0101, 0b010>; +def : RWSysReg<"TRCSSCCR6", 0b10, 0b001, 0b0001, 0b0110, 0b010>; +def : RWSysReg<"TRCSSCCR7", 0b10, 0b001, 0b0001, 0b0111, 0b010>; +def : RWSysReg<"TRCSSCSR0", 0b10, 0b001, 0b0001, 0b1000, 0b010>; +def : RWSysReg<"TRCSSCSR1", 0b10, 0b001, 0b0001, 0b1001, 0b010>; +def : RWSysReg<"TRCSSCSR2", 0b10, 0b001, 0b0001, 0b1010, 0b010>; +def : RWSysReg<"TRCSSCSR3", 0b10, 0b001, 0b0001, 0b1011, 0b010>; +def : RWSysReg<"TRCSSCSR4", 0b10, 0b001, 0b0001, 0b1100, 0b010>; +def : RWSysReg<"TRCSSCSR5", 0b10, 0b001, 0b0001, 0b1101, 0b010>; +def : RWSysReg<"TRCSSCSR6", 0b10, 0b001, 0b0001, 0b1110, 0b010>; +def : RWSysReg<"TRCSSCSR7", 0b10, 0b001, 0b0001, 0b1111, 0b010>; +def : RWSysReg<"TRCSSPCICR0", 0b10, 0b001, 0b0001, 0b0000, 0b011>; +def : RWSysReg<"TRCSSPCICR1", 0b10, 0b001, 0b0001, 0b0001, 0b011>; +def : RWSysReg<"TRCSSPCICR2", 0b10, 0b001, 0b0001, 0b0010, 0b011>; +def : RWSysReg<"TRCSSPCICR3", 0b10, 0b001, 0b0001, 0b0011, 0b011>; +def : RWSysReg<"TRCSSPCICR4", 0b10, 0b001, 0b0001, 0b0100, 0b011>; +def : RWSysReg<"TRCSSPCICR5", 0b10, 0b001, 0b0001, 0b0101, 0b011>; +def : RWSysReg<"TRCSSPCICR6", 0b10, 0b001, 0b0001, 0b0110, 0b011>; +def : RWSysReg<"TRCSSPCICR7", 0b10, 0b001, 0b0001, 0b0111, 0b011>; +def : RWSysReg<"TRCPDCR", 0b10, 0b001, 0b0001, 0b0100, 0b100>; +def : RWSysReg<"TRCACVR0", 0b10, 0b001, 0b0010, 0b0000, 0b000>; +def : RWSysReg<"TRCACVR1", 0b10, 0b001, 0b0010, 0b0010, 0b000>; +def : RWSysReg<"TRCACVR2", 0b10, 0b001, 0b0010, 0b0100, 0b000>; +def : RWSysReg<"TRCACVR3", 0b10, 0b001, 0b0010, 0b0110, 0b000>; +def : RWSysReg<"TRCACVR4", 0b10, 0b001, 0b0010, 0b1000, 0b000>; +def : RWSysReg<"TRCACVR5", 0b10, 0b001, 0b0010, 0b1010, 0b000>; +def : RWSysReg<"TRCACVR6", 0b10, 0b001, 0b0010, 0b1100, 0b000>; +def : RWSysReg<"TRCACVR7", 0b10, 0b001, 0b0010, 0b1110, 0b000>; +def : RWSysReg<"TRCACVR8", 0b10, 0b001, 0b0010, 0b0000, 0b001>; +def : RWSysReg<"TRCACVR9", 0b10, 0b001, 0b0010, 0b0010, 0b001>; +def : RWSysReg<"TRCACVR10", 0b10, 0b001, 0b0010, 0b0100, 0b001>; +def : RWSysReg<"TRCACVR11", 0b10, 0b001, 0b0010, 0b0110, 0b001>; +def : RWSysReg<"TRCACVR12", 0b10, 0b001, 0b0010, 0b1000, 0b001>; +def : RWSysReg<"TRCACVR13", 0b10, 0b001, 0b0010, 0b1010, 0b001>; +def : RWSysReg<"TRCACVR14", 0b10, 0b001, 0b0010, 0b1100, 0b001>; +def : RWSysReg<"TRCACVR15", 0b10, 0b001, 0b0010, 0b1110, 0b001>; +def : RWSysReg<"TRCACATR0", 0b10, 0b001, 0b0010, 0b0000, 0b010>; +def : RWSysReg<"TRCACATR1", 0b10, 0b001, 0b0010, 0b0010, 0b010>; +def : RWSysReg<"TRCACATR2", 0b10, 0b001, 0b0010, 0b0100, 0b010>; +def : RWSysReg<"TRCACATR3", 0b10, 0b001, 0b0010, 0b0110, 0b010>; +def : RWSysReg<"TRCACATR4", 0b10, 0b001, 0b0010, 0b1000, 0b010>; +def : RWSysReg<"TRCACATR5", 0b10, 0b001, 0b0010, 0b1010, 0b010>; +def : RWSysReg<"TRCACATR6", 0b10, 0b001, 0b0010, 0b1100, 0b010>; +def : RWSysReg<"TRCACATR7", 0b10, 0b001, 0b0010, 0b1110, 0b010>; +def : RWSysReg<"TRCACATR8", 0b10, 0b001, 0b0010, 0b0000, 0b011>; +def : RWSysReg<"TRCACATR9", 0b10, 0b001, 0b0010, 0b0010, 0b011>; +def : RWSysReg<"TRCACATR10", 0b10, 0b001, 0b0010, 0b0100, 0b011>; +def : RWSysReg<"TRCACATR11", 0b10, 0b001, 0b0010, 0b0110, 0b011>; +def : RWSysReg<"TRCACATR12", 0b10, 0b001, 0b0010, 0b1000, 0b011>; +def : RWSysReg<"TRCACATR13", 0b10, 0b001, 0b0010, 0b1010, 0b011>; +def : RWSysReg<"TRCACATR14", 0b10, 0b001, 0b0010, 0b1100, 0b011>; +def : RWSysReg<"TRCACATR15", 0b10, 0b001, 0b0010, 0b1110, 0b011>; +def : RWSysReg<"TRCDVCVR0", 0b10, 0b001, 0b0010, 0b0000, 0b100>; +def : RWSysReg<"TRCDVCVR1", 0b10, 0b001, 0b0010, 0b0100, 0b100>; +def : RWSysReg<"TRCDVCVR2", 0b10, 0b001, 0b0010, 0b1000, 0b100>; +def : RWSysReg<"TRCDVCVR3", 0b10, 0b001, 0b0010, 0b1100, 0b100>; +def : RWSysReg<"TRCDVCVR4", 0b10, 0b001, 0b0010, 0b0000, 0b101>; +def : RWSysReg<"TRCDVCVR5", 0b10, 0b001, 0b0010, 0b0100, 0b101>; +def : RWSysReg<"TRCDVCVR6", 0b10, 0b001, 0b0010, 0b1000, 0b101>; +def : RWSysReg<"TRCDVCVR7", 0b10, 0b001, 0b0010, 0b1100, 0b101>; +def : RWSysReg<"TRCDVCMR0", 0b10, 0b001, 0b0010, 0b0000, 0b110>; +def : RWSysReg<"TRCDVCMR1", 0b10, 0b001, 0b0010, 0b0100, 0b110>; +def : RWSysReg<"TRCDVCMR2", 0b10, 0b001, 0b0010, 0b1000, 0b110>; +def : RWSysReg<"TRCDVCMR3", 0b10, 0b001, 0b0010, 0b1100, 0b110>; +def : RWSysReg<"TRCDVCMR4", 0b10, 0b001, 0b0010, 0b0000, 0b111>; +def : RWSysReg<"TRCDVCMR5", 0b10, 0b001, 0b0010, 0b0100, 0b111>; +def : RWSysReg<"TRCDVCMR6", 0b10, 0b001, 0b0010, 0b1000, 0b111>; +def : RWSysReg<"TRCDVCMR7", 0b10, 0b001, 0b0010, 0b1100, 0b111>; +def : RWSysReg<"TRCCIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b000>; +def : RWSysReg<"TRCCIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b000>; +def : RWSysReg<"TRCCIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b000>; +def : RWSysReg<"TRCCIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b000>; +def : RWSysReg<"TRCCIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b000>; +def : RWSysReg<"TRCCIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b000>; +def : RWSysReg<"TRCCIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b000>; +def : RWSysReg<"TRCCIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b000>; +def : RWSysReg<"TRCVMIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b001>; +def : RWSysReg<"TRCVMIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b001>; +def : RWSysReg<"TRCVMIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b001>; +def : RWSysReg<"TRCVMIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b001>; +def : RWSysReg<"TRCVMIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b001>; +def : RWSysReg<"TRCVMIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b001>; +def : RWSysReg<"TRCVMIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b001>; +def : RWSysReg<"TRCVMIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b001>; +def : RWSysReg<"TRCCIDCCTLR0", 0b10, 0b001, 0b0011, 0b0000, 0b010>; +def : RWSysReg<"TRCCIDCCTLR1", 0b10, 0b001, 0b0011, 0b0001, 0b010>; +def : RWSysReg<"TRCVMIDCCTLR0", 0b10, 0b001, 0b0011, 0b0010, 0b010>; +def : RWSysReg<"TRCVMIDCCTLR1", 0b10, 0b001, 0b0011, 0b0011, 0b010>; +def : RWSysReg<"TRCITCTRL", 0b10, 0b001, 0b0111, 0b0000, 0b100>; +def : RWSysReg<"TRCCLAIMSET", 0b10, 0b001, 0b0111, 0b1000, 0b110>; +def : RWSysReg<"TRCCLAIMCLR", 0b10, 0b001, 0b0111, 0b1001, 0b110>; + +// GICv3 registers +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"ICC_BPR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b011>; +def : RWSysReg<"ICC_BPR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b011>; +def : RWSysReg<"ICC_PMR_EL1", 0b11, 0b000, 0b0100, 0b0110, 0b000>; +def : RWSysReg<"ICC_CTLR_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b100>; +def : RWSysReg<"ICC_CTLR_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b100>; +def : RWSysReg<"ICC_SRE_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b101>; +def : RWSysReg<"ICC_SRE_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b101>; +def : RWSysReg<"ICC_SRE_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b101>; +def : RWSysReg<"ICC_IGRPEN0_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b110>; +def : RWSysReg<"ICC_IGRPEN1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b111>; +def : RWSysReg<"ICC_IGRPEN1_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b111>; +def : RWSysReg<"ICC_SEIEN_EL1", 0b11, 0b000, 0b1100, 0b1101, 0b000>; +def : RWSysReg<"ICC_AP0R0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b100>; +def : RWSysReg<"ICC_AP0R1_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b101>; +def : RWSysReg<"ICC_AP0R2_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b110>; +def : RWSysReg<"ICC_AP0R3_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b111>; +def : RWSysReg<"ICC_AP1R0_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b000>; +def : RWSysReg<"ICC_AP1R1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b001>; +def : RWSysReg<"ICC_AP1R2_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b010>; +def : RWSysReg<"ICC_AP1R3_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b011>; +def : RWSysReg<"ICH_AP0R0_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b000>; +def : RWSysReg<"ICH_AP0R1_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b001>; +def : RWSysReg<"ICH_AP0R2_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b010>; +def : RWSysReg<"ICH_AP0R3_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b011>; +def : RWSysReg<"ICH_AP1R0_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b000>; +def : RWSysReg<"ICH_AP1R1_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b001>; +def : RWSysReg<"ICH_AP1R2_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b010>; +def : RWSysReg<"ICH_AP1R3_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b011>; +def : RWSysReg<"ICH_HCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b000>; +def : RWSysReg<"ICH_MISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b010>; +def : RWSysReg<"ICH_VMCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b111>; +def : RWSysReg<"ICH_VSEIR_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b100>; +def : RWSysReg<"ICH_LR0_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b000>; +def : RWSysReg<"ICH_LR1_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b001>; +def : RWSysReg<"ICH_LR2_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b010>; +def : RWSysReg<"ICH_LR3_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b011>; +def : RWSysReg<"ICH_LR4_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b100>; +def : RWSysReg<"ICH_LR5_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b101>; +def : RWSysReg<"ICH_LR6_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b110>; +def : RWSysReg<"ICH_LR7_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b111>; +def : RWSysReg<"ICH_LR8_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b000>; +def : RWSysReg<"ICH_LR9_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b001>; +def : RWSysReg<"ICH_LR10_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b010>; +def : RWSysReg<"ICH_LR11_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b011>; +def : RWSysReg<"ICH_LR12_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b100>; +def : RWSysReg<"ICH_LR13_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b101>; +def : RWSysReg<"ICH_LR14_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b110>; +def : RWSysReg<"ICH_LR15_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b111>; + +// v8.1a "Privileged Access Never" extension-specific system registers +let Requires = [{ {AArch64::HasV8_1aOps} }] in +def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>; + +// v8.1a "Limited Ordering Regions" extension-specific system registers +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::HasV8_1aOps} }] in { +def : RWSysReg<"LORSA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b000>; +def : RWSysReg<"LOREA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b001>; +def : RWSysReg<"LORN_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b010>; +def : RWSysReg<"LORC_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b011>; +} + +// v8.1a "Virtualization hos extensions" system registers +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::HasV8_1aOps} }] in { +def : RWSysReg<"TTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b001>; +def : RWSysReg<"CONTEXTIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b001>; +def : RWSysReg<"CNTHV_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b000>; +def : RWSysReg<"CNTHV_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b010>; +def : RWSysReg<"CNTHV_CTL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b001>; +def : RWSysReg<"SCTLR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b000>; +def : RWSysReg<"CPACR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b010>; +def : RWSysReg<"TTBR0_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b000>; +def : RWSysReg<"TTBR1_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b001>; +def : RWSysReg<"TCR_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b010>; +def : RWSysReg<"AFSR0_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b000>; +def : RWSysReg<"AFSR1_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b001>; +def : RWSysReg<"ESR_EL12", 0b11, 0b101, 0b0101, 0b0010, 0b000>; +def : RWSysReg<"FAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b000>; +def : RWSysReg<"MAIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b000>; +def : RWSysReg<"AMAIR_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b000>; +def : RWSysReg<"VBAR_EL12", 0b11, 0b101, 0b1100, 0b0000, 0b000>; +def : RWSysReg<"CONTEXTIDR_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b001>; +def : RWSysReg<"CNTKCTL_EL12", 0b11, 0b101, 0b1110, 0b0001, 0b000>; +def : RWSysReg<"CNTP_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b000>; +def : RWSysReg<"CNTP_CTL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b001>; +def : RWSysReg<"CNTP_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b010>; +def : RWSysReg<"CNTV_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b000>; +def : RWSysReg<"CNTV_CTL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b001>; +def : RWSysReg<"CNTV_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b010>; +def : RWSysReg<"SPSR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b000>; +def : RWSysReg<"ELR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b001>; +} +// v8.2a registers +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::HasV8_2aOps} }] in +def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>; + +// v8.2a "Statistical Profiling extension" registers +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeatureSPE} }] in { +def : RWSysReg<"PMBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b000>; +def : RWSysReg<"PMBPTR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b001>; +def : RWSysReg<"PMBSR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b011>; +def : RWSysReg<"PMBIDR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b111>; +def : RWSysReg<"PMSCR_EL2", 0b11, 0b100, 0b1001, 0b1001, 0b000>; +def : RWSysReg<"PMSCR_EL12", 0b11, 0b101, 0b1001, 0b1001, 0b000>; +def : RWSysReg<"PMSCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b000>; +def : RWSysReg<"PMSICR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b010>; +def : RWSysReg<"PMSIRR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b011>; +def : RWSysReg<"PMSFCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b100>; +def : RWSysReg<"PMSEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b101>; +def : RWSysReg<"PMSLATFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b110>; +def : RWSysReg<"PMSIDR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b111>; +} + +// v8.2a "RAS extension" registers +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeatureRAS} }] in { +def : RWSysReg<"ERRSELR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b001>; +def : RWSysReg<"ERXCTLR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b001>; +def : RWSysReg<"ERXSTATUS_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b010>; +def : RWSysReg<"ERXADDR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b011>; +def : RWSysReg<"ERXMISC0_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b000>; +def : RWSysReg<"ERXMISC1_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b001>; +def : RWSysReg<"DISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b001>; +def : RWSysReg<"VDISR_EL2", 0b11, 0b100, 0b1100, 0b0001, 0b001>; +def : RWSysReg<"VSESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b011>; +} + +// Cyclone specific system registers +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::ProcCyclone} }] in +def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>; diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 432c7217c132..aebc370333e3 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -2073,12 +2073,9 @@ AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) { return MatchOperand_ParseFail; } - bool Valid; - auto Mapper = AArch64PRFM::PRFMMapper(); - StringRef Name = - Mapper.toString(MCE->getValue(), getSTI().getFeatureBits(), Valid); - Operands.push_back(AArch64Operand::CreatePrefetch(prfop, Name, - S, getContext())); + auto PRFM = AArch64PRFM::lookupPRFMByEncoding(MCE->getValue()); + Operands.push_back(AArch64Operand::CreatePrefetch( + prfop, PRFM ? PRFM->Name : "", S, getContext())); return MatchOperand_Success; } @@ -2087,18 +2084,15 @@ AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) { return MatchOperand_ParseFail; } - bool Valid; - auto Mapper = AArch64PRFM::PRFMMapper(); - unsigned prfop = - Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid); - if (!Valid) { + auto PRFM = AArch64PRFM::lookupPRFMByName(Tok.getString()); + if (!PRFM) { TokError("pre-fetch hint expected"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat identifier token. - Operands.push_back(AArch64Operand::CreatePrefetch(prfop, Tok.getString(), - S, getContext())); + Operands.push_back(AArch64Operand::CreatePrefetch( + PRFM->Encoding, Tok.getString(), S, getContext())); return MatchOperand_Success; } @@ -2113,18 +2107,15 @@ AArch64AsmParser::tryParsePSBHint(OperandVector &Operands) { return MatchOperand_ParseFail; } - bool Valid; - auto Mapper = AArch64PSBHint::PSBHintMapper(); - unsigned psbhint = - Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid); - if (!Valid) { + auto PSB = AArch64PSBHint::lookupPSBByName(Tok.getString()); + if (!PSB) { TokError("invalid operand for instruction"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat identifier token. - Operands.push_back(AArch64Operand::CreatePSBHint(psbhint, Tok.getString(), - S, getContext())); + Operands.push_back(AArch64Operand::CreatePSBHint( + PSB->Encoding, Tok.getString(), S, getContext())); return MatchOperand_Success; } @@ -2748,12 +2739,9 @@ AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) { Error(ExprLoc, "barrier operand out of range"); return MatchOperand_ParseFail; } - bool Valid; - auto Mapper = AArch64DB::DBarrierMapper(); - StringRef Name = - Mapper.toString(MCE->getValue(), getSTI().getFeatureBits(), Valid); - Operands.push_back( AArch64Operand::CreateBarrier(MCE->getValue(), Name, - ExprLoc, getContext())); + auto DB = AArch64DB::lookupDBByEncoding(MCE->getValue()); + Operands.push_back(AArch64Operand::CreateBarrier( + MCE->getValue(), DB ? DB->Name : "", ExprLoc, getContext())); return MatchOperand_Success; } @@ -2762,23 +2750,20 @@ AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) { return MatchOperand_ParseFail; } - bool Valid; - auto Mapper = AArch64DB::DBarrierMapper(); - unsigned Opt = - Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid); - if (!Valid) { + auto DB = AArch64DB::lookupDBByName(Tok.getString()); + if (!DB) { TokError("invalid barrier option name"); return MatchOperand_ParseFail; } // The only valid named option for ISB is 'sy' - if (Mnemonic == "isb" && Opt != AArch64DB::SY) { + if (Mnemonic == "isb" && DB->Encoding != AArch64DB::sy) { TokError("'sy' or #imm operand expected"); return MatchOperand_ParseFail; } - Operands.push_back( AArch64Operand::CreateBarrier(Opt, Tok.getString(), - getLoc(), getContext())); + Operands.push_back(AArch64Operand::CreateBarrier( + DB->Encoding, Tok.getString(), getLoc(), getContext())); Parser.Lex(); // Consume the option return MatchOperand_Success; @@ -2792,28 +2777,22 @@ AArch64AsmParser::tryParseSysReg(OperandVector &Operands) { if (Tok.isNot(AsmToken::Identifier)) return MatchOperand_NoMatch; - bool IsKnown; - auto MRSMapper = AArch64SysReg::MRSMapper(); - uint32_t MRSReg = MRSMapper.fromString(Tok.getString(), - getSTI().getFeatureBits(), IsKnown); - assert(IsKnown == (MRSReg != -1U) && - "register should be -1 if and only if it's unknown"); + int MRSReg, MSRReg; + auto SysReg = AArch64SysReg::lookupSysRegByName(Tok.getString()); + if (SysReg && SysReg->haveFeatures(getSTI().getFeatureBits())) { + MRSReg = SysReg->Readable ? SysReg->Encoding : -1; + MSRReg = SysReg->Writeable ? SysReg->Encoding : -1; + } else + MRSReg = MSRReg = AArch64SysReg::parseGenericRegister(Tok.getString()); - auto MSRMapper = AArch64SysReg::MSRMapper(); - uint32_t MSRReg = MSRMapper.fromString(Tok.getString(), - getSTI().getFeatureBits(), IsKnown); - assert(IsKnown == (MSRReg != -1U) && - "register should be -1 if and only if it's unknown"); + auto PState = AArch64PState::lookupPStateByName(Tok.getString()); + unsigned PStateImm = -1; + if (PState && PState->haveFeatures(getSTI().getFeatureBits())) + PStateImm = PState->Encoding; - auto PStateMapper = AArch64PState::PStateMapper(); - uint32_t PStateField = - PStateMapper.fromString(Tok.getString(), - getSTI().getFeatureBits(), IsKnown); - assert(IsKnown == (PStateField != -1U) && - "register should be -1 if and only if it's unknown"); - - Operands.push_back(AArch64Operand::CreateSysReg( - Tok.getString(), getLoc(), MRSReg, MSRReg, PStateField, getContext())); + Operands.push_back( + AArch64Operand::CreateSysReg(Tok.getString(), getLoc(), MRSReg, MSRReg, + PStateImm, getContext())); Parser.Lex(); // Eat identifier return MatchOperand_Success; diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt b/llvm/lib/Target/AArch64/CMakeLists.txt index 4bbb7aed0b43..a79960ea9605 100644 --- a/llvm/lib/Target/AArch64/CMakeLists.txt +++ b/llvm/lib/Target/AArch64/CMakeLists.txt @@ -12,6 +12,8 @@ tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel) tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv) tablegen(LLVM AArch64GenSubtargetInfo.inc -gen-subtarget) tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler) +tablegen(LLVM AArch64GenSystemOperands.inc -gen-searchable-tables) + add_public_tablegen_target(AArch64CommonTableGen) # List of all GlobalISel files. diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index f1f968e73123..3ae713be1027 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -1523,13 +1523,12 @@ static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst, Inst.addOperand(MCOperand::createImm(pstate_field)); Inst.addOperand(MCOperand::createImm(crm)); - bool ValidNamed; - const AArch64Disassembler *Dis = + const AArch64Disassembler *Dis = static_cast(Decoder); - (void)AArch64PState::PStateMapper().toString(pstate_field, - Dis->getSubtargetInfo().getFeatureBits(), ValidNamed); - - return ValidNamed ? Success : Fail; + auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); + if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) + return Success; + return Fail; } static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn, diff --git a/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp index a3669cf18e73..b4f85204714f 100644 --- a/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp @@ -1191,11 +1191,9 @@ void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { unsigned prfop = MI->getOperand(OpNum).getImm(); - bool Valid; - StringRef Name = - AArch64PRFM::PRFMMapper().toString(prfop, STI.getFeatureBits(), Valid); - if (Valid) - O << Name; + auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop); + if (PRFM) + O << PRFM->Name; else O << '#' << formatImm(prfop); } @@ -1204,11 +1202,9 @@ void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { unsigned psbhintop = MI->getOperand(OpNum).getImm(); - bool Valid; - StringRef Name = - AArch64PSBHint::PSBHintMapper().toString(psbhintop, STI.getFeatureBits(), Valid); - if (Valid) - O << Name; + auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop); + if (PSB) + O << PSB->Name; else O << '#' << formatImm(psbhintop); } @@ -1404,15 +1400,15 @@ void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo, unsigned Val = MI->getOperand(OpNo).getImm(); unsigned Opcode = MI->getOpcode(); - bool Valid; StringRef Name; - if (Opcode == AArch64::ISB) - Name = AArch64ISB::ISBMapper().toString(Val, STI.getFeatureBits(), - Valid); - else - Name = AArch64DB::DBarrierMapper().toString(Val, STI.getFeatureBits(), - Valid); - if (Valid) + if (Opcode == AArch64::ISB) { + auto ISB = AArch64ISB::lookupISBByEncoding(Val); + Name = ISB ? ISB->Name : ""; + } else { + auto DB = AArch64DB::lookupDBByEncoding(Val); + Name = DB ? DB->Name : ""; + } + if (!Name.empty()) O << Name; else O << "#" << Val; @@ -1423,10 +1419,19 @@ void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo, raw_ostream &O) { unsigned Val = MI->getOperand(OpNo).getImm(); - auto Mapper = AArch64SysReg::MRSMapper(); - std::string Name = Mapper.toString(Val, STI.getFeatureBits()); + // Horrible hack for the one register that has identical encodings but + // different names in MSR and MRS. Because of this, one of MRS and MSR is + // going to get the wrong entry + if (Val == AArch64SysReg::DBGDTRRX_EL0) { + O << "DBGDTRRX_EL0"; + return; + } - O << StringRef(Name).upper(); + const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val); + if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits())) + O << Reg->Name; + else + O << AArch64SysReg::genericRegisterString(Val); } void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo, @@ -1434,10 +1439,19 @@ void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo, raw_ostream &O) { unsigned Val = MI->getOperand(OpNo).getImm(); - auto Mapper = AArch64SysReg::MSRMapper(); - std::string Name = Mapper.toString(Val, STI.getFeatureBits()); + // Horrible hack for the one register that has identical encodings but + // different names in MSR and MRS. Because of this, one of MRS and MSR is + // going to get the wrong entry + if (Val == AArch64SysReg::DBGDTRTX_EL0) { + O << "DBGDTRTX_EL0"; + return; + } - O << StringRef(Name).upper(); + const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val); + if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits())) + O << Reg->Name; + else + O << AArch64SysReg::genericRegisterString(Val); } void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo, @@ -1445,11 +1459,9 @@ void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo, raw_ostream &O) { unsigned Val = MI->getOperand(OpNo).getImm(); - bool Valid; - StringRef Name = - AArch64PState::PStateMapper().toString(Val, STI.getFeatureBits(), Valid); - if (Valid) - O << Name.upper(); + auto PState = AArch64PState::lookupPStateByEncoding(Val); + if (PState && PState->haveFeatures(STI.getFeatureBits())) + O << PState->Name; else O << "#" << formatImm(Val); } diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp index e0f2a07db7c0..4a7903d26daa 100644 --- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp +++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp @@ -11,872 +11,83 @@ // //===----------------------------------------------------------------------===// #include "AArch64BaseInfo.h" +#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/Regex.h" using namespace llvm; -StringRef AArch64NamedImmMapper::toString(uint32_t Value, - const FeatureBitset& FeatureBits, bool &Valid) const { - for (unsigned i = 0; i < NumMappings; ++i) { - if (Mappings[i].isValueEqual(Value, FeatureBits)) { - Valid = true; - return Mappings[i].Name; - } +namespace llvm { + namespace AArch64AT { +#define GET_AT_IMPL +#include "AArch64GenSystemOperands.inc" } - - Valid = false; - return StringRef(); } -uint32_t AArch64NamedImmMapper::fromString(StringRef Name, - const FeatureBitset& FeatureBits, bool &Valid) const { - std::string LowerCaseName = Name.lower(); - for (unsigned i = 0; i < NumMappings; ++i) { - if (Mappings[i].isNameEqual(LowerCaseName, FeatureBits)) { - Valid = true; - return Mappings[i].Value; - } + +namespace llvm { + namespace AArch64DB { +#define GET_DB_IMPL +#include "AArch64GenSystemOperands.inc" } - - Valid = false; - return -1; } -bool AArch64NamedImmMapper::validImm(uint32_t Value) const { - return Value < TooBigImm; -} - -const AArch64NamedImmMapper::Mapping AArch64AT::ATMapper::ATMappings[] = { - {"s1e1r", S1E1R, {}}, - {"s1e2r", S1E2R, {}}, - {"s1e3r", S1E3R, {}}, - {"s1e1w", S1E1W, {}}, - {"s1e2w", S1E2W, {}}, - {"s1e3w", S1E3W, {}}, - {"s1e0r", S1E0R, {}}, - {"s1e0w", S1E0W, {}}, - {"s12e1r", S12E1R, {}}, - {"s12e1w", S12E1W, {}}, - {"s12e0r", S12E0R, {}}, - {"s12e0w", S12E0W, {}}, -}; - -AArch64AT::ATMapper::ATMapper() - : AArch64NamedImmMapper(ATMappings, 0) {} - -const AArch64NamedImmMapper::Mapping AArch64DB::DBarrierMapper::DBarrierMappings[] = { - {"oshld", OSHLD, {}}, - {"oshst", OSHST, {}}, - {"osh", OSH, {}}, - {"nshld", NSHLD, {}}, - {"nshst", NSHST, {}}, - {"nsh", NSH, {}}, - {"ishld", ISHLD, {}}, - {"ishst", ISHST, {}}, - {"ish", ISH, {}}, - {"ld", LD, {}}, - {"st", ST, {}}, - {"sy", SY, {}} -}; - -AArch64DB::DBarrierMapper::DBarrierMapper() - : AArch64NamedImmMapper(DBarrierMappings, 16u) {} - -const AArch64NamedImmMapper::Mapping AArch64DC::DCMapper::DCMappings[] = { - {"zva", ZVA, {}}, - {"ivac", IVAC, {}}, - {"isw", ISW, {}}, - {"cvac", CVAC, {}}, - {"csw", CSW, {}}, - {"cvau", CVAU, {}}, - {"civac", CIVAC, {}}, - {"cisw", CISW, {}} -}; - -AArch64DC::DCMapper::DCMapper() - : AArch64NamedImmMapper(DCMappings, 0) {} - -const AArch64NamedImmMapper::Mapping AArch64IC::ICMapper::ICMappings[] = { - {"ialluis", IALLUIS, {}}, - {"iallu", IALLU, {}}, - {"ivau", IVAU, {}} -}; - -AArch64IC::ICMapper::ICMapper() - : AArch64NamedImmMapper(ICMappings, 0) {} - -const AArch64NamedImmMapper::Mapping AArch64ISB::ISBMapper::ISBMappings[] = { - {"sy", SY, {}}, -}; - -AArch64ISB::ISBMapper::ISBMapper() - : AArch64NamedImmMapper(ISBMappings, 16) {} - -const AArch64NamedImmMapper::Mapping AArch64PRFM::PRFMMapper::PRFMMappings[] = { - {"pldl1keep", PLDL1KEEP, {}}, - {"pldl1strm", PLDL1STRM, {}}, - {"pldl2keep", PLDL2KEEP, {}}, - {"pldl2strm", PLDL2STRM, {}}, - {"pldl3keep", PLDL3KEEP, {}}, - {"pldl3strm", PLDL3STRM, {}}, - {"plil1keep", PLIL1KEEP, {}}, - {"plil1strm", PLIL1STRM, {}}, - {"plil2keep", PLIL2KEEP, {}}, - {"plil2strm", PLIL2STRM, {}}, - {"plil3keep", PLIL3KEEP, {}}, - {"plil3strm", PLIL3STRM, {}}, - {"pstl1keep", PSTL1KEEP, {}}, - {"pstl1strm", PSTL1STRM, {}}, - {"pstl2keep", PSTL2KEEP, {}}, - {"pstl2strm", PSTL2STRM, {}}, - {"pstl3keep", PSTL3KEEP, {}}, - {"pstl3strm", PSTL3STRM, {}} -}; - -AArch64PRFM::PRFMMapper::PRFMMapper() - : AArch64NamedImmMapper(PRFMMappings, 32) {} - -const AArch64NamedImmMapper::Mapping AArch64PState::PStateMapper::PStateMappings[] = { - {"spsel", SPSel, {}}, - {"daifset", DAIFSet, {}}, - {"daifclr", DAIFClr, {}}, - - // v8.1a "Privileged Access Never" extension-specific PStates - {"pan", PAN, {AArch64::HasV8_1aOps}}, - - // v8.2a - {"uao", UAO, {AArch64::HasV8_2aOps}}, -}; - -AArch64PState::PStateMapper::PStateMapper() - : AArch64NamedImmMapper(PStateMappings, 0) {} - -const AArch64NamedImmMapper::Mapping AArch64PSBHint::PSBHintMapper::PSBHintMappings[] = { - // v8.2a "Statistical Profiling" extension-specific PSB operand - {"csync", CSync, {AArch64::FeatureSPE}}, -}; - -AArch64PSBHint::PSBHintMapper::PSBHintMapper() - : AArch64NamedImmMapper(PSBHintMappings, 0) {} - -const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = { - {"mdccsr_el0", MDCCSR_EL0, {}}, - {"dbgdtrrx_el0", DBGDTRRX_EL0, {}}, - {"mdrar_el1", MDRAR_EL1, {}}, - {"oslsr_el1", OSLSR_EL1, {}}, - {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1, {}}, - {"pmceid0_el0", PMCEID0_EL0, {}}, - {"pmceid1_el0", PMCEID1_EL0, {}}, - {"midr_el1", MIDR_EL1, {}}, - {"ccsidr_el1", CCSIDR_EL1, {}}, - {"clidr_el1", CLIDR_EL1, {}}, - {"ctr_el0", CTR_EL0, {}}, - {"mpidr_el1", MPIDR_EL1, {}}, - {"revidr_el1", REVIDR_EL1, {}}, - {"aidr_el1", AIDR_EL1, {}}, - {"dczid_el0", DCZID_EL0, {}}, - {"id_pfr0_el1", ID_PFR0_EL1, {}}, - {"id_pfr1_el1", ID_PFR1_EL1, {}}, - {"id_dfr0_el1", ID_DFR0_EL1, {}}, - {"id_afr0_el1", ID_AFR0_EL1, {}}, - {"id_mmfr0_el1", ID_MMFR0_EL1, {}}, - {"id_mmfr1_el1", ID_MMFR1_EL1, {}}, - {"id_mmfr2_el1", ID_MMFR2_EL1, {}}, - {"id_mmfr3_el1", ID_MMFR3_EL1, {}}, - {"id_mmfr4_el1", ID_MMFR4_EL1, {}}, - {"id_isar0_el1", ID_ISAR0_EL1, {}}, - {"id_isar1_el1", ID_ISAR1_EL1, {}}, - {"id_isar2_el1", ID_ISAR2_EL1, {}}, - {"id_isar3_el1", ID_ISAR3_EL1, {}}, - {"id_isar4_el1", ID_ISAR4_EL1, {}}, - {"id_isar5_el1", ID_ISAR5_EL1, {}}, - {"id_aa64pfr0_el1", ID_A64PFR0_EL1, {}}, - {"id_aa64pfr1_el1", ID_A64PFR1_EL1, {}}, - {"id_aa64dfr0_el1", ID_A64DFR0_EL1, {}}, - {"id_aa64dfr1_el1", ID_A64DFR1_EL1, {}}, - {"id_aa64afr0_el1", ID_A64AFR0_EL1, {}}, - {"id_aa64afr1_el1", ID_A64AFR1_EL1, {}}, - {"id_aa64isar0_el1", ID_A64ISAR0_EL1, {}}, - {"id_aa64isar1_el1", ID_A64ISAR1_EL1, {}}, - {"id_aa64mmfr0_el1", ID_A64MMFR0_EL1, {}}, - {"id_aa64mmfr1_el1", ID_A64MMFR1_EL1, {}}, - {"id_aa64mmfr2_el1", ID_A64MMFR2_EL1, {AArch64::HasV8_2aOps}}, - {"mvfr0_el1", MVFR0_EL1, {}}, - {"mvfr1_el1", MVFR1_EL1, {}}, - {"mvfr2_el1", MVFR2_EL1, {}}, - {"rvbar_el1", RVBAR_EL1, {}}, - {"rvbar_el2", RVBAR_EL2, {}}, - {"rvbar_el3", RVBAR_EL3, {}}, - {"isr_el1", ISR_EL1, {}}, - {"cntpct_el0", CNTPCT_EL0, {}}, - {"cntvct_el0", CNTVCT_EL0, {}}, - - // Trace registers - {"trcstatr", TRCSTATR, {}}, - {"trcidr8", TRCIDR8, {}}, - {"trcidr9", TRCIDR9, {}}, - {"trcidr10", TRCIDR10, {}}, - {"trcidr11", TRCIDR11, {}}, - {"trcidr12", TRCIDR12, {}}, - {"trcidr13", TRCIDR13, {}}, - {"trcidr0", TRCIDR0, {}}, - {"trcidr1", TRCIDR1, {}}, - {"trcidr2", TRCIDR2, {}}, - {"trcidr3", TRCIDR3, {}}, - {"trcidr4", TRCIDR4, {}}, - {"trcidr5", TRCIDR5, {}}, - {"trcidr6", TRCIDR6, {}}, - {"trcidr7", TRCIDR7, {}}, - {"trcoslsr", TRCOSLSR, {}}, - {"trcpdsr", TRCPDSR, {}}, - {"trcdevaff0", TRCDEVAFF0, {}}, - {"trcdevaff1", TRCDEVAFF1, {}}, - {"trclsr", TRCLSR, {}}, - {"trcauthstatus", TRCAUTHSTATUS, {}}, - {"trcdevarch", TRCDEVARCH, {}}, - {"trcdevid", TRCDEVID, {}}, - {"trcdevtype", TRCDEVTYPE, {}}, - {"trcpidr4", TRCPIDR4, {}}, - {"trcpidr5", TRCPIDR5, {}}, - {"trcpidr6", TRCPIDR6, {}}, - {"trcpidr7", TRCPIDR7, {}}, - {"trcpidr0", TRCPIDR0, {}}, - {"trcpidr1", TRCPIDR1, {}}, - {"trcpidr2", TRCPIDR2, {}}, - {"trcpidr3", TRCPIDR3, {}}, - {"trccidr0", TRCCIDR0, {}}, - {"trccidr1", TRCCIDR1, {}}, - {"trccidr2", TRCCIDR2, {}}, - {"trccidr3", TRCCIDR3, {}}, - - // GICv3 registers - {"icc_iar1_el1", ICC_IAR1_EL1, {}}, - {"icc_iar0_el1", ICC_IAR0_EL1, {}}, - {"icc_hppir1_el1", ICC_HPPIR1_EL1, {}}, - {"icc_hppir0_el1", ICC_HPPIR0_EL1, {}}, - {"icc_rpr_el1", ICC_RPR_EL1, {}}, - {"ich_vtr_el2", ICH_VTR_EL2, {}}, - {"ich_eisr_el2", ICH_EISR_EL2, {}}, - {"ich_elsr_el2", ICH_ELSR_EL2, {}}, - - // v8.1a "Limited Ordering Regions" extension-specific system registers - {"lorid_el1", LORID_EL1, {AArch64::HasV8_1aOps}}, - - // v8.2a "Reliability, Availability and Serviceability" extensions registers - {"erridr_el1", ERRIDR_EL1, {AArch64::FeatureRAS}}, - {"erxfr_el1", ERXFR_EL1, {AArch64::FeatureRAS}} -}; - -AArch64SysReg::MRSMapper::MRSMapper() { - InstMappings = &MRSMappings[0]; - NumInstMappings = llvm::array_lengthof(MRSMappings); -} - -const AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRMappings[] = { - {"dbgdtrtx_el0", DBGDTRTX_EL0, {}}, - {"oslar_el1", OSLAR_EL1, {}}, - {"pmswinc_el0", PMSWINC_EL0, {}}, - - // Trace registers - {"trcoslar", TRCOSLAR, {}}, - {"trclar", TRCLAR, {}}, - - // GICv3 registers - {"icc_eoir1_el1", ICC_EOIR1_EL1, {}}, - {"icc_eoir0_el1", ICC_EOIR0_EL1, {}}, - {"icc_dir_el1", ICC_DIR_EL1, {}}, - {"icc_sgi1r_el1", ICC_SGI1R_EL1, {}}, - {"icc_asgi1r_el1", ICC_ASGI1R_EL1, {}}, - {"icc_sgi0r_el1", ICC_SGI0R_EL1, {}}, -}; - -AArch64SysReg::MSRMapper::MSRMapper() { - InstMappings = &MSRMappings[0]; - NumInstMappings = llvm::array_lengthof(MSRMappings); -} - - -const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = { - {"osdtrrx_el1", OSDTRRX_EL1, {}}, - {"osdtrtx_el1", OSDTRTX_EL1, {}}, - {"teecr32_el1", TEECR32_EL1, {}}, - {"mdccint_el1", MDCCINT_EL1, {}}, - {"mdscr_el1", MDSCR_EL1, {}}, - {"dbgdtr_el0", DBGDTR_EL0, {}}, - {"oseccr_el1", OSECCR_EL1, {}}, - {"dbgvcr32_el2", DBGVCR32_EL2, {}}, - {"dbgbvr0_el1", DBGBVR0_EL1, {}}, - {"dbgbvr1_el1", DBGBVR1_EL1, {}}, - {"dbgbvr2_el1", DBGBVR2_EL1, {}}, - {"dbgbvr3_el1", DBGBVR3_EL1, {}}, - {"dbgbvr4_el1", DBGBVR4_EL1, {}}, - {"dbgbvr5_el1", DBGBVR5_EL1, {}}, - {"dbgbvr6_el1", DBGBVR6_EL1, {}}, - {"dbgbvr7_el1", DBGBVR7_EL1, {}}, - {"dbgbvr8_el1", DBGBVR8_EL1, {}}, - {"dbgbvr9_el1", DBGBVR9_EL1, {}}, - {"dbgbvr10_el1", DBGBVR10_EL1, {}}, - {"dbgbvr11_el1", DBGBVR11_EL1, {}}, - {"dbgbvr12_el1", DBGBVR12_EL1, {}}, - {"dbgbvr13_el1", DBGBVR13_EL1, {}}, - {"dbgbvr14_el1", DBGBVR14_EL1, {}}, - {"dbgbvr15_el1", DBGBVR15_EL1, {}}, - {"dbgbcr0_el1", DBGBCR0_EL1, {}}, - {"dbgbcr1_el1", DBGBCR1_EL1, {}}, - {"dbgbcr2_el1", DBGBCR2_EL1, {}}, - {"dbgbcr3_el1", DBGBCR3_EL1, {}}, - {"dbgbcr4_el1", DBGBCR4_EL1, {}}, - {"dbgbcr5_el1", DBGBCR5_EL1, {}}, - {"dbgbcr6_el1", DBGBCR6_EL1, {}}, - {"dbgbcr7_el1", DBGBCR7_EL1, {}}, - {"dbgbcr8_el1", DBGBCR8_EL1, {}}, - {"dbgbcr9_el1", DBGBCR9_EL1, {}}, - {"dbgbcr10_el1", DBGBCR10_EL1, {}}, - {"dbgbcr11_el1", DBGBCR11_EL1, {}}, - {"dbgbcr12_el1", DBGBCR12_EL1, {}}, - {"dbgbcr13_el1", DBGBCR13_EL1, {}}, - {"dbgbcr14_el1", DBGBCR14_EL1, {}}, - {"dbgbcr15_el1", DBGBCR15_EL1, {}}, - {"dbgwvr0_el1", DBGWVR0_EL1, {}}, - {"dbgwvr1_el1", DBGWVR1_EL1, {}}, - {"dbgwvr2_el1", DBGWVR2_EL1, {}}, - {"dbgwvr3_el1", DBGWVR3_EL1, {}}, - {"dbgwvr4_el1", DBGWVR4_EL1, {}}, - {"dbgwvr5_el1", DBGWVR5_EL1, {}}, - {"dbgwvr6_el1", DBGWVR6_EL1, {}}, - {"dbgwvr7_el1", DBGWVR7_EL1, {}}, - {"dbgwvr8_el1", DBGWVR8_EL1, {}}, - {"dbgwvr9_el1", DBGWVR9_EL1, {}}, - {"dbgwvr10_el1", DBGWVR10_EL1, {}}, - {"dbgwvr11_el1", DBGWVR11_EL1, {}}, - {"dbgwvr12_el1", DBGWVR12_EL1, {}}, - {"dbgwvr13_el1", DBGWVR13_EL1, {}}, - {"dbgwvr14_el1", DBGWVR14_EL1, {}}, - {"dbgwvr15_el1", DBGWVR15_EL1, {}}, - {"dbgwcr0_el1", DBGWCR0_EL1, {}}, - {"dbgwcr1_el1", DBGWCR1_EL1, {}}, - {"dbgwcr2_el1", DBGWCR2_EL1, {}}, - {"dbgwcr3_el1", DBGWCR3_EL1, {}}, - {"dbgwcr4_el1", DBGWCR4_EL1, {}}, - {"dbgwcr5_el1", DBGWCR5_EL1, {}}, - {"dbgwcr6_el1", DBGWCR6_EL1, {}}, - {"dbgwcr7_el1", DBGWCR7_EL1, {}}, - {"dbgwcr8_el1", DBGWCR8_EL1, {}}, - {"dbgwcr9_el1", DBGWCR9_EL1, {}}, - {"dbgwcr10_el1", DBGWCR10_EL1, {}}, - {"dbgwcr11_el1", DBGWCR11_EL1, {}}, - {"dbgwcr12_el1", DBGWCR12_EL1, {}}, - {"dbgwcr13_el1", DBGWCR13_EL1, {}}, - {"dbgwcr14_el1", DBGWCR14_EL1, {}}, - {"dbgwcr15_el1", DBGWCR15_EL1, {}}, - {"teehbr32_el1", TEEHBR32_EL1, {}}, - {"osdlr_el1", OSDLR_EL1, {}}, - {"dbgprcr_el1", DBGPRCR_EL1, {}}, - {"dbgclaimset_el1", DBGCLAIMSET_EL1, {}}, - {"dbgclaimclr_el1", DBGCLAIMCLR_EL1, {}}, - {"csselr_el1", CSSELR_EL1, {}}, - {"vpidr_el2", VPIDR_EL2, {}}, - {"vmpidr_el2", VMPIDR_EL2, {}}, - {"sctlr_el1", SCTLR_EL1, {}}, - {"sctlr_el2", SCTLR_EL2, {}}, - {"sctlr_el3", SCTLR_EL3, {}}, - {"actlr_el1", ACTLR_EL1, {}}, - {"actlr_el2", ACTLR_EL2, {}}, - {"actlr_el3", ACTLR_EL3, {}}, - {"cpacr_el1", CPACR_EL1, {}}, - {"hcr_el2", HCR_EL2, {}}, - {"scr_el3", SCR_EL3, {}}, - {"mdcr_el2", MDCR_EL2, {}}, - {"sder32_el3", SDER32_EL3, {}}, - {"cptr_el2", CPTR_EL2, {}}, - {"cptr_el3", CPTR_EL3, {}}, - {"hstr_el2", HSTR_EL2, {}}, - {"hacr_el2", HACR_EL2, {}}, - {"mdcr_el3", MDCR_EL3, {}}, - {"ttbr0_el1", TTBR0_EL1, {}}, - {"ttbr0_el2", TTBR0_EL2, {}}, - {"ttbr0_el3", TTBR0_EL3, {}}, - {"ttbr1_el1", TTBR1_EL1, {}}, - {"tcr_el1", TCR_EL1, {}}, - {"tcr_el2", TCR_EL2, {}}, - {"tcr_el3", TCR_EL3, {}}, - {"vttbr_el2", VTTBR_EL2, {}}, - {"vtcr_el2", VTCR_EL2, {}}, - {"dacr32_el2", DACR32_EL2, {}}, - {"spsr_el1", SPSR_EL1, {}}, - {"spsr_el2", SPSR_EL2, {}}, - {"spsr_el3", SPSR_EL3, {}}, - {"elr_el1", ELR_EL1, {}}, - {"elr_el2", ELR_EL2, {}}, - {"elr_el3", ELR_EL3, {}}, - {"sp_el0", SP_EL0, {}}, - {"sp_el1", SP_EL1, {}}, - {"sp_el2", SP_EL2, {}}, - {"spsel", SPSel, {}}, - {"nzcv", NZCV, {}}, - {"daif", DAIF, {}}, - {"currentel", CurrentEL, {}}, - {"spsr_irq", SPSR_irq, {}}, - {"spsr_abt", SPSR_abt, {}}, - {"spsr_und", SPSR_und, {}}, - {"spsr_fiq", SPSR_fiq, {}}, - {"fpcr", FPCR, {}}, - {"fpsr", FPSR, {}}, - {"dspsr_el0", DSPSR_EL0, {}}, - {"dlr_el0", DLR_EL0, {}}, - {"ifsr32_el2", IFSR32_EL2, {}}, - {"afsr0_el1", AFSR0_EL1, {}}, - {"afsr0_el2", AFSR0_EL2, {}}, - {"afsr0_el3", AFSR0_EL3, {}}, - {"afsr1_el1", AFSR1_EL1, {}}, - {"afsr1_el2", AFSR1_EL2, {}}, - {"afsr1_el3", AFSR1_EL3, {}}, - {"esr_el1", ESR_EL1, {}}, - {"esr_el2", ESR_EL2, {}}, - {"esr_el3", ESR_EL3, {}}, - {"fpexc32_el2", FPEXC32_EL2, {}}, - {"far_el1", FAR_EL1, {}}, - {"far_el2", FAR_EL2, {}}, - {"far_el3", FAR_EL3, {}}, - {"hpfar_el2", HPFAR_EL2, {}}, - {"par_el1", PAR_EL1, {}}, - {"pmcr_el0", PMCR_EL0, {}}, - {"pmcntenset_el0", PMCNTENSET_EL0, {}}, - {"pmcntenclr_el0", PMCNTENCLR_EL0, {}}, - {"pmovsclr_el0", PMOVSCLR_EL0, {}}, - {"pmselr_el0", PMSELR_EL0, {}}, - {"pmccntr_el0", PMCCNTR_EL0, {}}, - {"pmxevtyper_el0", PMXEVTYPER_EL0, {}}, - {"pmxevcntr_el0", PMXEVCNTR_EL0, {}}, - {"pmuserenr_el0", PMUSERENR_EL0, {}}, - {"pmintenset_el1", PMINTENSET_EL1, {}}, - {"pmintenclr_el1", PMINTENCLR_EL1, {}}, - {"pmovsset_el0", PMOVSSET_EL0, {}}, - {"mair_el1", MAIR_EL1, {}}, - {"mair_el2", MAIR_EL2, {}}, - {"mair_el3", MAIR_EL3, {}}, - {"amair_el1", AMAIR_EL1, {}}, - {"amair_el2", AMAIR_EL2, {}}, - {"amair_el3", AMAIR_EL3, {}}, - {"vbar_el1", VBAR_EL1, {}}, - {"vbar_el2", VBAR_EL2, {}}, - {"vbar_el3", VBAR_EL3, {}}, - {"rmr_el1", RMR_EL1, {}}, - {"rmr_el2", RMR_EL2, {}}, - {"rmr_el3", RMR_EL3, {}}, - {"contextidr_el1", CONTEXTIDR_EL1, {}}, - {"tpidr_el0", TPIDR_EL0, {}}, - {"tpidr_el2", TPIDR_EL2, {}}, - {"tpidr_el3", TPIDR_EL3, {}}, - {"tpidrro_el0", TPIDRRO_EL0, {}}, - {"tpidr_el1", TPIDR_EL1, {}}, - {"cntfrq_el0", CNTFRQ_EL0, {}}, - {"cntvoff_el2", CNTVOFF_EL2, {}}, - {"cntkctl_el1", CNTKCTL_EL1, {}}, - {"cnthctl_el2", CNTHCTL_EL2, {}}, - {"cntp_tval_el0", CNTP_TVAL_EL0, {}}, - {"cnthp_tval_el2", CNTHP_TVAL_EL2, {}}, - {"cntps_tval_el1", CNTPS_TVAL_EL1, {}}, - {"cntp_ctl_el0", CNTP_CTL_EL0, {}}, - {"cnthp_ctl_el2", CNTHP_CTL_EL2, {}}, - {"cntps_ctl_el1", CNTPS_CTL_EL1, {}}, - {"cntp_cval_el0", CNTP_CVAL_EL0, {}}, - {"cnthp_cval_el2", CNTHP_CVAL_EL2, {}}, - {"cntps_cval_el1", CNTPS_CVAL_EL1, {}}, - {"cntv_tval_el0", CNTV_TVAL_EL0, {}}, - {"cntv_ctl_el0", CNTV_CTL_EL0, {}}, - {"cntv_cval_el0", CNTV_CVAL_EL0, {}}, - {"pmevcntr0_el0", PMEVCNTR0_EL0, {}}, - {"pmevcntr1_el0", PMEVCNTR1_EL0, {}}, - {"pmevcntr2_el0", PMEVCNTR2_EL0, {}}, - {"pmevcntr3_el0", PMEVCNTR3_EL0, {}}, - {"pmevcntr4_el0", PMEVCNTR4_EL0, {}}, - {"pmevcntr5_el0", PMEVCNTR5_EL0, {}}, - {"pmevcntr6_el0", PMEVCNTR6_EL0, {}}, - {"pmevcntr7_el0", PMEVCNTR7_EL0, {}}, - {"pmevcntr8_el0", PMEVCNTR8_EL0, {}}, - {"pmevcntr9_el0", PMEVCNTR9_EL0, {}}, - {"pmevcntr10_el0", PMEVCNTR10_EL0, {}}, - {"pmevcntr11_el0", PMEVCNTR11_EL0, {}}, - {"pmevcntr12_el0", PMEVCNTR12_EL0, {}}, - {"pmevcntr13_el0", PMEVCNTR13_EL0, {}}, - {"pmevcntr14_el0", PMEVCNTR14_EL0, {}}, - {"pmevcntr15_el0", PMEVCNTR15_EL0, {}}, - {"pmevcntr16_el0", PMEVCNTR16_EL0, {}}, - {"pmevcntr17_el0", PMEVCNTR17_EL0, {}}, - {"pmevcntr18_el0", PMEVCNTR18_EL0, {}}, - {"pmevcntr19_el0", PMEVCNTR19_EL0, {}}, - {"pmevcntr20_el0", PMEVCNTR20_EL0, {}}, - {"pmevcntr21_el0", PMEVCNTR21_EL0, {}}, - {"pmevcntr22_el0", PMEVCNTR22_EL0, {}}, - {"pmevcntr23_el0", PMEVCNTR23_EL0, {}}, - {"pmevcntr24_el0", PMEVCNTR24_EL0, {}}, - {"pmevcntr25_el0", PMEVCNTR25_EL0, {}}, - {"pmevcntr26_el0", PMEVCNTR26_EL0, {}}, - {"pmevcntr27_el0", PMEVCNTR27_EL0, {}}, - {"pmevcntr28_el0", PMEVCNTR28_EL0, {}}, - {"pmevcntr29_el0", PMEVCNTR29_EL0, {}}, - {"pmevcntr30_el0", PMEVCNTR30_EL0, {}}, - {"pmccfiltr_el0", PMCCFILTR_EL0, {}}, - {"pmevtyper0_el0", PMEVTYPER0_EL0, {}}, - {"pmevtyper1_el0", PMEVTYPER1_EL0, {}}, - {"pmevtyper2_el0", PMEVTYPER2_EL0, {}}, - {"pmevtyper3_el0", PMEVTYPER3_EL0, {}}, - {"pmevtyper4_el0", PMEVTYPER4_EL0, {}}, - {"pmevtyper5_el0", PMEVTYPER5_EL0, {}}, - {"pmevtyper6_el0", PMEVTYPER6_EL0, {}}, - {"pmevtyper7_el0", PMEVTYPER7_EL0, {}}, - {"pmevtyper8_el0", PMEVTYPER8_EL0, {}}, - {"pmevtyper9_el0", PMEVTYPER9_EL0, {}}, - {"pmevtyper10_el0", PMEVTYPER10_EL0, {}}, - {"pmevtyper11_el0", PMEVTYPER11_EL0, {}}, - {"pmevtyper12_el0", PMEVTYPER12_EL0, {}}, - {"pmevtyper13_el0", PMEVTYPER13_EL0, {}}, - {"pmevtyper14_el0", PMEVTYPER14_EL0, {}}, - {"pmevtyper15_el0", PMEVTYPER15_EL0, {}}, - {"pmevtyper16_el0", PMEVTYPER16_EL0, {}}, - {"pmevtyper17_el0", PMEVTYPER17_EL0, {}}, - {"pmevtyper18_el0", PMEVTYPER18_EL0, {}}, - {"pmevtyper19_el0", PMEVTYPER19_EL0, {}}, - {"pmevtyper20_el0", PMEVTYPER20_EL0, {}}, - {"pmevtyper21_el0", PMEVTYPER21_EL0, {}}, - {"pmevtyper22_el0", PMEVTYPER22_EL0, {}}, - {"pmevtyper23_el0", PMEVTYPER23_EL0, {}}, - {"pmevtyper24_el0", PMEVTYPER24_EL0, {}}, - {"pmevtyper25_el0", PMEVTYPER25_EL0, {}}, - {"pmevtyper26_el0", PMEVTYPER26_EL0, {}}, - {"pmevtyper27_el0", PMEVTYPER27_EL0, {}}, - {"pmevtyper28_el0", PMEVTYPER28_EL0, {}}, - {"pmevtyper29_el0", PMEVTYPER29_EL0, {}}, - {"pmevtyper30_el0", PMEVTYPER30_EL0, {}}, - - // Trace registers - {"trcprgctlr", TRCPRGCTLR, {}}, - {"trcprocselr", TRCPROCSELR, {}}, - {"trcconfigr", TRCCONFIGR, {}}, - {"trcauxctlr", TRCAUXCTLR, {}}, - {"trceventctl0r", TRCEVENTCTL0R, {}}, - {"trceventctl1r", TRCEVENTCTL1R, {}}, - {"trcstallctlr", TRCSTALLCTLR, {}}, - {"trctsctlr", TRCTSCTLR, {}}, - {"trcsyncpr", TRCSYNCPR, {}}, - {"trcccctlr", TRCCCCTLR, {}}, - {"trcbbctlr", TRCBBCTLR, {}}, - {"trctraceidr", TRCTRACEIDR, {}}, - {"trcqctlr", TRCQCTLR, {}}, - {"trcvictlr", TRCVICTLR, {}}, - {"trcviiectlr", TRCVIIECTLR, {}}, - {"trcvissctlr", TRCVISSCTLR, {}}, - {"trcvipcssctlr", TRCVIPCSSCTLR, {}}, - {"trcvdctlr", TRCVDCTLR, {}}, - {"trcvdsacctlr", TRCVDSACCTLR, {}}, - {"trcvdarcctlr", TRCVDARCCTLR, {}}, - {"trcseqevr0", TRCSEQEVR0, {}}, - {"trcseqevr1", TRCSEQEVR1, {}}, - {"trcseqevr2", TRCSEQEVR2, {}}, - {"trcseqrstevr", TRCSEQRSTEVR, {}}, - {"trcseqstr", TRCSEQSTR, {}}, - {"trcextinselr", TRCEXTINSELR, {}}, - {"trccntrldvr0", TRCCNTRLDVR0, {}}, - {"trccntrldvr1", TRCCNTRLDVR1, {}}, - {"trccntrldvr2", TRCCNTRLDVR2, {}}, - {"trccntrldvr3", TRCCNTRLDVR3, {}}, - {"trccntctlr0", TRCCNTCTLR0, {}}, - {"trccntctlr1", TRCCNTCTLR1, {}}, - {"trccntctlr2", TRCCNTCTLR2, {}}, - {"trccntctlr3", TRCCNTCTLR3, {}}, - {"trccntvr0", TRCCNTVR0, {}}, - {"trccntvr1", TRCCNTVR1, {}}, - {"trccntvr2", TRCCNTVR2, {}}, - {"trccntvr3", TRCCNTVR3, {}}, - {"trcimspec0", TRCIMSPEC0, {}}, - {"trcimspec1", TRCIMSPEC1, {}}, - {"trcimspec2", TRCIMSPEC2, {}}, - {"trcimspec3", TRCIMSPEC3, {}}, - {"trcimspec4", TRCIMSPEC4, {}}, - {"trcimspec5", TRCIMSPEC5, {}}, - {"trcimspec6", TRCIMSPEC6, {}}, - {"trcimspec7", TRCIMSPEC7, {}}, - {"trcrsctlr2", TRCRSCTLR2, {}}, - {"trcrsctlr3", TRCRSCTLR3, {}}, - {"trcrsctlr4", TRCRSCTLR4, {}}, - {"trcrsctlr5", TRCRSCTLR5, {}}, - {"trcrsctlr6", TRCRSCTLR6, {}}, - {"trcrsctlr7", TRCRSCTLR7, {}}, - {"trcrsctlr8", TRCRSCTLR8, {}}, - {"trcrsctlr9", TRCRSCTLR9, {}}, - {"trcrsctlr10", TRCRSCTLR10, {}}, - {"trcrsctlr11", TRCRSCTLR11, {}}, - {"trcrsctlr12", TRCRSCTLR12, {}}, - {"trcrsctlr13", TRCRSCTLR13, {}}, - {"trcrsctlr14", TRCRSCTLR14, {}}, - {"trcrsctlr15", TRCRSCTLR15, {}}, - {"trcrsctlr16", TRCRSCTLR16, {}}, - {"trcrsctlr17", TRCRSCTLR17, {}}, - {"trcrsctlr18", TRCRSCTLR18, {}}, - {"trcrsctlr19", TRCRSCTLR19, {}}, - {"trcrsctlr20", TRCRSCTLR20, {}}, - {"trcrsctlr21", TRCRSCTLR21, {}}, - {"trcrsctlr22", TRCRSCTLR22, {}}, - {"trcrsctlr23", TRCRSCTLR23, {}}, - {"trcrsctlr24", TRCRSCTLR24, {}}, - {"trcrsctlr25", TRCRSCTLR25, {}}, - {"trcrsctlr26", TRCRSCTLR26, {}}, - {"trcrsctlr27", TRCRSCTLR27, {}}, - {"trcrsctlr28", TRCRSCTLR28, {}}, - {"trcrsctlr29", TRCRSCTLR29, {}}, - {"trcrsctlr30", TRCRSCTLR30, {}}, - {"trcrsctlr31", TRCRSCTLR31, {}}, - {"trcssccr0", TRCSSCCR0, {}}, - {"trcssccr1", TRCSSCCR1, {}}, - {"trcssccr2", TRCSSCCR2, {}}, - {"trcssccr3", TRCSSCCR3, {}}, - {"trcssccr4", TRCSSCCR4, {}}, - {"trcssccr5", TRCSSCCR5, {}}, - {"trcssccr6", TRCSSCCR6, {}}, - {"trcssccr7", TRCSSCCR7, {}}, - {"trcsscsr0", TRCSSCSR0, {}}, - {"trcsscsr1", TRCSSCSR1, {}}, - {"trcsscsr2", TRCSSCSR2, {}}, - {"trcsscsr3", TRCSSCSR3, {}}, - {"trcsscsr4", TRCSSCSR4, {}}, - {"trcsscsr5", TRCSSCSR5, {}}, - {"trcsscsr6", TRCSSCSR6, {}}, - {"trcsscsr7", TRCSSCSR7, {}}, - {"trcsspcicr0", TRCSSPCICR0, {}}, - {"trcsspcicr1", TRCSSPCICR1, {}}, - {"trcsspcicr2", TRCSSPCICR2, {}}, - {"trcsspcicr3", TRCSSPCICR3, {}}, - {"trcsspcicr4", TRCSSPCICR4, {}}, - {"trcsspcicr5", TRCSSPCICR5, {}}, - {"trcsspcicr6", TRCSSPCICR6, {}}, - {"trcsspcicr7", TRCSSPCICR7, {}}, - {"trcpdcr", TRCPDCR, {}}, - {"trcacvr0", TRCACVR0, {}}, - {"trcacvr1", TRCACVR1, {}}, - {"trcacvr2", TRCACVR2, {}}, - {"trcacvr3", TRCACVR3, {}}, - {"trcacvr4", TRCACVR4, {}}, - {"trcacvr5", TRCACVR5, {}}, - {"trcacvr6", TRCACVR6, {}}, - {"trcacvr7", TRCACVR7, {}}, - {"trcacvr8", TRCACVR8, {}}, - {"trcacvr9", TRCACVR9, {}}, - {"trcacvr10", TRCACVR10, {}}, - {"trcacvr11", TRCACVR11, {}}, - {"trcacvr12", TRCACVR12, {}}, - {"trcacvr13", TRCACVR13, {}}, - {"trcacvr14", TRCACVR14, {}}, - {"trcacvr15", TRCACVR15, {}}, - {"trcacatr0", TRCACATR0, {}}, - {"trcacatr1", TRCACATR1, {}}, - {"trcacatr2", TRCACATR2, {}}, - {"trcacatr3", TRCACATR3, {}}, - {"trcacatr4", TRCACATR4, {}}, - {"trcacatr5", TRCACATR5, {}}, - {"trcacatr6", TRCACATR6, {}}, - {"trcacatr7", TRCACATR7, {}}, - {"trcacatr8", TRCACATR8, {}}, - {"trcacatr9", TRCACATR9, {}}, - {"trcacatr10", TRCACATR10, {}}, - {"trcacatr11", TRCACATR11, {}}, - {"trcacatr12", TRCACATR12, {}}, - {"trcacatr13", TRCACATR13, {}}, - {"trcacatr14", TRCACATR14, {}}, - {"trcacatr15", TRCACATR15, {}}, - {"trcdvcvr0", TRCDVCVR0, {}}, - {"trcdvcvr1", TRCDVCVR1, {}}, - {"trcdvcvr2", TRCDVCVR2, {}}, - {"trcdvcvr3", TRCDVCVR3, {}}, - {"trcdvcvr4", TRCDVCVR4, {}}, - {"trcdvcvr5", TRCDVCVR5, {}}, - {"trcdvcvr6", TRCDVCVR6, {}}, - {"trcdvcvr7", TRCDVCVR7, {}}, - {"trcdvcmr0", TRCDVCMR0, {}}, - {"trcdvcmr1", TRCDVCMR1, {}}, - {"trcdvcmr2", TRCDVCMR2, {}}, - {"trcdvcmr3", TRCDVCMR3, {}}, - {"trcdvcmr4", TRCDVCMR4, {}}, - {"trcdvcmr5", TRCDVCMR5, {}}, - {"trcdvcmr6", TRCDVCMR6, {}}, - {"trcdvcmr7", TRCDVCMR7, {}}, - {"trccidcvr0", TRCCIDCVR0, {}}, - {"trccidcvr1", TRCCIDCVR1, {}}, - {"trccidcvr2", TRCCIDCVR2, {}}, - {"trccidcvr3", TRCCIDCVR3, {}}, - {"trccidcvr4", TRCCIDCVR4, {}}, - {"trccidcvr5", TRCCIDCVR5, {}}, - {"trccidcvr6", TRCCIDCVR6, {}}, - {"trccidcvr7", TRCCIDCVR7, {}}, - {"trcvmidcvr0", TRCVMIDCVR0, {}}, - {"trcvmidcvr1", TRCVMIDCVR1, {}}, - {"trcvmidcvr2", TRCVMIDCVR2, {}}, - {"trcvmidcvr3", TRCVMIDCVR3, {}}, - {"trcvmidcvr4", TRCVMIDCVR4, {}}, - {"trcvmidcvr5", TRCVMIDCVR5, {}}, - {"trcvmidcvr6", TRCVMIDCVR6, {}}, - {"trcvmidcvr7", TRCVMIDCVR7, {}}, - {"trccidcctlr0", TRCCIDCCTLR0, {}}, - {"trccidcctlr1", TRCCIDCCTLR1, {}}, - {"trcvmidcctlr0", TRCVMIDCCTLR0, {}}, - {"trcvmidcctlr1", TRCVMIDCCTLR1, {}}, - {"trcitctrl", TRCITCTRL, {}}, - {"trcclaimset", TRCCLAIMSET, {}}, - {"trcclaimclr", TRCCLAIMCLR, {}}, - - // GICv3 registers - {"icc_bpr1_el1", ICC_BPR1_EL1, {}}, - {"icc_bpr0_el1", ICC_BPR0_EL1, {}}, - {"icc_pmr_el1", ICC_PMR_EL1, {}}, - {"icc_ctlr_el1", ICC_CTLR_EL1, {}}, - {"icc_ctlr_el3", ICC_CTLR_EL3, {}}, - {"icc_sre_el1", ICC_SRE_EL1, {}}, - {"icc_sre_el2", ICC_SRE_EL2, {}}, - {"icc_sre_el3", ICC_SRE_EL3, {}}, - {"icc_igrpen0_el1", ICC_IGRPEN0_EL1, {}}, - {"icc_igrpen1_el1", ICC_IGRPEN1_EL1, {}}, - {"icc_igrpen1_el3", ICC_IGRPEN1_EL3, {}}, - {"icc_seien_el1", ICC_SEIEN_EL1, {}}, - {"icc_ap0r0_el1", ICC_AP0R0_EL1, {}}, - {"icc_ap0r1_el1", ICC_AP0R1_EL1, {}}, - {"icc_ap0r2_el1", ICC_AP0R2_EL1, {}}, - {"icc_ap0r3_el1", ICC_AP0R3_EL1, {}}, - {"icc_ap1r0_el1", ICC_AP1R0_EL1, {}}, - {"icc_ap1r1_el1", ICC_AP1R1_EL1, {}}, - {"icc_ap1r2_el1", ICC_AP1R2_EL1, {}}, - {"icc_ap1r3_el1", ICC_AP1R3_EL1, {}}, - {"ich_ap0r0_el2", ICH_AP0R0_EL2, {}}, - {"ich_ap0r1_el2", ICH_AP0R1_EL2, {}}, - {"ich_ap0r2_el2", ICH_AP0R2_EL2, {}}, - {"ich_ap0r3_el2", ICH_AP0R3_EL2, {}}, - {"ich_ap1r0_el2", ICH_AP1R0_EL2, {}}, - {"ich_ap1r1_el2", ICH_AP1R1_EL2, {}}, - {"ich_ap1r2_el2", ICH_AP1R2_EL2, {}}, - {"ich_ap1r3_el2", ICH_AP1R3_EL2, {}}, - {"ich_hcr_el2", ICH_HCR_EL2, {}}, - {"ich_misr_el2", ICH_MISR_EL2, {}}, - {"ich_vmcr_el2", ICH_VMCR_EL2, {}}, - {"ich_vseir_el2", ICH_VSEIR_EL2, {}}, - {"ich_lr0_el2", ICH_LR0_EL2, {}}, - {"ich_lr1_el2", ICH_LR1_EL2, {}}, - {"ich_lr2_el2", ICH_LR2_EL2, {}}, - {"ich_lr3_el2", ICH_LR3_EL2, {}}, - {"ich_lr4_el2", ICH_LR4_EL2, {}}, - {"ich_lr5_el2", ICH_LR5_EL2, {}}, - {"ich_lr6_el2", ICH_LR6_EL2, {}}, - {"ich_lr7_el2", ICH_LR7_EL2, {}}, - {"ich_lr8_el2", ICH_LR8_EL2, {}}, - {"ich_lr9_el2", ICH_LR9_EL2, {}}, - {"ich_lr10_el2", ICH_LR10_EL2, {}}, - {"ich_lr11_el2", ICH_LR11_EL2, {}}, - {"ich_lr12_el2", ICH_LR12_EL2, {}}, - {"ich_lr13_el2", ICH_LR13_EL2, {}}, - {"ich_lr14_el2", ICH_LR14_EL2, {}}, - {"ich_lr15_el2", ICH_LR15_EL2, {}}, - - // Cyclone registers - {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3, {AArch64::ProcCyclone}}, - - // v8.1a "Privileged Access Never" extension-specific system registers - {"pan", PAN, {AArch64::HasV8_1aOps}}, - - // v8.1a "Limited Ordering Regions" extension-specific system registers - {"lorsa_el1", LORSA_EL1, {AArch64::HasV8_1aOps}}, - {"lorea_el1", LOREA_EL1, {AArch64::HasV8_1aOps}}, - {"lorn_el1", LORN_EL1, {AArch64::HasV8_1aOps}}, - {"lorc_el1", LORC_EL1, {AArch64::HasV8_1aOps}}, - - // v8.1a "Virtualization host extensions" system registers - {"ttbr1_el2", TTBR1_EL2, {AArch64::HasV8_1aOps}}, - {"contextidr_el2", CONTEXTIDR_EL2, {AArch64::HasV8_1aOps}}, - {"cnthv_tval_el2", CNTHV_TVAL_EL2, {AArch64::HasV8_1aOps}}, - {"cnthv_cval_el2", CNTHV_CVAL_EL2, {AArch64::HasV8_1aOps}}, - {"cnthv_ctl_el2", CNTHV_CTL_EL2, {AArch64::HasV8_1aOps}}, - {"sctlr_el12", SCTLR_EL12, {AArch64::HasV8_1aOps}}, - {"cpacr_el12", CPACR_EL12, {AArch64::HasV8_1aOps}}, - {"ttbr0_el12", TTBR0_EL12, {AArch64::HasV8_1aOps}}, - {"ttbr1_el12", TTBR1_EL12, {AArch64::HasV8_1aOps}}, - {"tcr_el12", TCR_EL12, {AArch64::HasV8_1aOps}}, - {"afsr0_el12", AFSR0_EL12, {AArch64::HasV8_1aOps}}, - {"afsr1_el12", AFSR1_EL12, {AArch64::HasV8_1aOps}}, - {"esr_el12", ESR_EL12, {AArch64::HasV8_1aOps}}, - {"far_el12", FAR_EL12, {AArch64::HasV8_1aOps}}, - {"mair_el12", MAIR_EL12, {AArch64::HasV8_1aOps}}, - {"amair_el12", AMAIR_EL12, {AArch64::HasV8_1aOps}}, - {"vbar_el12", VBAR_EL12, {AArch64::HasV8_1aOps}}, - {"contextidr_el12", CONTEXTIDR_EL12, {AArch64::HasV8_1aOps}}, - {"cntkctl_el12", CNTKCTL_EL12, {AArch64::HasV8_1aOps}}, - {"cntp_tval_el02", CNTP_TVAL_EL02, {AArch64::HasV8_1aOps}}, - {"cntp_ctl_el02", CNTP_CTL_EL02, {AArch64::HasV8_1aOps}}, - {"cntp_cval_el02", CNTP_CVAL_EL02, {AArch64::HasV8_1aOps}}, - {"cntv_tval_el02", CNTV_TVAL_EL02, {AArch64::HasV8_1aOps}}, - {"cntv_ctl_el02", CNTV_CTL_EL02, {AArch64::HasV8_1aOps}}, - {"cntv_cval_el02", CNTV_CVAL_EL02, {AArch64::HasV8_1aOps}}, - {"spsr_el12", SPSR_EL12, {AArch64::HasV8_1aOps}}, - {"elr_el12", ELR_EL12, {AArch64::HasV8_1aOps}}, - - // v8.2a registers - {"uao", UAO, {AArch64::HasV8_2aOps}}, - - // v8.2a "Reliability, Availability and Serviceability" extensions registers - {"errselr_el1", ERRSELR_EL1, {AArch64::FeatureRAS}}, - {"erxctlr_el1", ERXCTLR_EL1, {AArch64::FeatureRAS}}, - {"erxstatus_el1", ERXSTATUS_EL1, {AArch64::FeatureRAS}}, - {"erxaddr_el1", ERXADDR_EL1, {AArch64::FeatureRAS}}, - {"erxmisc0_el1", ERXMISC0_EL1, {AArch64::FeatureRAS}}, - {"erxmisc1_el1", ERXMISC1_EL1, {AArch64::FeatureRAS}}, - {"disr_el1", DISR_EL1, {AArch64::FeatureRAS}}, - {"vdisr_el2", VDISR_EL2, {AArch64::FeatureRAS}}, - {"vsesr_el2", VSESR_EL2, {AArch64::FeatureRAS}}, - - // v8.2a "Statistical Profiling extension" registers - {"pmblimitr_el1", PMBLIMITR_EL1, {AArch64::FeatureSPE}}, - {"pmbptr_el1", PMBPTR_EL1, {AArch64::FeatureSPE}}, - {"pmbsr_el1", PMBSR_EL1, {AArch64::FeatureSPE}}, - {"pmbidr_el1", PMBIDR_EL1, {AArch64::FeatureSPE}}, - {"pmscr_el2", PMSCR_EL2, {AArch64::FeatureSPE}}, - {"pmscr_el12", PMSCR_EL12, {AArch64::FeatureSPE}}, - {"pmscr_el1", PMSCR_EL1, {AArch64::FeatureSPE}}, - {"pmsicr_el1", PMSICR_EL1, {AArch64::FeatureSPE}}, - {"pmsirr_el1", PMSIRR_EL1, {AArch64::FeatureSPE}}, - {"pmsfcr_el1", PMSFCR_EL1, {AArch64::FeatureSPE}}, - {"pmsevfr_el1", PMSEVFR_EL1, {AArch64::FeatureSPE}}, - {"pmslatfr_el1", PMSLATFR_EL1, {AArch64::FeatureSPE}}, - {"pmsidr_el1", PMSIDR_EL1, {AArch64::FeatureSPE}}, -}; - -uint32_t -AArch64SysReg::SysRegMapper::fromString(StringRef Name, - const FeatureBitset& FeatureBits, bool &Valid) const { - std::string NameLower = Name.lower(); - - // First search the registers shared by all - for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) { - if (SysRegMappings[i].isNameEqual(NameLower, FeatureBits)) { - Valid = true; - return SysRegMappings[i].Value; - } +namespace llvm { + namespace AArch64DC { +#define GET_DC_IMPL +#include "AArch64GenSystemOperands.inc" } +} - // Now try the instruction-specific registers (either read-only or - // write-only). - for (unsigned i = 0; i < NumInstMappings; ++i) { - if (InstMappings[i].isNameEqual(NameLower, FeatureBits)) { - Valid = true; - return InstMappings[i].Value; - } +namespace llvm { + namespace AArch64IC { +#define GET_IC_IMPL +#include "AArch64GenSystemOperands.inc" } +} +namespace llvm { + namespace AArch64ISB { +#define GET_ISB_IMPL +#include "AArch64GenSystemOperands.inc" + } +} +namespace llvm { + namespace AArch64PRFM { +#define GET_PRFM_IMPL +#include "AArch64GenSystemOperands.inc" + } +} + +namespace llvm { + namespace AArch64PState { +#define GET_PSTATE_IMPL +#include "AArch64GenSystemOperands.inc" + } +} + +namespace llvm { + namespace AArch64PSBHint { +#define GET_PSB_IMPL +#include "AArch64GenSystemOperands.inc" + } +} + +namespace llvm { + namespace AArch64SysReg { +#define GET_SYSREG_IMPL +#include "AArch64GenSystemOperands.inc" + } +} + +uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) { // Try to parse an S____ register name - Regex GenericRegPattern("^s([0-3])_([0-7])_c([0-9]|1[0-5])_c([0-9]|1[0-5])_([0-7])$"); + Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$"); SmallVector Ops; - if (!GenericRegPattern.match(NameLower, &Ops)) { - Valid = false; + if (!GenericRegPattern.match(Name.upper(), &Ops)) return -1; - } uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; uint32_t Bits; @@ -887,28 +98,10 @@ AArch64SysReg::SysRegMapper::fromString(StringRef Name, Ops[5].getAsInteger(10, Op2); Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; - Valid = true; return Bits; } -std::string -AArch64SysReg::SysRegMapper::toString(uint32_t Bits, - const FeatureBitset& FeatureBits) const { - // First search the registers shared by all - for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) { - if (SysRegMappings[i].isValueEqual(Bits, FeatureBits)) { - return SysRegMappings[i].Name; - } - } - - // Now try the instruction-specific registers (either read-only or - // write-only). - for (unsigned i = 0; i < NumInstMappings; ++i) { - if (InstMappings[i].isValueEqual(Bits, FeatureBits)) { - return InstMappings[i].Name; - } - } - +std::string AArch64SysReg::genericRegisterString(uint32_t Bits) { assert(Bits < 0x10000); uint32_t Op0 = (Bits >> 14) & 0x3; uint32_t Op1 = (Bits >> 11) & 0x7; @@ -916,44 +109,13 @@ AArch64SysReg::SysRegMapper::toString(uint32_t Bits, uint32_t CRm = (Bits >> 3) & 0xf; uint32_t Op2 = Bits & 0x7; - return "s" + utostr(Op0)+ "_" + utostr(Op1) + "_c" + utostr(CRn) - + "_c" + utostr(CRm) + "_" + utostr(Op2); + return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" + + utostr(CRm) + "_" + utostr(Op2); } -const AArch64NamedImmMapper::Mapping AArch64TLBI::TLBIMapper::TLBIMappings[] = { - {"ipas2e1is", IPAS2E1IS, {}}, - {"ipas2le1is", IPAS2LE1IS, {}}, - {"vmalle1is", VMALLE1IS, {}}, - {"alle2is", ALLE2IS, {}}, - {"alle3is", ALLE3IS, {}}, - {"vae1is", VAE1IS, {}}, - {"vae2is", VAE2IS, {}}, - {"vae3is", VAE3IS, {}}, - {"aside1is", ASIDE1IS, {}}, - {"vaae1is", VAAE1IS, {}}, - {"alle1is", ALLE1IS, {}}, - {"vale1is", VALE1IS, {}}, - {"vale2is", VALE2IS, {}}, - {"vale3is", VALE3IS, {}}, - {"vmalls12e1is", VMALLS12E1IS, {}}, - {"vaale1is", VAALE1IS, {}}, - {"ipas2e1", IPAS2E1, {}}, - {"ipas2le1", IPAS2LE1, {}}, - {"vmalle1", VMALLE1, {}}, - {"alle2", ALLE2, {}}, - {"alle3", ALLE3, {}}, - {"vae1", VAE1, {}}, - {"vae2", VAE2, {}}, - {"vae3", VAE3, {}}, - {"aside1", ASIDE1, {}}, - {"vaae1", VAAE1, {}}, - {"alle1", ALLE1, {}}, - {"vale1", VALE1, {}}, - {"vale2", VALE2, {}}, - {"vale3", VALE3, {}}, - {"vmalls12e1", VMALLS12E1, {}}, - {"vaale1", VAALE1, {}} -}; - -AArch64TLBI::TLBIMapper::TLBIMapper() - : AArch64NamedImmMapper(TLBIMappings, 0) {} +namespace llvm { + namespace AArch64TLBI { +#define GET_TLBI_IMPL +#include "AArch64GenSystemOperands.inc" + } +} diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h index f4676e48c0c1..dcc39176031c 100644 --- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h +++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h @@ -266,231 +266,85 @@ inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { } } // end namespace AArch64CC -/// Instances of this class can perform bidirectional mapping from random -/// identifier strings to operand encodings. For example "MSR" takes a named -/// system-register which must be encoded somehow and decoded for printing. This -/// central location means that the information for those transformations is not -/// duplicated and remains in sync. -/// -/// FIXME: currently the algorithm is a completely unoptimised linear -/// search. Obviously this could be improved, but we would probably want to work -/// out just how often these instructions are emitted before working on it. It -/// might even be optimal to just reorder the tables for the common instructions -/// rather than changing the algorithm. -struct AArch64NamedImmMapper { - struct Mapping { +namespace AArch64AT{ + struct AT { const char *Name; - uint32_t Value; - // Set of features this mapping is available for - // Zero value of FeatureBitSet means the mapping is always available - FeatureBitset FeatureBitSet; - - bool isNameEqual(const std::string &Other, - const FeatureBitset &FeatureBits) const { - if (FeatureBitSet.any() && - (FeatureBitSet & FeatureBits).none()) - return false; - return Name == Other; - } - - bool isValueEqual(uint32_t Other, - const FeatureBitset& FeatureBits) const { - if (FeatureBitSet.any() && - (FeatureBitSet & FeatureBits).none()) - return false; - return Value == Other; - } + uint16_t Encoding; }; - template - AArch64NamedImmMapper(const Mapping (&Mappings)[N], uint32_t TooBigImm) - : Mappings(&Mappings[0]), NumMappings(N), TooBigImm(TooBigImm) {} - - // Maps value to string, depending on availability for FeatureBits given - StringRef toString(uint32_t Value, const FeatureBitset& FeatureBits, - bool &Valid) const; - // Maps string to value, depending on availability for FeatureBits given - uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits, - bool &Valid) const; - - /// Many of the instructions allow an alternative assembly form consisting of - /// a simple immediate. Currently the only valid forms are ranges [0, N) where - /// N being 0 indicates no immediate syntax-form is allowed. - bool validImm(uint32_t Value) const; -protected: - const Mapping *Mappings; - size_t NumMappings; - uint32_t TooBigImm; -}; - -namespace AArch64AT { - enum ATValues { - Invalid = -1, // Op0 Op1 CRn CRm Op2 - S1E1R = 0x43c0, // 01 000 0111 1000 000 - S1E2R = 0x63c0, // 01 100 0111 1000 000 - S1E3R = 0x73c0, // 01 110 0111 1000 000 - S1E1W = 0x43c1, // 01 000 0111 1000 001 - S1E2W = 0x63c1, // 01 100 0111 1000 001 - S1E3W = 0x73c1, // 01 110 0111 1000 001 - S1E0R = 0x43c2, // 01 000 0111 1000 010 - S1E0W = 0x43c3, // 01 000 0111 1000 011 - S12E1R = 0x63c4, // 01 100 0111 1000 100 - S12E1W = 0x63c5, // 01 100 0111 1000 101 - S12E0R = 0x63c6, // 01 100 0111 1000 110 - S12E0W = 0x63c7, // 01 100 0111 1000 111 - S1E1RP = 0x43c8, // 01 000 0111 1001 000 - S1E1WP = 0x43c9 // 01 000 0111 1001 001 - }; - - struct ATMapper : AArch64NamedImmMapper { - const static Mapping ATMappings[]; - - ATMapper(); - }; + #define GET_AT_DECL + #include "AArch64GenSystemOperands.inc" } namespace AArch64DB { - enum DBValues { - Invalid = -1, - OSHLD = 0x1, - OSHST = 0x2, - OSH = 0x3, - NSHLD = 0x5, - NSHST = 0x6, - NSH = 0x7, - ISHLD = 0x9, - ISHST = 0xa, - ISH = 0xb, - LD = 0xd, - ST = 0xe, - SY = 0xf + struct DB { + const char *Name; + uint16_t Encoding; }; - struct DBarrierMapper : AArch64NamedImmMapper { - const static Mapping DBarrierMappings[]; - - DBarrierMapper(); - }; + #define GET_DB_DECL + #include "AArch64GenSystemOperands.inc" } namespace AArch64DC { - enum DCValues { - Invalid = -1, // Op1 CRn CRm Op2 - ZVA = 0x5ba1, // 01 011 0111 0100 001 - IVAC = 0x43b1, // 01 000 0111 0110 001 - ISW = 0x43b2, // 01 000 0111 0110 010 - CVAC = 0x5bd1, // 01 011 0111 1010 001 - CSW = 0x43d2, // 01 000 0111 1010 010 - CVAU = 0x5bd9, // 01 011 0111 1011 001 - CIVAC = 0x5bf1, // 01 011 0111 1110 001 - CISW = 0x43f2 // 01 000 0111 1110 010 - }; - - struct DCMapper : AArch64NamedImmMapper { - const static Mapping DCMappings[]; - - DCMapper(); + struct DC { + const char *Name; + uint16_t Encoding; }; + #define GET_DC_DECL + #include "AArch64GenSystemOperands.inc" } namespace AArch64IC { - enum ICValues { - Invalid = -1, // Op1 CRn CRm Op2 - IALLUIS = 0x0388, // 000 0111 0001 000 - IALLU = 0x03a8, // 000 0111 0101 000 - IVAU = 0x1ba9 // 011 0111 0101 001 + struct IC { + const char *Name; + uint16_t Encoding; + bool NeedsReg; }; - - - struct ICMapper : AArch64NamedImmMapper { - const static Mapping ICMappings[]; - - ICMapper(); - }; - - static inline bool NeedsRegister(ICValues Val) { - return Val == IVAU; - } + #define GET_IC_DECL + #include "AArch64GenSystemOperands.inc" } namespace AArch64ISB { - enum ISBValues { - Invalid = -1, - SY = 0xf - }; - struct ISBMapper : AArch64NamedImmMapper { - const static Mapping ISBMappings[]; - - ISBMapper(); + struct ISB { + const char *Name; + uint16_t Encoding; }; + #define GET_ISB_DECL + #include "AArch64GenSystemOperands.inc" } namespace AArch64PRFM { - enum PRFMValues { - Invalid = -1, - PLDL1KEEP = 0x00, - PLDL1STRM = 0x01, - PLDL2KEEP = 0x02, - PLDL2STRM = 0x03, - PLDL3KEEP = 0x04, - PLDL3STRM = 0x05, - PLIL1KEEP = 0x08, - PLIL1STRM = 0x09, - PLIL2KEEP = 0x0a, - PLIL2STRM = 0x0b, - PLIL3KEEP = 0x0c, - PLIL3STRM = 0x0d, - PSTL1KEEP = 0x10, - PSTL1STRM = 0x11, - PSTL2KEEP = 0x12, - PSTL2STRM = 0x13, - PSTL3KEEP = 0x14, - PSTL3STRM = 0x15 - }; - - struct PRFMMapper : AArch64NamedImmMapper { - const static Mapping PRFMMappings[]; - - PRFMMapper(); + struct PRFM { + const char *Name; + uint16_t Encoding; }; + #define GET_PRFM_DECL + #include "AArch64GenSystemOperands.inc" } namespace AArch64PState { - enum PStateValues { - Invalid = -1, - SPSel = 0x05, - DAIFSet = 0x1e, - DAIFClr = 0x1f, + struct PState { + const char *Name; + uint16_t Encoding; + FeatureBitset FeaturesRequired; - // v8.1a "Privileged Access Never" extension-specific PStates - PAN = 0x04, - - // v8.2a "User Access Override" extension-specific PStates - UAO = 0x03 + bool haveFeatures(FeatureBitset ActiveFeatures) const { + return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; + } }; - - struct PStateMapper : AArch64NamedImmMapper { - const static Mapping PStateMappings[]; - - PStateMapper(); - }; - + #define GET_PSTATE_DECL + #include "AArch64GenSystemOperands.inc" } namespace AArch64PSBHint { - enum PSBHintValues { - Invalid = -1, - // v8.2a "Statistical Profiling" extension-specific PSB operands - CSync = 0x11, // psb csync = hint #0x11 + struct PSB { + const char *Name; + uint16_t Encoding; }; - - struct PSBHintMapper : AArch64NamedImmMapper { - const static Mapping PSBHintMappings[]; - - PSBHintMapper(); - }; - + #define GET_PSB_DECL + #include "AArch64GenSystemOperands.inc" } namespace AArch64SE { @@ -574,769 +428,36 @@ AArch64StringToVectorLayout(StringRef LayoutStr) { } namespace AArch64SysReg { - enum SysRegROValues { - MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000 - DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000 - MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000 - OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100 - DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110 - PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110 - PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111 - MIDR_EL1 = 0xc000, // 11 000 0000 0000 000 - CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000 - CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001 - CTR_EL0 = 0xd801, // 11 011 0000 0000 001 - MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101 - REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110 - AIDR_EL1 = 0xc807, // 11 001 0000 0000 111 - DCZID_EL0 = 0xd807, // 11 011 0000 0000 111 - ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000 - ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001 - ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010 - ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011 - ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100 - ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101 - ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110 - ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111 - ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000 - ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001 - ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010 - ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011 - ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100 - ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101 - ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000 - ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001 - ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000 - ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001 - ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100 - ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101 - ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000 - ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 - ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 - ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 - ID_A64MMFR2_EL1 = 0xc03a, // 11 000 0000 0111 010 - MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 - MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 - MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 - RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001 - RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001 - RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001 - ISR_EL1 = 0xc608, // 11 000 1100 0001 000 - CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001 - CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010 - ID_MMFR4_EL1 = 0xc016, // 11 000 0000 0010 110 + struct SysReg { + const char *Name; + unsigned Encoding; + bool Readable; + bool Writeable; + FeatureBitset FeaturesRequired; - // Trace registers - TRCSTATR = 0x8818, // 10 001 0000 0011 000 - TRCIDR8 = 0x8806, // 10 001 0000 0000 110 - TRCIDR9 = 0x880e, // 10 001 0000 0001 110 - TRCIDR10 = 0x8816, // 10 001 0000 0010 110 - TRCIDR11 = 0x881e, // 10 001 0000 0011 110 - TRCIDR12 = 0x8826, // 10 001 0000 0100 110 - TRCIDR13 = 0x882e, // 10 001 0000 0101 110 - TRCIDR0 = 0x8847, // 10 001 0000 1000 111 - TRCIDR1 = 0x884f, // 10 001 0000 1001 111 - TRCIDR2 = 0x8857, // 10 001 0000 1010 111 - TRCIDR3 = 0x885f, // 10 001 0000 1011 111 - TRCIDR4 = 0x8867, // 10 001 0000 1100 111 - TRCIDR5 = 0x886f, // 10 001 0000 1101 111 - TRCIDR6 = 0x8877, // 10 001 0000 1110 111 - TRCIDR7 = 0x887f, // 10 001 0000 1111 111 - TRCOSLSR = 0x888c, // 10 001 0001 0001 100 - TRCPDSR = 0x88ac, // 10 001 0001 0101 100 - TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110 - TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110 - TRCLSR = 0x8bee, // 10 001 0111 1101 110 - TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110 - TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110 - TRCDEVID = 0x8b97, // 10 001 0111 0010 111 - TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111 - TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111 - TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111 - TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111 - TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111 - TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111 - TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111 - TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111 - TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111 - TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111 - TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111 - TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111 - TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111 - - // GICv3 registers - ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000 - ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000 - ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010 - ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010 - ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011 - ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001 - ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011 - ICH_ELSR_EL2 = 0xe65d, // 11 100 1100 1011 101 - - // RAS extension registers - ERRIDR_EL1 = 0xc298, // 11 000 0101 0011 000 - ERXFR_EL1 = 0xc2a0 // 11 000 0101 0100 000 + bool haveFeatures(FeatureBitset ActiveFeatures) const { + return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; + } }; - enum SysRegWOValues { - DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000 - OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100 - PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100 + #define GET_SYSREG_DECL + #include "AArch64GenSystemOperands.inc" - // Trace Registers - TRCOSLAR = 0x8884, // 10 001 0001 0000 100 - TRCLAR = 0x8be6, // 10 001 0111 1100 110 + const SysReg *lookupSysRegByName(StringRef); + const SysReg *lookupSysRegByEncoding(uint16_t); - // GICv3 registers - ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001 - ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001 - ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001 - ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101 - ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110 - ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111 - }; - - enum SysRegValues { - Invalid = -1, // Op0 Op1 CRn CRm Op2 - OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010 - OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010 - TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000 - MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000 - MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010 - DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000 - OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010 - DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000 - DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100 - DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100 - DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100 - DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100 - DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100 - DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100 - DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100 - DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100 - DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100 - DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100 - DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100 - DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100 - DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100 - DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100 - DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100 - DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100 - DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101 - DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101 - DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101 - DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101 - DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101 - DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101 - DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101 - DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101 - DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101 - DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101 - DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101 - DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101 - DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101 - DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101 - DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101 - DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101 - DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110 - DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110 - DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110 - DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110 - DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110 - DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110 - DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110 - DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110 - DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110 - DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110 - DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110 - DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110 - DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110 - DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110 - DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110 - DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110 - DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111 - DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111 - DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111 - DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111 - DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111 - DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111 - DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111 - DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111 - DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111 - DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111 - DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111 - DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111 - DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111 - DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111 - DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111 - DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111 - TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000 - OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100 - DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100 - DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110 - DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110 - CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000 - VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000 - VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101 - CPACR_EL1 = 0xc082, // 11 000 0001 0000 010 - SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000 - SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000 - SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000 - ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001 - ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001 - ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001 - HCR_EL2 = 0xe088, // 11 100 0001 0001 000 - SCR_EL3 = 0xf088, // 11 110 0001 0001 000 - MDCR_EL2 = 0xe089, // 11 100 0001 0001 001 - SDER32_EL3 = 0xf089, // 11 110 0001 0001 001 - CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010 - CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010 - HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011 - HACR_EL2 = 0xe08f, // 11 100 0001 0001 111 - MDCR_EL3 = 0xf099, // 11 110 0001 0011 001 - TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000 - TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000 - TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000 - TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001 - TCR_EL1 = 0xc102, // 11 000 0010 0000 010 - TCR_EL2 = 0xe102, // 11 100 0010 0000 010 - TCR_EL3 = 0xf102, // 11 110 0010 0000 010 - VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000 - VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010 - DACR32_EL2 = 0xe180, // 11 100 0011 0000 000 - SPSR_EL1 = 0xc200, // 11 000 0100 0000 000 - SPSR_EL2 = 0xe200, // 11 100 0100 0000 000 - SPSR_EL3 = 0xf200, // 11 110 0100 0000 000 - ELR_EL1 = 0xc201, // 11 000 0100 0000 001 - ELR_EL2 = 0xe201, // 11 100 0100 0000 001 - ELR_EL3 = 0xf201, // 11 110 0100 0000 001 - SP_EL0 = 0xc208, // 11 000 0100 0001 000 - SP_EL1 = 0xe208, // 11 100 0100 0001 000 - SP_EL2 = 0xf208, // 11 110 0100 0001 000 - SPSel = 0xc210, // 11 000 0100 0010 000 - NZCV = 0xda10, // 11 011 0100 0010 000 - DAIF = 0xda11, // 11 011 0100 0010 001 - CurrentEL = 0xc212, // 11 000 0100 0010 010 - SPSR_irq = 0xe218, // 11 100 0100 0011 000 - SPSR_abt = 0xe219, // 11 100 0100 0011 001 - SPSR_und = 0xe21a, // 11 100 0100 0011 010 - SPSR_fiq = 0xe21b, // 11 100 0100 0011 011 - FPCR = 0xda20, // 11 011 0100 0100 000 - FPSR = 0xda21, // 11 011 0100 0100 001 - DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000 - DLR_EL0 = 0xda29, // 11 011 0100 0101 001 - IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001 - AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000 - AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000 - AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000 - AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001 - AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001 - AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001 - ESR_EL1 = 0xc290, // 11 000 0101 0010 000 - ESR_EL2 = 0xe290, // 11 100 0101 0010 000 - ESR_EL3 = 0xf290, // 11 110 0101 0010 000 - FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000 - FAR_EL1 = 0xc300, // 11 000 0110 0000 000 - FAR_EL2 = 0xe300, // 11 100 0110 0000 000 - FAR_EL3 = 0xf300, // 11 110 0110 0000 000 - HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100 - PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000 - PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000 - PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001 - PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010 - PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011 - PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101 - PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000 - PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001 - PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010 - PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000 - PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001 - PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010 - PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011 - MAIR_EL1 = 0xc510, // 11 000 1010 0010 000 - MAIR_EL2 = 0xe510, // 11 100 1010 0010 000 - MAIR_EL3 = 0xf510, // 11 110 1010 0010 000 - AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000 - AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000 - AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000 - VBAR_EL1 = 0xc600, // 11 000 1100 0000 000 - VBAR_EL2 = 0xe600, // 11 100 1100 0000 000 - VBAR_EL3 = 0xf600, // 11 110 1100 0000 000 - RMR_EL1 = 0xc602, // 11 000 1100 0000 010 - RMR_EL2 = 0xe602, // 11 100 1100 0000 010 - RMR_EL3 = 0xf602, // 11 110 1100 0000 010 - CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001 - TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010 - TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010 - TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010 - TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011 - TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100 - CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000 - CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011 - CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000 - CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000 - CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000 - CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000 - CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000 - CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001 - CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001 - CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001 - CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010 - CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010 - CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010 - CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000 - CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001 - CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010 - PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000 - PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001 - PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010 - PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011 - PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100 - PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101 - PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110 - PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111 - PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000 - PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001 - PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010 - PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011 - PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100 - PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101 - PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110 - PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111 - PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000 - PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001 - PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010 - PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011 - PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100 - PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101 - PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110 - PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111 - PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000 - PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001 - PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010 - PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011 - PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100 - PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101 - PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110 - PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111 - PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000 - PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001 - PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010 - PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011 - PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100 - PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101 - PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110 - PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111 - PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000 - PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001 - PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010 - PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011 - PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100 - PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101 - PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110 - PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111 - PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000 - PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001 - PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010 - PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011 - PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100 - PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101 - PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110 - PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111 - PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000 - PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001 - PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010 - PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011 - PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100 - PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101 - PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110 - - // Trace registers - TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000 - TRCPROCSELR = 0x8810, // 10 001 0000 0010 000 - TRCCONFIGR = 0x8820, // 10 001 0000 0100 000 - TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000 - TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000 - TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000 - TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000 - TRCTSCTLR = 0x8860, // 10 001 0000 1100 000 - TRCSYNCPR = 0x8868, // 10 001 0000 1101 000 - TRCCCCTLR = 0x8870, // 10 001 0000 1110 000 - TRCBBCTLR = 0x8878, // 10 001 0000 1111 000 - TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001 - TRCQCTLR = 0x8809, // 10 001 0000 0001 001 - TRCVICTLR = 0x8802, // 10 001 0000 0000 010 - TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010 - TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010 - TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010 - TRCVDCTLR = 0x8842, // 10 001 0000 1000 010 - TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010 - TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010 - TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100 - TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100 - TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100 - TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100 - TRCSEQSTR = 0x883c, // 10 001 0000 0111 100 - TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100 - TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101 - TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101 - TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101 - TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101 - TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101 - TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101 - TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101 - TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101 - TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101 - TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101 - TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101 - TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101 - TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111 - TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111 - TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111 - TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111 - TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111 - TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111 - TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111 - TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111 - TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000 - TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000 - TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000 - TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000 - TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000 - TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000 - TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000 - TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000 - TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000 - TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000 - TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000 - TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000 - TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000 - TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000 - TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001 - TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001 - TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001 - TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001 - TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001 - TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001 - TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001 - TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001 - TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001 - TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001 - TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001 - TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001 - TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001 - TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001 - TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001 - TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001 - TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010 - TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010 - TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010 - TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010 - TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010 - TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010 - TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010 - TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010 - TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010 - TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010 - TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010 - TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010 - TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010 - TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010 - TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010 - TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010 - TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011 - TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011 - TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011 - TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011 - TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011 - TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011 - TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011 - TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011 - TRCPDCR = 0x88a4, // 10 001 0001 0100 100 - TRCACVR0 = 0x8900, // 10 001 0010 0000 000 - TRCACVR1 = 0x8910, // 10 001 0010 0010 000 - TRCACVR2 = 0x8920, // 10 001 0010 0100 000 - TRCACVR3 = 0x8930, // 10 001 0010 0110 000 - TRCACVR4 = 0x8940, // 10 001 0010 1000 000 - TRCACVR5 = 0x8950, // 10 001 0010 1010 000 - TRCACVR6 = 0x8960, // 10 001 0010 1100 000 - TRCACVR7 = 0x8970, // 10 001 0010 1110 000 - TRCACVR8 = 0x8901, // 10 001 0010 0000 001 - TRCACVR9 = 0x8911, // 10 001 0010 0010 001 - TRCACVR10 = 0x8921, // 10 001 0010 0100 001 - TRCACVR11 = 0x8931, // 10 001 0010 0110 001 - TRCACVR12 = 0x8941, // 10 001 0010 1000 001 - TRCACVR13 = 0x8951, // 10 001 0010 1010 001 - TRCACVR14 = 0x8961, // 10 001 0010 1100 001 - TRCACVR15 = 0x8971, // 10 001 0010 1110 001 - TRCACATR0 = 0x8902, // 10 001 0010 0000 010 - TRCACATR1 = 0x8912, // 10 001 0010 0010 010 - TRCACATR2 = 0x8922, // 10 001 0010 0100 010 - TRCACATR3 = 0x8932, // 10 001 0010 0110 010 - TRCACATR4 = 0x8942, // 10 001 0010 1000 010 - TRCACATR5 = 0x8952, // 10 001 0010 1010 010 - TRCACATR6 = 0x8962, // 10 001 0010 1100 010 - TRCACATR7 = 0x8972, // 10 001 0010 1110 010 - TRCACATR8 = 0x8903, // 10 001 0010 0000 011 - TRCACATR9 = 0x8913, // 10 001 0010 0010 011 - TRCACATR10 = 0x8923, // 10 001 0010 0100 011 - TRCACATR11 = 0x8933, // 10 001 0010 0110 011 - TRCACATR12 = 0x8943, // 10 001 0010 1000 011 - TRCACATR13 = 0x8953, // 10 001 0010 1010 011 - TRCACATR14 = 0x8963, // 10 001 0010 1100 011 - TRCACATR15 = 0x8973, // 10 001 0010 1110 011 - TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100 - TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100 - TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100 - TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100 - TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101 - TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101 - TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101 - TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101 - TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110 - TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110 - TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110 - TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110 - TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111 - TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111 - TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111 - TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111 - TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000 - TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000 - TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000 - TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000 - TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000 - TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000 - TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000 - TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000 - TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001 - TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001 - TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001 - TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001 - TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001 - TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001 - TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001 - TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001 - TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010 - TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010 - TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010 - TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010 - TRCITCTRL = 0x8b84, // 10 001 0111 0000 100 - TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110 - TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110 - - // GICv3 registers - ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011 - ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011 - ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000 - ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100 - ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100 - ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101 - ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101 - ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101 - ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110 - ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111 - ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111 - ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000 - ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100 - ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101 - ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110 - ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111 - ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000 - ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001 - ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010 - ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011 - ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000 - ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001 - ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010 - ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011 - ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000 - ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001 - ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010 - ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011 - ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000 - ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010 - ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111 - ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100 - ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000 - ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001 - ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010 - ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011 - ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100 - ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101 - ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110 - ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111 - ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000 - ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001 - ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010 - ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011 - ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100 - ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101 - ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110 - ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111 - - // v8.1a "Privileged Access Never" extension-specific system registers - PAN = 0xc213, // 11 000 0100 0010 011 - - // v8.1a "Limited Ordering Regions" extension-specific system registers - LORSA_EL1 = 0xc520, // 11 000 1010 0100 000 - LOREA_EL1 = 0xc521, // 11 000 1010 0100 001 - LORN_EL1 = 0xc522, // 11 000 1010 0100 010 - LORC_EL1 = 0xc523, // 11 000 1010 0100 011 - LORID_EL1 = 0xc527, // 11 000 1010 0100 111 - - // v8.1a "Virtualization host extensions" system registers - TTBR1_EL2 = 0xe101, // 11 100 0010 0000 001 - CONTEXTIDR_EL2 = 0xe681, // 11 100 1101 0000 001 - CNTHV_TVAL_EL2 = 0xe718, // 11 100 1110 0011 000 - CNTHV_CVAL_EL2 = 0xe71a, // 11 100 1110 0011 010 - CNTHV_CTL_EL2 = 0xe719, // 11 100 1110 0011 001 - SCTLR_EL12 = 0xe880, // 11 101 0001 0000 000 - CPACR_EL12 = 0xe882, // 11 101 0001 0000 010 - TTBR0_EL12 = 0xe900, // 11 101 0010 0000 000 - TTBR1_EL12 = 0xe901, // 11 101 0010 0000 001 - TCR_EL12 = 0xe902, // 11 101 0010 0000 010 - AFSR0_EL12 = 0xea88, // 11 101 0101 0001 000 - AFSR1_EL12 = 0xea89, // 11 101 0101 0001 001 - ESR_EL12 = 0xea90, // 11 101 0101 0010 000 - FAR_EL12 = 0xeb00, // 11 101 0110 0000 000 - MAIR_EL12 = 0xed10, // 11 101 1010 0010 000 - AMAIR_EL12 = 0xed18, // 11 101 1010 0011 000 - VBAR_EL12 = 0xee00, // 11 101 1100 0000 000 - CONTEXTIDR_EL12 = 0xee81, // 11 101 1101 0000 001 - CNTKCTL_EL12 = 0xef08, // 11 101 1110 0001 000 - CNTP_TVAL_EL02 = 0xef10, // 11 101 1110 0010 000 - CNTP_CTL_EL02 = 0xef11, // 11 101 1110 0010 001 - CNTP_CVAL_EL02 = 0xef12, // 11 101 1110 0010 010 - CNTV_TVAL_EL02 = 0xef18, // 11 101 1110 0011 000 - CNTV_CTL_EL02 = 0xef19, // 11 101 1110 0011 001 - CNTV_CVAL_EL02 = 0xef1a, // 11 101 1110 0011 010 - SPSR_EL12 = 0xea00, // 11 101 0100 0000 000 - ELR_EL12 = 0xea01, // 11 101 0100 0000 001 - - // RAS extension registers - ERRSELR_EL1 = 0xc299, // 11 000 0101 0011 001 - ERXCTLR_EL1 = 0xc2a1, // 11 000 0101 0100 001 - ERXSTATUS_EL1 = 0xc2a2, // 11 000 0101 0100 010 - ERXADDR_EL1 = 0xc2a3, // 11 000 0101 0100 011 - ERXMISC0_EL1 = 0xc2a8, // 11 000 0101 0101 000 - ERXMISC1_EL1 = 0xc2a9, // 11 000 0101 0101 001 - DISR_EL1 = 0xc609, // 11 000 1100 0001 001 - VDISR_EL2 = 0xe609, // 11 100 1100 0001 001 - VSESR_EL2 = 0xe293, // 11 100 0101 0010 011 - - // v8.2a registers - UAO = 0xc214, // 11 000 0100 0010 100 - - // v8.2a "Statistical Profiling extension" registers - PMBLIMITR_EL1 = 0xc4d0, // 11 000 1001 1010 000 - PMBPTR_EL1 = 0xc4d1, // 11 000 1001 1010 001 - PMBSR_EL1 = 0xc4d3, // 11 000 1001 1010 011 - PMBIDR_EL1 = 0xc4d7, // 11 000 1001 1010 111 - PMSCR_EL2 = 0xe4c8, // 11 100 1001 1001 000 - PMSCR_EL12 = 0xecc8, // 11 101 1001 1001 000 - PMSCR_EL1 = 0xc4c8, // 11 000 1001 1001 000 - PMSICR_EL1 = 0xc4ca, // 11 000 1001 1001 010 - PMSIRR_EL1 = 0xc4cb, // 11 000 1001 1001 011 - PMSFCR_EL1 = 0xc4cc, // 11 000 1001 1001 100 - PMSEVFR_EL1 = 0xc4cd, // 11 000 1001 1001 101 - PMSLATFR_EL1 = 0xc4ce, // 11 000 1001 1001 110 - PMSIDR_EL1 = 0xc4cf, // 11 000 1001 1001 111 - - // Cyclone specific system registers - CPM_IOACC_CTL_EL3 = 0xff90, - }; - - // Note that these do not inherit from AArch64NamedImmMapper. This class is - // sufficiently different in its behaviour that I don't believe it's worth - // burdening the common AArch64NamedImmMapper with abstractions only needed in - // this one case. - struct SysRegMapper { - static const AArch64NamedImmMapper::Mapping SysRegMappings[]; - - const AArch64NamedImmMapper::Mapping *InstMappings; - size_t NumInstMappings; - - SysRegMapper() { } - uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits, - bool &Valid) const; - std::string toString(uint32_t Bits, const FeatureBitset& FeatureBits) const; - }; - - struct MSRMapper : SysRegMapper { - static const AArch64NamedImmMapper::Mapping MSRMappings[]; - MSRMapper(); - }; - - struct MRSMapper : SysRegMapper { - static const AArch64NamedImmMapper::Mapping MRSMappings[]; - MRSMapper(); - }; - - uint32_t ParseGenericRegister(StringRef Name, bool &Valid); + uint32_t parseGenericRegister(StringRef Name); + std::string genericRegisterString(uint32_t Bits); } namespace AArch64TLBI { - enum TLBIValues { - Invalid = -1, // Op0 Op1 CRn CRm Op2 - IPAS2E1IS = 0x6401, // 01 100 1000 0000 001 - IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101 - VMALLE1IS = 0x4418, // 01 000 1000 0011 000 - ALLE2IS = 0x6418, // 01 100 1000 0011 000 - ALLE3IS = 0x7418, // 01 110 1000 0011 000 - VAE1IS = 0x4419, // 01 000 1000 0011 001 - VAE2IS = 0x6419, // 01 100 1000 0011 001 - VAE3IS = 0x7419, // 01 110 1000 0011 001 - ASIDE1IS = 0x441a, // 01 000 1000 0011 010 - VAAE1IS = 0x441b, // 01 000 1000 0011 011 - ALLE1IS = 0x641c, // 01 100 1000 0011 100 - VALE1IS = 0x441d, // 01 000 1000 0011 101 - VALE2IS = 0x641d, // 01 100 1000 0011 101 - VALE3IS = 0x741d, // 01 110 1000 0011 101 - VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110 - VAALE1IS = 0x441f, // 01 000 1000 0011 111 - IPAS2E1 = 0x6421, // 01 100 1000 0100 001 - IPAS2LE1 = 0x6425, // 01 100 1000 0100 101 - VMALLE1 = 0x4438, // 01 000 1000 0111 000 - ALLE2 = 0x6438, // 01 100 1000 0111 000 - ALLE3 = 0x7438, // 01 110 1000 0111 000 - VAE1 = 0x4439, // 01 000 1000 0111 001 - VAE2 = 0x6439, // 01 100 1000 0111 001 - VAE3 = 0x7439, // 01 110 1000 0111 001 - ASIDE1 = 0x443a, // 01 000 1000 0111 010 - VAAE1 = 0x443b, // 01 000 1000 0111 011 - ALLE1 = 0x643c, // 01 100 1000 0111 100 - VALE1 = 0x443d, // 01 000 1000 0111 101 - VALE2 = 0x643d, // 01 100 1000 0111 101 - VALE3 = 0x743d, // 01 110 1000 0111 101 - VMALLS12E1 = 0x643e, // 01 100 1000 0111 110 - VAALE1 = 0x443f // 01 000 1000 0111 111 + struct TLBI { + const char *Name; + uint16_t Encoding; + bool NeedsReg; }; - - struct TLBIMapper : AArch64NamedImmMapper { - const static Mapping TLBIMappings[]; - - TLBIMapper(); - }; - - static inline bool NeedsRegister(TLBIValues Val) { - switch (Val) { - case VMALLE1IS: - case ALLE2IS: - case ALLE3IS: - case ALLE1IS: - case VMALLS12E1IS: - case VMALLE1: - case ALLE2: - case ALLE3: - case ALLE1: - case VMALLS12E1: - return false; - default: - return true; - } - } + #define GET_TLBI_DECL + #include "AArch64GenSystemOperands.inc" } namespace AArch64II { diff --git a/llvm/test/CodeGen/AArch64/special-reg.ll b/llvm/test/CodeGen/AArch64/special-reg.ll index 91c32158d420..4b8c75b70985 100644 --- a/llvm/test/CodeGen/AArch64/special-reg.ll +++ b/llvm/test/CodeGen/AArch64/special-reg.ll @@ -35,7 +35,7 @@ entry: define void @write_daifset() nounwind { entry: ; CHECK-LABEL: write_daifset: -; CHECK: msr DAIFSET, #2 +; CHECK: msr DAIFSet, #2 call void @llvm.write_register.i64(metadata !2, i64 2) ret void } diff --git a/llvm/test/MC/AArch64/arm64-spsel-sysreg.s b/llvm/test/MC/AArch64/arm64-spsel-sysreg.s index f1d94d8c2d8b..f1c675f6edf4 100644 --- a/llvm/test/MC/AArch64/arm64-spsel-sysreg.s +++ b/llvm/test/MC/AArch64/arm64-spsel-sysreg.s @@ -8,11 +8,11 @@ msr ESR_EL1, x0 mrs x0, SPSel mrs x0, ESR_EL1 -// CHECK: msr SPSEL, #0 // encoding: [0xbf,0x40,0x00,0xd5] -// CHECK: msr SPSEL, x0 // encoding: [0x00,0x42,0x18,0xd5] -// CHECK: msr DAIFSET, #0 // encoding: [0xdf,0x40,0x03,0xd5] +// CHECK: msr SPSel, #0 // encoding: [0xbf,0x40,0x00,0xd5] +// CHECK: msr SPSel, x0 // encoding: [0x00,0x42,0x18,0xd5] +// CHECK: msr DAIFSet, #0 // encoding: [0xdf,0x40,0x03,0xd5] // CHECK: msr ESR_EL1, x0 // encoding: [0x00,0x52,0x18,0xd5] -// CHECK: mrs x0, SPSEL // encoding: [0x00,0x42,0x38,0xd5] +// CHECK: mrs x0, SPSel // encoding: [0x00,0x42,0x38,0xd5] // CHECK: mrs x0, ESR_EL1 // encoding: [0x00,0x52,0x38,0xd5] diff --git a/llvm/test/MC/AArch64/arm64-system-encoding.s b/llvm/test/MC/AArch64/arm64-system-encoding.s index eb29117428fd..ef4037b7bf3f 100644 --- a/llvm/test/MC/AArch64/arm64-system-encoding.s +++ b/llvm/test/MC/AArch64/arm64-system-encoding.s @@ -167,7 +167,7 @@ foo: ; CHECK: msr CPTR_EL2, x3 ; encoding: [0x43,0x11,0x1c,0xd5] ; CHECK: msr CPTR_EL3, x3 ; encoding: [0x43,0x11,0x1e,0xd5] ; CHECK: msr CSSELR_EL1, x3 ; encoding: [0x03,0x00,0x1a,0xd5] -; CHECK: msr CURRENTEL, x3 ; encoding: [0x43,0x42,0x18,0xd5] +; CHECK: msr CurrentEL, x3 ; encoding: [0x43,0x42,0x18,0xd5] ; CHECK: msr DACR32_EL2, x3 ; encoding: [0x03,0x30,0x1c,0xd5] ; CHECK: msr ESR_EL1, x3 ; encoding: [0x03,0x52,0x18,0xd5] ; CHECK: msr ESR_EL2, x3 ; encoding: [0x03,0x52,0x1c,0xd5] @@ -213,7 +213,7 @@ foo: ; CHECK: msr VPIDR_EL2, x3 ; encoding: [0x03,0x00,0x1c,0xd5] ; CHECK: msr VTCR_EL2, x3 ; encoding: [0x43,0x21,0x1c,0xd5] ; CHECK: msr VTTBR_EL2, x3 ; encoding: [0x03,0x21,0x1c,0xd5] -; CHECK: msr SPSEL, x3 ; encoding: [0x03,0x42,0x18,0xd5] +; CHECK: msr SPSel, x3 ; encoding: [0x03,0x42,0x18,0xd5] ; CHECK: msr S3_2_C11_C6_4, x1 ; encoding: [0x81,0xb6,0x1a,0xd5] ; CHECK: msr S0_0_C0_C0_0, x0 ; encoding: [0x00,0x00,0x00,0xd5] ; CHECK: msr S1_2_C3_C4_5, x2 ; encoding: [0xa2,0x34,0x0a,0xd5] @@ -439,7 +439,7 @@ foo: ; CHECK: mrs x3, CPTR_EL3 ; encoding: [0x43,0x11,0x3e,0xd5] ; CHECK: mrs x3, CSSELR_EL1 ; encoding: [0x03,0x00,0x3a,0xd5] ; CHECK: mrs x3, CTR_EL0 ; encoding: [0x23,0x00,0x3b,0xd5] -; CHECK: mrs x3, CURRENTEL ; encoding: [0x43,0x42,0x38,0xd5] +; CHECK: mrs x3, CurrentEL ; encoding: [0x43,0x42,0x38,0xd5] ; CHECK: mrs x3, DACR32_EL2 ; encoding: [0x03,0x30,0x3c,0xd5] ; CHECK: mrs x3, DCZID_EL0 ; encoding: [0xe3,0x00,0x3b,0xd5] ; CHECK: mrs x3, REVIDR_EL1 ; encoding: [0xc3,0x00,0x38,0xd5] diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s index 69229848fde3..8a82c99eb8c1 100644 --- a/llvm/test/MC/AArch64/basic-a64-instructions.s +++ b/llvm/test/MC/AArch64/basic-a64-instructions.s @@ -3571,9 +3571,9 @@ _func: msr spsel, #0 msr daifset, #15 msr daifclr, #12 -// CHECK: msr {{spsel|SPSEL}}, #0 // encoding: [0xbf,0x40,0x00,0xd5] -// CHECK: msr {{daifset|DAIFSET}}, #15 // encoding: [0xdf,0x4f,0x03,0xd5] -// CHECK: msr {{daifclr|DAIFCLR}}, #12 // encoding: [0xff,0x4c,0x03,0xd5] +// CHECK: msr {{SPSel|SPSEL}}, #0 // encoding: [0xbf,0x40,0x00,0xd5] +// CHECK: msr {{DAIFSet|DAIFSET}}, #15 // encoding: [0xdf,0x4f,0x03,0xd5] +// CHECK: msr {{DAIFClr|DAIFCLR}}, #12 // encoding: [0xff,0x4c,0x03,0xd5] sys #7, c5, c9, #7, x5 sys #0, c15, c15, #2 @@ -4070,14 +4070,14 @@ _func: // CHECK: msr {{sp_el0|SP_EL0}}, x12 // encoding: [0x0c,0x41,0x18,0xd5] // CHECK: msr {{sp_el1|SP_EL1}}, x12 // encoding: [0x0c,0x41,0x1c,0xd5] // CHECK: msr {{sp_el2|SP_EL2}}, x12 // encoding: [0x0c,0x41,0x1e,0xd5] -// CHECK: msr {{spsel|SPSEL}}, x12 // encoding: [0x0c,0x42,0x18,0xd5] +// CHECK: msr {{SPSel|SPSEL}}, x12 // encoding: [0x0c,0x42,0x18,0xd5] // CHECK: msr {{nzcv|NZCV}}, x12 // encoding: [0x0c,0x42,0x1b,0xd5] // CHECK: msr {{daif|DAIF}}, x12 // encoding: [0x2c,0x42,0x1b,0xd5] -// CHECK: msr {{currentel|CURRENTEL}}, x12 // encoding: [0x4c,0x42,0x18,0xd5] -// CHECK: msr {{spsr_irq|SPSR_IRQ}}, x12 // encoding: [0x0c,0x43,0x1c,0xd5] -// CHECK: msr {{spsr_abt|SPSR_ABT}}, x12 // encoding: [0x2c,0x43,0x1c,0xd5] -// CHECK: msr {{spsr_und|SPSR_UND}}, x12 // encoding: [0x4c,0x43,0x1c,0xd5] -// CHECK: msr {{spsr_fiq|SPSR_FIQ}}, x12 // encoding: [0x6c,0x43,0x1c,0xd5] +// CHECK: msr {{CurrentEL|CURRENTEL}}, x12 // encoding: [0x4c,0x42,0x18,0xd5] +// CHECK: msr {{SPSR_irq|SPSR_IRQ}}, x12 // encoding: [0x0c,0x43,0x1c,0xd5] +// CHECK: msr {{SPSR_abt|SPSR_ABT}}, x12 // encoding: [0x2c,0x43,0x1c,0xd5] +// CHECK: msr {{SPSR_und|SPSR_UND}}, x12 // encoding: [0x4c,0x43,0x1c,0xd5] +// CHECK: msr {{SPSR_fiq|SPSR_FIQ}}, x12 // encoding: [0x6c,0x43,0x1c,0xd5] // CHECK: msr {{fpcr|FPCR}}, x12 // encoding: [0x0c,0x44,0x1b,0xd5] // CHECK: msr {{fpsr|FPSR}}, x12 // encoding: [0x2c,0x44,0x1b,0xd5] // CHECK: msr {{dspsr_el0|DSPSR_EL0}}, x12 // encoding: [0x0c,0x45,0x1b,0xd5] @@ -4665,14 +4665,14 @@ _func: // CHECK: mrs x9, {{sp_el0|SP_EL0}} // encoding: [0x09,0x41,0x38,0xd5] // CHECK: mrs x9, {{sp_el1|SP_EL1}} // encoding: [0x09,0x41,0x3c,0xd5] // CHECK: mrs x9, {{sp_el2|SP_EL2}} // encoding: [0x09,0x41,0x3e,0xd5] -// CHECK: mrs x9, {{spsel|SPSEL}} // encoding: [0x09,0x42,0x38,0xd5] +// CHECK: mrs x9, {{SPSel|SPSEL}} // encoding: [0x09,0x42,0x38,0xd5] // CHECK: mrs x9, {{nzcv|NZCV}} // encoding: [0x09,0x42,0x3b,0xd5] // CHECK: mrs x9, {{daif|DAIF}} // encoding: [0x29,0x42,0x3b,0xd5] -// CHECK: mrs x9, {{currentel|CURRENTEL}} // encoding: [0x49,0x42,0x38,0xd5] -// CHECK: mrs x9, {{spsr_irq|SPSR_IRQ}} // encoding: [0x09,0x43,0x3c,0xd5] -// CHECK: mrs x9, {{spsr_abt|SPSR_ABT}} // encoding: [0x29,0x43,0x3c,0xd5] -// CHECK: mrs x9, {{spsr_und|SPSR_UND}} // encoding: [0x49,0x43,0x3c,0xd5] -// CHECK: mrs x9, {{spsr_fiq|SPSR_FIQ}} // encoding: [0x69,0x43,0x3c,0xd5] +// CHECK: mrs x9, {{CurrentEL|CURRENTEL}} // encoding: [0x49,0x42,0x38,0xd5] +// CHECK: mrs x9, {{SPSR_irq|SPSR_IRQ}} // encoding: [0x09,0x43,0x3c,0xd5] +// CHECK: mrs x9, {{SPSR_abt|SPSR_ABT}} // encoding: [0x29,0x43,0x3c,0xd5] +// CHECK: mrs x9, {{SPSR_und|SPSR_UND}} // encoding: [0x49,0x43,0x3c,0xd5] +// CHECK: mrs x9, {{SPSR_fiq|SPSR_FIQ}} // encoding: [0x69,0x43,0x3c,0xd5] // CHECK: mrs x9, {{fpcr|FPCR}} // encoding: [0x09,0x44,0x3b,0xd5] // CHECK: mrs x9, {{fpsr|FPSR}} // encoding: [0x29,0x44,0x3b,0xd5] // CHECK: mrs x9, {{dspsr_el0|DSPSR_EL0}} // encoding: [0x09,0x45,0x3b,0xd5] diff --git a/llvm/test/MC/Disassembler/AArch64/arm64-system.txt b/llvm/test/MC/Disassembler/AArch64/arm64-system.txt index 9027a60dd30d..e31d32329519 100644 --- a/llvm/test/MC/Disassembler/AArch64/arm64-system.txt +++ b/llvm/test/MC/Disassembler/AArch64/arm64-system.txt @@ -48,7 +48,7 @@ # CHECK: sys #2, c0, c5, #7 # CHECK: sys #7, c6, c10, #7, x7 # CHECK: sysl x20, #6, c3, c15, #7 -# CHECK: msr SPSEL, #0 +# CHECK: msr SPSel, #0 # CHECK: msr S3_0_C11_C0_0, x0 # CHECK: mrs x0, S3_0_C11_C0_0 diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt index 9d6723a96e4d..4d438e032e77 100644 --- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -3131,9 +3131,9 @@ 0xdf 0x3f 0x3 0xd5 0xdf 0x3c 0x3 0xd5 -# CHECK: msr {{spsel|SPSEL}}, #0 -# CHECK: msr {{daifset|DAIFSET}}, #15 -# CHECK: msr {{daifclr|DAIFCLR}}, #12 +# CHECK: msr {{SPSel|SPSEL}}, #0 +# CHECK: msr {{DAIFSet|DAIFSET}}, #15 +# CHECK: msr {{DAIFClr|DAIFCLR}}, #12 0xbf 0x40 0x0 0xd5 0xdf 0x4f 0x3 0xd5 0xff 0x4c 0x3 0xd5 @@ -3289,14 +3289,14 @@ # CHECK: msr {{sp_el0|SP_EL0}}, x12 # CHECK: msr {{sp_el1|SP_EL1}}, x12 # CHECK: msr {{sp_el2|SP_EL2}}, x12 -# CHECK: msr {{spsel|SPSEL}}, x12 +# CHECK: msr {{SPSel|SPSEL}}, x12 # CHECK: msr {{nzcv|NZCV}}, x12 # CHECK: msr {{daif|DAIF}}, x12 -# CHECK: msr {{currentel|CURRENTEL}}, x12 -# CHECK: msr {{spsr_irq|SPSR_IRQ}}, x12 -# CHECK: msr {{spsr_abt|SPSR_ABT}}, x12 -# CHECK: msr {{spsr_und|SPSR_UND}}, x12 -# CHECK: msr {{spsr_fiq|SPSR_FIQ}}, x12 +# CHECK: msr {{CurrentEL|CURRENTEL}}, x12 +# CHECK: msr {{SPSR_irq|SPSR_IRQ}}, x12 +# CHECK: msr {{SPSR_abt|SPSR_ABT}}, x12 +# CHECK: msr {{SPSR_und|SPSR_UND}}, x12 +# CHECK: msr {{SPSR_fiq|SPSR_FIQ}}, x12 # CHECK: msr {{fpcr|FPCR}}, x12 # CHECK: msr {{fpsr|FPSR}}, x12 # CHECK: msr {{dspsr_el0|DSPSR_EL0}}, x12 @@ -3581,14 +3581,14 @@ # CHECK: mrs x9, {{sp_el0|SP_EL0}} # CHECK: mrs x9, {{sp_el1|SP_EL1}} # CHECK: mrs x9, {{sp_el2|SP_EL2}} -# CHECK: mrs x9, {{spsel|SPSEL}} +# CHECK: mrs x9, {{SPSel|SPSEL}} # CHECK: mrs x9, {{nzcv|NZCV}} # CHECK: mrs x9, {{daif|DAIF}} -# CHECK: mrs x9, {{currentel|CURRENTEL}} -# CHECK: mrs x9, {{spsr_irq|SPSR_IRQ}} -# CHECK: mrs x9, {{spsr_abt|SPSR_ABT}} -# CHECK: mrs x9, {{spsr_und|SPSR_UND}} -# CHECK: mrs x9, {{spsr_fiq|SPSR_FIQ}} +# CHECK: mrs x9, {{CurrentEL|CURRENTEL}} +# CHECK: mrs x9, {{SPSR_irq|SPSR_IRQ}} +# CHECK: mrs x9, {{SPSR_abt|SPSR_ABT}} +# CHECK: mrs x9, {{SPSR_und|SPSR_UND}} +# CHECK: mrs x9, {{SPSR_fiq|SPSR_FIQ}} # CHECK: mrs x9, {{fpcr|FPCR}} # CHECK: mrs x9, {{fpsr|FPSR}} # CHECK: mrs x9, {{dspsr_el0|DSPSR_EL0}} diff --git a/llvm/utils/TableGen/CMakeLists.txt b/llvm/utils/TableGen/CMakeLists.txt index eef1540424dd..e8fe30f5ac70 100644 --- a/llvm/utils/TableGen/CMakeLists.txt +++ b/llvm/utils/TableGen/CMakeLists.txt @@ -27,6 +27,7 @@ add_tablegen(llvm-tblgen LLVM OptParserEmitter.cpp PseudoLoweringEmitter.cpp RegisterInfoEmitter.cpp + SearchableTableEmitter.cpp SubtargetEmitter.cpp TableGen.cpp X86DisassemblerTables.cpp diff --git a/llvm/utils/TableGen/SearchableTableEmitter.cpp b/llvm/utils/TableGen/SearchableTableEmitter.cpp new file mode 100644 index 000000000000..1b0e67f835fe --- /dev/null +++ b/llvm/utils/TableGen/SearchableTableEmitter.cpp @@ -0,0 +1,320 @@ +//===- SearchableTableEmitter.cpp - Generate efficiently searchable tables -==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This tablegen backend emits a generic array initialized by specified fields, +// together with companion index tables and lookup functions (binary search, +// currently). +// +//===----------------------------------------------------------------------===// + +#include "llvm/ADT/StringExtras.h" +#include "llvm/Support/Format.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/SourceMgr.h" +#include "llvm/TableGen/Error.h" +#include "llvm/TableGen/Record.h" +#include +#include +#include +#include +using namespace llvm; + +#define DEBUG_TYPE "searchable-table-emitter" + +namespace { + +class SearchableTableEmitter { + RecordKeeper &Records; + +public: + SearchableTableEmitter(RecordKeeper &R) : Records(R) {} + + void run(raw_ostream &OS); + +private: + typedef std::pair SearchTableEntry; + + int getAsInt(BitsInit *B) { + return cast(B->convertInitializerTo(IntRecTy::get()))->getValue(); + } + int getInt(Record *R, StringRef Field) { + return getAsInt(R->getValueAsBitsInit(Field)); + } + + std::string primaryRepresentation(Init *I) { + if (StringInit *SI = dyn_cast(I)) + return SI->getAsString(); + else if (BitsInit *BI = dyn_cast(I)) + return "0x" + utohexstr(getAsInt(BI)); + else if (BitInit *BI = dyn_cast(I)) + return BI->getValue() ? "true" : "false"; + else if (CodeInit *CI = dyn_cast(I)) { + return CI->getValue(); + } + PrintFatalError(SMLoc(), + "invalid field type, expected: string, bits, bit or code"); + } + + std::string searchRepresentation(Init *I) { + std::string PrimaryRep = primaryRepresentation(I); + if (!isa(I)) + return PrimaryRep; + return StringRef(PrimaryRep).upper(); + } + + std::string searchableFieldType(Init *I) { + if (isa(I)) + return "const char *"; + else if (BitsInit *BI = dyn_cast(I)) { + unsigned NumBits = BI->getNumBits(); + if (NumBits <= 8) + NumBits = 8; + else if (NumBits <= 16) + NumBits = 16; + else if (NumBits <= 32) + NumBits = 32; + else if (NumBits <= 64) + NumBits = 64; + else + PrintFatalError(SMLoc(), "bitfield too large to search"); + return "uint" + utostr(NumBits) + "_t"; + } + PrintFatalError(SMLoc(), "Unknown type to search by"); + } + + void emitMapping(Record *MappingDesc, raw_ostream &OS); + void emitMappingEnum(std::vector &Items, Record *InstanceClass, + raw_ostream &OS); + void + emitPrimaryTable(StringRef Name, std::vector &FieldNames, + std::vector &SearchFieldNames, + std::vector> &SearchTables, + std::vector &Items, raw_ostream &OS); + void emitSearchTable(StringRef Name, StringRef Field, + std::vector &SearchTable, + raw_ostream &OS); + void emitLookupDeclaration(StringRef Name, StringRef Field, Init *I, + raw_ostream &OS); + void emitLookupFunction(StringRef Name, StringRef Field, Init *I, + raw_ostream &OS); +}; + +} // End anonymous namespace. + +/// Emit an enum providing symbolic access to some preferred field from +/// C++. +void SearchableTableEmitter::emitMappingEnum(std::vector &Items, + Record *InstanceClass, + raw_ostream &OS) { + std::string EnumNameField = InstanceClass->getValueAsString("EnumNameField"); + std::string EnumValueField; + if (!InstanceClass->isValueUnset("EnumValueField")) + EnumValueField = InstanceClass->getValueAsString("EnumValueField"); + + OS << "enum " << InstanceClass->getName() << "Values {\n"; + for (auto Item : Items) { + OS << " " << Item->getValueAsString(EnumNameField); + if (EnumValueField != StringRef()) + OS << " = " << getInt(Item, EnumValueField); + OS << ",\n"; + } + OS << "};\n\n"; +} + +void SearchableTableEmitter::emitPrimaryTable( + StringRef Name, std::vector &FieldNames, + std::vector &SearchFieldNames, + std::vector> &SearchTables, + std::vector &Items, raw_ostream &OS) { + OS << "const " << Name << " " << Name << "sList[] = {\n"; + + for (auto Item : Items) { + OS << " { "; + for (unsigned i = 0; i < FieldNames.size(); ++i) { + OS << primaryRepresentation(Item->getValueInit(FieldNames[i])); + if (i != FieldNames.size() - 1) + OS << ", "; + } + OS << "},\n"; + } + OS << "};\n\n"; +} + +void SearchableTableEmitter::emitSearchTable( + StringRef Name, StringRef Field, std::vector &SearchTable, + raw_ostream &OS) { + OS << "const std::pair<" << searchableFieldType(SearchTable[0].first) + << ", int> " << Name << "sBy" << Field << "[] = {\n"; + + if (isa(SearchTable[0].first)) { + std::stable_sort(SearchTable.begin(), SearchTable.end(), + [this](const SearchTableEntry &LHS, + const SearchTableEntry &RHS) { + return getAsInt(cast(LHS.first)) < + getAsInt(cast(RHS.first)); + }); + } else { + std::stable_sort(SearchTable.begin(), SearchTable.end(), + [this](const SearchTableEntry &LHS, + const SearchTableEntry &RHS) { + return searchRepresentation(LHS.first) < + searchRepresentation(RHS.first); + }); + } + + for (auto Entry : SearchTable) { + OS << " { " << searchRepresentation(Entry.first) << ", " << Entry.second + << " },\n"; + } + OS << "};\n\n"; +} + +void SearchableTableEmitter::emitLookupFunction(StringRef Name, StringRef Field, + Init *I, raw_ostream &OS) { + bool IsIntegral = isa(I); + std::string FieldType = searchableFieldType(I); + std::string PairType = "std::pair<" + FieldType + ", int>"; + + // const SysRegs *lookupSysRegByName(const char *Name) { + OS << "const " << Name << " *" + << "lookup" << Name << "By" << Field; + OS << "(" << (IsIntegral ? FieldType : "StringRef") << " " << Field + << ") {\n"; + + if (IsIntegral) { + OS << " auto CanonicalVal = " << Field << ";\n"; + OS << " " << PairType << " Val = {CanonicalVal, 0};\n"; + } else { + // Make sure the result is null terminated because it's going via "char *". + OS << " std::string CanonicalVal = " << Field << ".upper();\n"; + OS << " " << PairType << " Val = {CanonicalVal.data(), 0};\n"; + } + + OS << " ArrayRef<" << PairType << "> Table(" << Name << "sBy" << Field + << ");\n"; + OS << " auto Idx = std::lower_bound(Table.begin(), Table.end(), Val"; + + if (IsIntegral) + OS << ");\n"; + else { + OS << ",\n "; + OS << "[](const " << PairType << " &LHS, const " << PairType + << " &RHS) {\n"; + OS << " return StringRef(LHS.first) < StringRef(RHS.first);\n"; + OS << " });\n\n"; + } + + OS << " if (Idx == Table.end() || CanonicalVal != Idx->first)\n"; + OS << " return nullptr;\n"; + + OS << " return &" << Name << "sList[Idx->second];\n"; + OS << "}\n\n"; +} + +void SearchableTableEmitter::emitLookupDeclaration(StringRef Name, + StringRef Field, Init *I, + raw_ostream &OS) { + bool IsIntegral = isa(I); + std::string FieldType = searchableFieldType(I); + OS << "const " << Name << " *" + << "lookup" << Name << "By" << Field; + OS << "(" << (IsIntegral ? FieldType : "StringRef") << " " << Field + << ");\n\n"; +} + +void SearchableTableEmitter::emitMapping(Record *InstanceClass, + raw_ostream &OS) { + std::string TableName = InstanceClass->getName(); + std::vector Items = Records.getAllDerivedDefinitions(TableName); + + // Gather all the records we're going to need for this particular mapping. + std::vector> SearchTables; + std::vector SearchFieldNames; + + std::vector FieldNames; + for (const RecordVal &Field : InstanceClass->getValues()) { + std::string FieldName = Field.getName(); + + // Skip uninteresting fields: either built-in, special to us, or injected + // template parameters (if they contain a ':'). + if (FieldName.find(':') != std::string::npos || FieldName == "NAME" || + FieldName == "SearchableFields" || FieldName == "EnumNameField" || + FieldName == "EnumValueField") + continue; + + FieldNames.push_back(FieldName); + } + + for (auto *Field : *InstanceClass->getValueAsListInit("SearchableFields")) { + SearchTables.emplace_back(); + SearchFieldNames.push_back(Field->getAsUnquotedString()); + } + + int Idx = 0; + for (Record *Item : Items) { + for (unsigned i = 0; i < SearchFieldNames.size(); ++i) { + Init *SearchVal = Item->getValueInit(SearchFieldNames[i]); + SearchTables[i].emplace_back(SearchVal, Idx); + } + ++Idx; + } + + OS << "#ifdef GET_" << StringRef(TableName).upper() << "_DECL\n"; + OS << "#undef GET_" << StringRef(TableName).upper() << "_DECL\n"; + + // Next emit the enum containing the top-level names for use in C++ code if + // requested + if (!InstanceClass->isValueUnset("EnumNameField")) { + emitMappingEnum(Items, InstanceClass, OS); + } + + // And the declarations for the functions that will perform lookup. + for (unsigned i = 0; i < SearchFieldNames.size(); ++i) + emitLookupDeclaration(TableName, SearchFieldNames[i], + SearchTables[i][0].first, OS); + + OS << "#endif\n\n"; + + OS << "#ifdef GET_" << StringRef(TableName).upper() << "_IMPL\n"; + OS << "#undef GET_" << StringRef(TableName).upper() << "_IMPL\n"; + + // The primary data table contains all the fields defined for this map. + emitPrimaryTable(TableName, FieldNames, SearchFieldNames, SearchTables, Items, + OS); + + // Indexes are sorted "{ Thing, PrimaryIdx }" arrays, so that a binary + // search can be performed by "Thing". + for (unsigned i = 0; i < SearchTables.size(); ++i) { + emitSearchTable(TableName, SearchFieldNames[i], SearchTables[i], OS); + emitLookupFunction(TableName, SearchFieldNames[i], SearchTables[i][0].first, + OS); + } + + OS << "#endif\n"; +} + +void SearchableTableEmitter::run(raw_ostream &OS) { + // Tables are defined to be the direct descendents of "SearchableEntry". + Record *SearchableTable = Records.getClass("SearchableTable"); + for (auto &NameRec : Records.getClasses()) { + Record *Class = NameRec.second.get(); + if (Class->getSuperClasses().size() != 1 || + !Class->isSubClassOf(SearchableTable)) + continue; + emitMapping(Class, OS); + } +} + +namespace llvm { + +void EmitSearchableTables(RecordKeeper &RK, raw_ostream &OS) { + SearchableTableEmitter(RK).run(OS); +} + +} // End llvm namespace. diff --git a/llvm/utils/TableGen/TableGen.cpp b/llvm/utils/TableGen/TableGen.cpp index cf751235535d..24dbe5d3a280 100644 --- a/llvm/utils/TableGen/TableGen.cpp +++ b/llvm/utils/TableGen/TableGen.cpp @@ -43,7 +43,8 @@ enum ActionType { PrintSets, GenOptParserDefs, GenCTags, - GenAttributes + GenAttributes, + GenSearchableTables, }; namespace { @@ -89,6 +90,8 @@ namespace { "Generate ctags-compatible index"), clEnumValN(GenAttributes, "gen-attrs", "Generate attributes"), + clEnumValN(GenSearchableTables, "gen-searchable-tables", + "Generate generic binary-searchable table"), clEnumValEnd)); cl::opt @@ -172,6 +175,9 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { case GenAttributes: EmitAttributes(Records, OS); break; + case GenSearchableTables: + EmitSearchableTables(Records, OS); + break; } return false; diff --git a/llvm/utils/TableGen/TableGenBackends.h b/llvm/utils/TableGen/TableGenBackends.h index d9dd3d157697..51e017fe6594 100644 --- a/llvm/utils/TableGen/TableGenBackends.h +++ b/llvm/utils/TableGen/TableGenBackends.h @@ -79,6 +79,7 @@ void EmitMapTable(RecordKeeper &RK, raw_ostream &OS); void EmitOptParser(RecordKeeper &RK, raw_ostream &OS); void EmitCTags(RecordKeeper &RK, raw_ostream &OS); void EmitAttributes(RecordKeeper &RK, raw_ostream &OS); +void EmitSearchableTables(RecordKeeper &RK, raw_ostream &OS); } // End llvm namespace