maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Add float/vector registers for ppc64le 

Summary: Add read and write functions for VSX, VMX and float registers and fix watchpoint size

Reviewers: clayborg

Reviewed By: clayborg

Subscribers: eugene, labath, clayborg, nemanjai, kbarton, JDevlieghere, anajuliapc, gut, lbianc, lldb-commits

Differential Revision: https://reviews.llvm.org/D39487
Patch by: Alexandre Yukio Yamashita <alexandre.yamashita@eldorado.org.br>

llvm-svn: 317329
This commit is contained in:
Pavel Labath 2017-11-03 15:22:36 +00:00
parent 6e6228477b
commit e6a661053d
8 changed files with 1103 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lldb/packages/Python/lldbsuite/test/make/Makefile.rules
View File

@ -181,6 +181,9 @@ else
ifeq "$(ARCH)" "powerpc64"
override ARCH := $(subst powerpc64,64,$(ARCH))
endif
ifeq "$(ARCH)" "powerpc64le"
override ARCH := $(subst powerpc64le,64,$(ARCH))
endif
ifeq "$(ARCH)" "aarch64"
override ARCH :=
override ARCHFLAG :=

2
lldb/source/Core/ArchSpec.cpp
View File

@ -368,6 +368,8 @@ static const ArchDefinitionEntry g_macho_arch_entries[] = {
SUBTYPE_MASK},
{ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0,
UINT32_MAX, SUBTYPE_MASK},
{ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY,
UINT32_MAX, SUBTYPE_MASK},
{ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100,
UINT32_MAX, SUBTYPE_MASK},
{ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX,

336
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.cpp
View File

@ -32,8 +32,8 @@
#include <elf.h>
#include <asm/ptrace.h>
#define REG_CONTEXT_SIZE GetGPRSize()
#define REG_CONTEXT_SIZE \
(GetGPRSize() + GetFPRSize() + sizeof(m_vmx_ppc64le) + sizeof(m_vsx_ppc64le))
using namespace lldb;
using namespace lldb_private;
using namespace lldb_private::process_linux;
@ -52,14 +52,63 @@ static const uint32_t g_gpr_regnums_ppc64le[] = {
gpr_trap_ppc64le,
};
static const uint32_t g_fpr_regnums_ppc64le[] = {
fpr_f0_ppc64le, fpr_f1_ppc64le, fpr_f2_ppc64le, fpr_f3_ppc64le,
fpr_f4_ppc64le, fpr_f5_ppc64le, fpr_f6_ppc64le, fpr_f7_ppc64le,
fpr_f8_ppc64le, fpr_f9_ppc64le, fpr_f10_ppc64le, fpr_f11_ppc64le,
fpr_f12_ppc64le, fpr_f13_ppc64le, fpr_f14_ppc64le, fpr_f15_ppc64le,
fpr_f16_ppc64le, fpr_f17_ppc64le, fpr_f18_ppc64le, fpr_f19_ppc64le,
fpr_f20_ppc64le, fpr_f21_ppc64le, fpr_f22_ppc64le, fpr_f23_ppc64le,
fpr_f24_ppc64le, fpr_f25_ppc64le, fpr_f26_ppc64le, fpr_f27_ppc64le,
fpr_f28_ppc64le, fpr_f29_ppc64le, fpr_f30_ppc64le, fpr_f31_ppc64le,
fpr_fpscr_ppc64le,
};
static const uint32_t g_vmx_regnums_ppc64le[] = {
vmx_vr0_ppc64le, vmx_vr1_ppc64le, vmx_vr2_ppc64le, vmx_vr3_ppc64le,
vmx_vr4_ppc64le, vmx_vr5_ppc64le, vmx_vr6_ppc64le, vmx_vr7_ppc64le,
vmx_vr8_ppc64le, vmx_vr9_ppc64le, vmx_vr10_ppc64le, vmx_vr11_ppc64le,
vmx_vr12_ppc64le, vmx_vr13_ppc64le, vmx_vr14_ppc64le, vmx_vr15_ppc64le,
vmx_vr16_ppc64le, vmx_vr17_ppc64le, vmx_vr18_ppc64le, vmx_vr19_ppc64le,
vmx_vr20_ppc64le, vmx_vr21_ppc64le, vmx_vr22_ppc64le, vmx_vr23_ppc64le,
vmx_vr24_ppc64le, vmx_vr25_ppc64le, vmx_vr26_ppc64le, vmx_vr27_ppc64le,
vmx_vr28_ppc64le, vmx_vr29_ppc64le, vmx_vr30_ppc64le, vmx_vr31_ppc64le,
vmx_vscr_ppc64le, vmx_vrsave_ppc64le,
};
static const uint32_t g_vsx_regnums_ppc64le[] = {
vsx_vs0_ppc64le, vsx_vs1_ppc64le, vsx_vs2_ppc64le, vsx_vs3_ppc64le,
vsx_vs4_ppc64le, vsx_vs5_ppc64le, vsx_vs6_ppc64le, vsx_vs7_ppc64le,
vsx_vs8_ppc64le, vsx_vs9_ppc64le, vsx_vs10_ppc64le, vsx_vs11_ppc64le,
vsx_vs12_ppc64le, vsx_vs13_ppc64le, vsx_vs14_ppc64le, vsx_vs15_ppc64le,
vsx_vs16_ppc64le, vsx_vs17_ppc64le, vsx_vs18_ppc64le, vsx_vs19_ppc64le,
vsx_vs20_ppc64le, vsx_vs21_ppc64le, vsx_vs22_ppc64le, vsx_vs23_ppc64le,
vsx_vs24_ppc64le, vsx_vs25_ppc64le, vsx_vs26_ppc64le, vsx_vs27_ppc64le,
vsx_vs28_ppc64le, vsx_vs29_ppc64le, vsx_vs30_ppc64le, vsx_vs31_ppc64le,
vsx_vs32_ppc64le, vsx_vs33_ppc64le, vsx_vs34_ppc64le, vsx_vs35_ppc64le,
vsx_vs36_ppc64le, vsx_vs37_ppc64le, vsx_vs38_ppc64le, vsx_vs39_ppc64le,
vsx_vs40_ppc64le, vsx_vs41_ppc64le, vsx_vs42_ppc64le, vsx_vs43_ppc64le,
vsx_vs44_ppc64le, vsx_vs45_ppc64le, vsx_vs46_ppc64le, vsx_vs47_ppc64le,
vsx_vs48_ppc64le, vsx_vs49_ppc64le, vsx_vs50_ppc64le, vsx_vs51_ppc64le,
vsx_vs52_ppc64le, vsx_vs53_ppc64le, vsx_vs54_ppc64le, vsx_vs55_ppc64le,
vsx_vs56_ppc64le, vsx_vs57_ppc64le, vsx_vs58_ppc64le, vsx_vs59_ppc64le,
vsx_vs60_ppc64le, vsx_vs61_ppc64le, vsx_vs62_ppc64le, vsx_vs63_ppc64le,
};
namespace {
// Number of register sets provided by this context.
enum { k_num_register_sets = 1 };
enum { k_num_register_sets = 4 };
}
static const RegisterSet g_reg_sets_ppc64le[k_num_register_sets] = {
{"General Purpose Registers", "gpr", k_num_gpr_registers_ppc64le,
g_gpr_regnums_ppc64le},
{"Floating Point Registers", "fpr", k_num_fpr_registers_ppc64le,
g_fpr_regnums_ppc64le},
{"AltiVec/VMX Registers", "vmx", k_num_vmx_registers_ppc64le,
g_vmx_regnums_ppc64le},
{"VSX Registers", "vsx", k_num_vsx_registers_ppc64le,
g_vsx_regnums_ppc64le},
};
NativeRegisterContextLinux *
@ -85,6 +134,9 @@ NativeRegisterContextLinux_ppc64le::NativeRegisterContextLinux_ppc64le(
}
::memset(&m_gpr_ppc64le, 0, sizeof(m_gpr_ppc64le));
::memset(&m_fpr_ppc64le, 0, sizeof(m_fpr_ppc64le));
::memset(&m_vmx_ppc64le, 0, sizeof(m_vmx_ppc64le));
::memset(&m_vsx_ppc64le, 0, sizeof(m_vsx_ppc64le));
::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs));
}
@ -118,7 +170,63 @@ Status NativeRegisterContextLinux_ppc64le::ReadRegister(
const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
if (IsGPR(reg)) {
if (IsFPR(reg)) {
error = ReadFPR();
if (error.Fail())
return error;
// Get pointer to m_fpr_ppc64le variable and set the data from it.
uint32_t fpr_offset = CalculateFprOffset(reg_info);
assert(fpr_offset < sizeof m_fpr_ppc64le);
uint8_t *src = (uint8_t *)&m_fpr_ppc64le + fpr_offset;
reg_value.SetFromMemoryData(reg_info, src, reg_info->byte_size,
eByteOrderLittle, error);
} else if (IsVSX(reg)) {
uint32_t vsx_offset = CalculateVsxOffset(reg_info);
assert(vsx_offset < sizeof(m_vsx_ppc64le));
if (vsx_offset < sizeof(m_vsx_ppc64le) / 2) {
error = ReadVSX();
if (error.Fail())
return error;
error = ReadFPR();
if (error.Fail())
return error;
uint64_t value[2];
uint8_t *dst, *src;
dst = (uint8_t *)&value;
src = (uint8_t *)&m_vsx_ppc64le + vsx_offset / 2;
::memcpy(dst, src, 8);
dst += 8;
src = (uint8_t *)&m_fpr_ppc64le + vsx_offset / 2;
::memcpy(dst, src, 8);
reg_value.SetFromMemoryData(reg_info, &value, reg_info->byte_size,
eByteOrderLittle, error);
} else {
error = ReadVMX();
if (error.Fail())
return error;
// Get pointer to m_vmx_ppc64le variable and set the data from it.
uint32_t vmx_offset = vsx_offset - sizeof(m_vsx_ppc64le) / 2;
uint8_t *src = (uint8_t *)&m_vmx_ppc64le + vmx_offset;
reg_value.SetFromMemoryData(reg_info, src, reg_info->byte_size,
eByteOrderLittle, error);
}
} else if (IsVMX(reg)) {
error = ReadVMX();
if (error.Fail())
return error;
// Get pointer to m_vmx_ppc64le variable and set the data from it.
uint32_t vmx_offset = CalculateVmxOffset(reg_info);
assert(vmx_offset < sizeof m_vmx_ppc64le);
uint8_t *src = (uint8_t *)&m_vmx_ppc64le + vmx_offset;
reg_value.SetFromMemoryData(reg_info, src, reg_info->byte_size,
eByteOrderLittle, error);
} else if (IsGPR(reg)) {
error = ReadGPR();
if (error.Fail())
return error;
@ -127,8 +235,8 @@ Status NativeRegisterContextLinux_ppc64le::ReadRegister(
reg_value.SetFromMemoryData(reg_info, src, reg_info->byte_size,
eByteOrderLittle, error);
} else {
return Status("failed - register wasn't recognized to be a GPR, "
"read strategy unknown");
return Status("failed - register wasn't recognized to be a GPR, FPR, VSX "
"or VMX, read strategy unknown");
}
return error;
@ -147,22 +255,98 @@ Status NativeRegisterContextLinux_ppc64le::WriteRegister(
: "<unknown register>");
if (IsGPR(reg_index)) {
error = ReadGPR();
if (error.Fail())
return error;
error = ReadGPR();
if (error.Fail())
return error;
uint8_t *dst = (uint8_t *) &m_gpr_ppc64le + reg_info->byte_offset;
::memcpy(dst, reg_value.GetBytes(), reg_value.GetByteSize());
uint8_t *dst = (uint8_t *)&m_gpr_ppc64le + reg_info->byte_offset;
::memcpy(dst, reg_value.GetBytes(), reg_value.GetByteSize());
error = WriteGPR();
if (error.Fail())
return error;
error = WriteGPR();
if (error.Fail())
return error;
return Status();
return Status();
}
return Status("failed - register wasn't recognized to be a GPR, "
"write strategy unknown");
if (IsFPR(reg_index)) {
error = ReadFPR();
if (error.Fail())
return error;
// Get pointer to m_fpr_ppc64le variable and set the data to it.
uint32_t fpr_offset = CalculateFprOffset(reg_info);
assert(fpr_offset < GetFPRSize());
uint8_t *dst = (uint8_t *)&m_fpr_ppc64le + fpr_offset;
::memcpy(dst, reg_value.GetBytes(), reg_value.GetByteSize());
error = WriteFPR();
if (error.Fail())
return error;
return Status();
}
if (IsVMX(reg_index)) {
error = ReadVMX();
if (error.Fail())
return error;
// Get pointer to m_vmx_ppc64le variable and set the data to it.
uint32_t vmx_offset = CalculateVmxOffset(reg_info);
assert(vmx_offset < sizeof(m_vmx_ppc64le));
uint8_t *dst = (uint8_t *)&m_vmx_ppc64le + vmx_offset;
::memcpy(dst, reg_value.GetBytes(), reg_value.GetByteSize());
error = WriteVMX();
if (error.Fail())
return error;
return Status();
}
if (IsVSX(reg_index)) {
uint32_t vsx_offset = CalculateVsxOffset(reg_info);
assert(vsx_offset < sizeof(m_vsx_ppc64le));
if (vsx_offset < sizeof(m_vsx_ppc64le) / 2) {
error = ReadVSX();
if (error.Fail())
return error;
error = ReadFPR();
if (error.Fail())
return error;
uint64_t value[2];
::memcpy(value, reg_value.GetBytes(), 16);
uint8_t *dst, *src;
src = (uint8_t *)value;
dst = (uint8_t *)&m_vsx_ppc64le + vsx_offset / 2;
::memcpy(dst, src, 8);
src += 8;
dst = (uint8_t *)&m_fpr_ppc64le + vsx_offset / 2;
::memcpy(dst, src, 8);
WriteVSX();
WriteFPR();
} else {
error = ReadVMX();
if (error.Fail())
return error;
// Get pointer to m_vmx_ppc64le variable and set the data from it.
uint32_t vmx_offset = vsx_offset - sizeof(m_vsx_ppc64le) / 2;
uint8_t *dst = (uint8_t *)&m_vmx_ppc64le + vmx_offset;
::memcpy(dst, reg_value.GetBytes(), reg_value.GetByteSize());
WriteVMX();
}
return Status();
}
return Status("failed - register wasn't recognized to be a GPR, FPR, VSX "
"or VMX, write strategy unknown");
}
Status NativeRegisterContextLinux_ppc64le::ReadAllRegisterValues(
@ -178,6 +362,18 @@ Status NativeRegisterContextLinux_ppc64le::ReadAllRegisterValues(
if (error.Fail())
return error;
error = ReadFPR();
if (error.Fail())
return error;
error = ReadVMX();
if (error.Fail())
return error;
error = ReadVSX();
if (error.Fail())
return error;
uint8_t *dst = data_sp->GetBytes();
if (dst == nullptr) {
error.SetErrorStringWithFormat("DataBufferHeap instance of size %" PRIu64
@ -187,6 +383,12 @@ Status NativeRegisterContextLinux_ppc64le::ReadAllRegisterValues(
}
::memcpy(dst, &m_gpr_ppc64le, GetGPRSize());
dst += GetGPRSize();
::memcpy(dst, &m_fpr_ppc64le, GetFPRSize());
dst += GetFPRSize();
::memcpy(dst, &m_vmx_ppc64le, sizeof(m_vmx_ppc64le));
dst += sizeof(m_vmx_ppc64le);
::memcpy(dst, &m_vsx_ppc64le, sizeof(m_vsx_ppc64le));
return error;
}
@ -222,6 +424,27 @@ Status NativeRegisterContextLinux_ppc64le::WriteAllRegisterValues(
::memcpy(&m_gpr_ppc64le, src, GetGPRSize());
error = WriteGPR();
if (error.Fail())
return error;
src += GetGPRSize();
::memcpy(&m_fpr_ppc64le, src, GetFPRSize());
error = WriteFPR();
if (error.Fail())
return error;
src += GetFPRSize();
::memcpy(&m_vmx_ppc64le, src, sizeof(m_vmx_ppc64le));
error = WriteVMX();
if (error.Fail())
return error;
src += sizeof(m_vmx_ppc64le);
::memcpy(&m_vsx_ppc64le, src, sizeof(m_vsx_ppc64le));
error = WriteVSX();
return error;
}
@ -229,6 +452,10 @@ bool NativeRegisterContextLinux_ppc64le::IsGPR(unsigned reg) const {
return reg <= k_last_gpr_ppc64le; // GPR's come first.
}
bool NativeRegisterContextLinux_ppc64le::IsFPR(unsigned reg) const {
return (k_first_fpr_ppc64le <= reg && reg <= k_last_fpr_ppc64le);
}
Status NativeRegisterContextLinux_ppc64le::DoReadGPR(
void *buf, size_t buf_size) {
int regset = NT_PRSTATUS;
@ -243,6 +470,74 @@ Status NativeRegisterContextLinux_ppc64le::DoWriteGPR(
&regset, buf, buf_size);
}
Status NativeRegisterContextLinux_ppc64le::DoReadFPR(void *buf,
size_t buf_size) {
int regset = NT_FPREGSET;
return NativeProcessLinux::PtraceWrapper(PTRACE_GETFPREGS, m_thread.GetID(),
&regset, buf, buf_size);
}
Status NativeRegisterContextLinux_ppc64le::DoWriteFPR(void *buf,
size_t buf_size) {
int regset = NT_FPREGSET;
return NativeProcessLinux::PtraceWrapper(PTRACE_SETFPREGS, m_thread.GetID(),
&regset, buf, buf_size);
}
uint32_t NativeRegisterContextLinux_ppc64le::CalculateFprOffset(
const RegisterInfo *reg_info) const {
return reg_info->byte_offset -
GetRegisterInfoAtIndex(k_first_fpr_ppc64le)->byte_offset;
}
uint32_t NativeRegisterContextLinux_ppc64le::CalculateVmxOffset(
const RegisterInfo *reg_info) const {
return reg_info->byte_offset -
GetRegisterInfoAtIndex(k_first_vmx_ppc64le)->byte_offset;
}
uint32_t NativeRegisterContextLinux_ppc64le::CalculateVsxOffset(
const RegisterInfo *reg_info) const {
return reg_info->byte_offset -
GetRegisterInfoAtIndex(k_first_vsx_ppc64le)->byte_offset;
}
Status NativeRegisterContextLinux_ppc64le::ReadVMX() {
int regset = NT_PPC_VMX;
return NativeProcessLinux::PtraceWrapper(PTRACE_GETVRREGS, m_thread.GetID(),
&regset, &m_vmx_ppc64le,
sizeof(m_vmx_ppc64le));
}
Status NativeRegisterContextLinux_ppc64le::WriteVMX() {
int regset = NT_PPC_VMX;
return NativeProcessLinux::PtraceWrapper(PTRACE_SETVRREGS, m_thread.GetID(),
&regset, &m_vmx_ppc64le,
sizeof(m_vmx_ppc64le));
}
Status NativeRegisterContextLinux_ppc64le::ReadVSX() {
int regset = NT_PPC_VSX;
return NativeProcessLinux::PtraceWrapper(PTRACE_GETVSRREGS, m_thread.GetID(),
&regset, &m_vsx_ppc64le,
sizeof(m_vsx_ppc64le));
}
Status NativeRegisterContextLinux_ppc64le::WriteVSX() {
int regset = NT_PPC_VSX;
return NativeProcessLinux::PtraceWrapper(PTRACE_SETVSRREGS, m_thread.GetID(),
&regset, &m_vsx_ppc64le,
sizeof(m_vsx_ppc64le));
}
bool NativeRegisterContextLinux_ppc64le::IsVMX(unsigned reg) {
return (reg >= k_first_vmx_ppc64le) && (reg <= k_last_vmx_ppc64le);
}
bool NativeRegisterContextLinux_ppc64le::IsVSX(unsigned reg) {
return (reg >= k_first_vsx_ppc64le) && (reg <= k_last_vsx_ppc64le);
}
uint32_t NativeRegisterContextLinux_ppc64le::NumSupportedHardwareWatchpoints() {
Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS));
@ -389,8 +684,11 @@ NativeRegisterContextLinux_ppc64le::GetWatchpointSize(uint32_t wp_index) {
LLDB_LOG(log, "wp_index: {0}", wp_index);
unsigned control = (m_hwp_regs[wp_index].control >> 5) & 0xff;
assert(llvm::isPowerOf2_32(control + 1));
return llvm::countPopulation(control);
if (llvm::isPowerOf2_32(control + 1)) {
return llvm::countPopulation(control);
}
return 0;
}
bool NativeRegisterContextLinux_ppc64le::WatchpointIsEnabled(

35
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.h
View File

@ -76,13 +76,48 @@ protected:
Status DoWriteGPR(void *buf, size_t buf_size) override;
Status DoReadFPR(void *buf, size_t buf_size) override;
Status DoWriteFPR(void *buf, size_t buf_size) override;
bool IsVMX(unsigned reg);
bool IsVSX(unsigned reg);
Status ReadVMX();
Status WriteVMX();
Status ReadVSX();
Status WriteVSX();
void *GetGPRBuffer() override { return &m_gpr_ppc64le; }
void *GetFPRBuffer() override { return &m_fpr_ppc64le; }
size_t GetFPRSize() override { return sizeof(m_fpr_ppc64le); }
private:
GPR m_gpr_ppc64le; // 64-bit general purpose registers.
FPR m_fpr_ppc64le; // floating-point registers including extended register.
VMX m_vmx_ppc64le; // VMX registers.
VSX m_vsx_ppc64le; // Last lower bytes from first VSX registers.
bool IsGPR(unsigned reg) const;
bool IsFPR(unsigned reg) const;
bool IsVMX(unsigned reg) const;
bool IsVSX(unsigned reg) const;
uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const;
uint32_t CalculateVmxOffset(const RegisterInfo *reg_info) const;
uint32_t CalculateVsxOffset(const RegisterInfo *reg_info) const;
Status ReadHardwareDebugInfo();
Status WriteHardwareDebugRegs();

343
lldb/source/Plugins/Process/Utility/RegisterInfos_ppc64le.h
View File

@ -14,6 +14,10 @@
// Computes the offset of the given GPR in the user data area.
#define GPR_OFFSET(regname) (offsetof(GPR, regname))
#define FPR_OFFSET(regname) (offsetof(FPR, regname) + sizeof(GPR))
#define VMX_OFFSET(regname) (offsetof(VMX, regname) + sizeof(GPR) + sizeof(FPR))
#define VSX_OFFSET(regname) \
(offsetof(VSX, regname) + sizeof(GPR) + sizeof(FPR) + sizeof(VMX))
#define GPR_SIZE(regname) (sizeof(((GPR *)NULL)->regname))
#include "Utility/PPC64LE_DWARF_Registers.h"
@ -31,6 +35,32 @@
gpr_##reg##_ppc64le }, \
NULL, NULL, NULL, 0 \
}
#define DEFINE_FPR(reg, alt, lldb_kind) \
{ \
#reg, alt, 8, FPR_OFFSET(reg), lldb::eEncodingIEEE754, lldb::eFormatFloat, \
{ppc64le_dwarf::dwarf_##reg##_ppc64le, \
ppc64le_dwarf::dwarf_##reg##_ppc64le, lldb_kind, LLDB_INVALID_REGNUM, \
fpr_##reg##_ppc64le }, \
NULL, NULL, NULL, 0 \
}
#define DEFINE_VMX(reg, lldb_kind) \
{ \
#reg, NULL, 16, VMX_OFFSET(reg), lldb::eEncodingVector, \
lldb::eFormatVectorOfUInt32, \
{ppc64le_dwarf::dwarf_##reg##_ppc64le, \
ppc64le_dwarf::dwarf_##reg##_ppc64le, lldb_kind, LLDB_INVALID_REGNUM, \
vmx_##reg##_ppc64le }, \
NULL, NULL, NULL, 0 \
}
#define DEFINE_VSX(reg, lldb_kind) \
{ \
#reg, NULL, 16, VSX_OFFSET(reg), lldb::eEncodingVector, \
lldb::eFormatVectorOfUInt32, \
{ppc64le_dwarf::dwarf_##reg##_ppc64le, \
ppc64le_dwarf::dwarf_##reg##_ppc64le, lldb_kind, LLDB_INVALID_REGNUM, \
vsx_##reg##_ppc64le }, \
NULL, NULL, NULL, 0 \
}
// General purpose registers.
// EH_Frame, Generic, Process Plugin
@ -76,7 +106,172 @@
DEFINE_GPR(cr, "cr", LLDB_REGNUM_GENERIC_FLAGS), \
DEFINE_GPR(softe, "softe", LLDB_INVALID_REGNUM), \
DEFINE_GPR(trap, "trap", LLDB_INVALID_REGNUM), \
/* */
DEFINE_FPR(f0, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f1, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f2, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f3, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f4, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f5, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f6, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f7, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f8, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f9, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f10, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f11, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f12, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f13, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f14, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f15, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f16, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f17, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f18, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f19, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f20, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f21, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f22, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f23, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f24, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f25, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f26, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f27, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f28, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f29, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f30, NULL, LLDB_INVALID_REGNUM), \
DEFINE_FPR(f31, NULL, LLDB_INVALID_REGNUM), \
{"fpscr", \
NULL, \
8, \
FPR_OFFSET(fpscr), \
lldb::eEncodingUint, \
lldb::eFormatHex, \
{ppc64le_dwarf::dwarf_fpscr_ppc64le, \
ppc64le_dwarf::dwarf_fpscr_ppc64le, LLDB_INVALID_REGNUM, \
LLDB_INVALID_REGNUM, fpr_fpscr_ppc64le}, \
NULL, \
NULL, \
NULL, \
0}, \
DEFINE_VMX(vr0, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr1, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr2, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr3, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr4, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr5, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr6, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr7, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr8, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr9, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr10, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr11, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr12, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr13, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr14, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr15, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr16, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr17, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr18, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr19, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr20, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr21, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr22, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr23, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr24, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr25, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr26, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr27, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr28, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr29, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr30, LLDB_INVALID_REGNUM), \
DEFINE_VMX(vr31, LLDB_INVALID_REGNUM), \
{"vscr", \
NULL, \
4, \
VMX_OFFSET(vscr), \
lldb::eEncodingUint, \
lldb::eFormatHex, \
{ppc64le_dwarf::dwarf_vscr_ppc64le, ppc64le_dwarf::dwarf_vscr_ppc64le, \
LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, vmx_vscr_ppc64le}, \
NULL, \
NULL, \
NULL, \
0}, \
{"vrsave", \
NULL, \
4, \
VMX_OFFSET(vrsave), \
lldb::eEncodingUint, \
lldb::eFormatHex, \
{ppc64le_dwarf::dwarf_vrsave_ppc64le, \
ppc64le_dwarf::dwarf_vrsave_ppc64le, LLDB_INVALID_REGNUM, \
LLDB_INVALID_REGNUM, vmx_vrsave_ppc64le}, \
NULL, \
NULL, \
NULL, \
0}, \
DEFINE_VSX(vs0, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs1, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs2, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs3, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs4, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs5, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs6, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs7, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs8, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs9, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs10, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs11, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs12, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs13, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs14, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs15, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs16, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs17, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs18, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs19, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs20, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs21, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs22, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs23, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs24, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs25, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs26, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs27, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs28, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs29, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs30, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs31, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs32, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs33, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs34, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs35, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs36, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs37, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs38, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs39, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs40, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs41, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs42, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs43, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs44, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs45, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs46, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs47, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs48, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs49, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs50, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs51, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs52, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs53, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs54, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs55, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs56, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs57, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs58, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs59, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs50, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs61, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs62, LLDB_INVALID_REGNUM), \
DEFINE_VSX(vs63, LLDB_INVALID_REGNUM), /* */
typedef struct _GPR {
uint64_t r0;
@ -120,9 +315,150 @@ typedef struct _GPR {
uint64_t cr;
uint64_t softe;
uint64_t trap;
uint64_t pad[4];
uint64_t pad[3];
} GPR;
typedef struct _FPR {
uint64_t f0;
uint64_t f1;
uint64_t f2;
uint64_t f3;
uint64_t f4;
uint64_t f5;
uint64_t f6;
uint64_t f7;
uint64_t f8;
uint64_t f9;
uint64_t f10;
uint64_t f11;
uint64_t f12;
uint64_t f13;
uint64_t f14;
uint64_t f15;
uint64_t f16;
uint64_t f17;
uint64_t f18;
uint64_t f19;
uint64_t f20;
uint64_t f21;
uint64_t f22;
uint64_t f23;
uint64_t f24;
uint64_t f25;
uint64_t f26;
uint64_t f27;
uint64_t f28;
uint64_t f29;
uint64_t f30;
uint64_t f31;
uint64_t fpscr;
} FPR;
typedef struct _VMX {
uint32_t vr0[4];
uint32_t vr1[4];
uint32_t vr2[4];
uint32_t vr3[4];
uint32_t vr4[4];
uint32_t vr5[4];
uint32_t vr6[4];
uint32_t vr7[4];
uint32_t vr8[4];
uint32_t vr9[4];
uint32_t vr10[4];
uint32_t vr11[4];
uint32_t vr12[4];
uint32_t vr13[4];
uint32_t vr14[4];
uint32_t vr15[4];
uint32_t vr16[4];
uint32_t vr17[4];
uint32_t vr18[4];
uint32_t vr19[4];
uint32_t vr20[4];
uint32_t vr21[4];
uint32_t vr22[4];
uint32_t vr23[4];
uint32_t vr24[4];
uint32_t vr25[4];
uint32_t vr26[4];
uint32_t vr27[4];
uint32_t vr28[4];
uint32_t vr29[4];
uint32_t vr30[4];
uint32_t vr31[4];
uint32_t pad[2];
uint32_t vscr[2];
uint32_t vrsave;
} VMX;
typedef struct _VSX {
uint32_t vs0[4];
uint32_t vs1[4];
uint32_t vs2[4];
uint32_t vs3[4];
uint32_t vs4[4];
uint32_t vs5[4];
uint32_t vs6[4];
uint32_t vs7[4];
uint32_t vs8[4];
uint32_t vs9[4];
uint32_t vs10[4];
uint32_t vs11[4];
uint32_t vs12[4];
uint32_t vs13[4];
uint32_t vs14[4];
uint32_t vs15[4];
uint32_t vs16[4];
uint32_t vs17[4];
uint32_t vs18[4];
uint32_t vs19[4];
uint32_t vs20[4];
uint32_t vs21[4];
uint32_t vs22[4];
uint32_t vs23[4];
uint32_t vs24[4];
uint32_t vs25[4];
uint32_t vs26[4];
uint32_t vs27[4];
uint32_t vs28[4];
uint32_t vs29[4];
uint32_t vs30[4];
uint32_t vs31[4];
uint32_t vs32[4];
uint32_t vs33[4];
uint32_t vs34[4];
uint32_t vs35[4];
uint32_t vs36[4];
uint32_t vs37[4];
uint32_t vs38[4];
uint32_t vs39[4];
uint32_t vs40[4];
uint32_t vs41[4];
uint32_t vs42[4];
uint32_t vs43[4];
uint32_t vs44[4];
uint32_t vs45[4];
uint32_t vs46[4];
uint32_t vs47[4];
uint32_t vs48[4];
uint32_t vs49[4];
uint32_t vs50[4];
uint32_t vs51[4];
uint32_t vs52[4];
uint32_t vs53[4];
uint32_t vs54[4];
uint32_t vs55[4];
uint32_t vs56[4];
uint32_t vs57[4];
uint32_t vs58[4];
uint32_t vs59[4];
uint32_t vs60[4];
uint32_t vs61[4];
uint32_t vs62[4];
uint32_t vs63[4];
} VSX;
static lldb_private::RegisterInfo g_register_infos_ppc64le[] = {
POWERPC_REGS
};
@ -132,6 +468,9 @@ static_assert((sizeof(g_register_infos_ppc64le) /
k_num_registers_ppc64le,
"g_register_infos_powerpc64 has wrong number of register infos");
#undef DEFINE_FPR
#undef DEFINE_GPR
#undef DEFINE_VMX
#undef DEFINE_VSX
#endif // DECLARE_REGISTER_INFOS_PPC64LE_STRUCT

143
lldb/source/Plugins/Process/Utility/lldb-ppc64le-register-enums.h
View File

@ -60,8 +60,151 @@ enum {
gpr_trap_ppc64le,
k_last_gpr_ppc64le = gpr_trap_ppc64le,
k_first_fpr_ppc64le,
fpr_f0_ppc64le = k_first_fpr_ppc64le,
fpr_f1_ppc64le,
fpr_f2_ppc64le,
fpr_f3_ppc64le,
fpr_f4_ppc64le,
fpr_f5_ppc64le,
fpr_f6_ppc64le,
fpr_f7_ppc64le,
fpr_f8_ppc64le,
fpr_f9_ppc64le,
fpr_f10_ppc64le,
fpr_f11_ppc64le,
fpr_f12_ppc64le,
fpr_f13_ppc64le,
fpr_f14_ppc64le,
fpr_f15_ppc64le,
fpr_f16_ppc64le,
fpr_f17_ppc64le,
fpr_f18_ppc64le,
fpr_f19_ppc64le,
fpr_f20_ppc64le,
fpr_f21_ppc64le,
fpr_f22_ppc64le,
fpr_f23_ppc64le,
fpr_f24_ppc64le,
fpr_f25_ppc64le,
fpr_f26_ppc64le,
fpr_f27_ppc64le,
fpr_f28_ppc64le,
fpr_f29_ppc64le,
fpr_f30_ppc64le,
fpr_f31_ppc64le,
fpr_fpscr_ppc64le,
k_last_fpr_ppc64le = fpr_fpscr_ppc64le,
k_first_vmx_ppc64le,
vmx_vr0_ppc64le = k_first_vmx_ppc64le,
vmx_vr1_ppc64le,
vmx_vr2_ppc64le,
vmx_vr3_ppc64le,
vmx_vr4_ppc64le,
vmx_vr5_ppc64le,
vmx_vr6_ppc64le,
vmx_vr7_ppc64le,
vmx_vr8_ppc64le,
vmx_vr9_ppc64le,
vmx_vr10_ppc64le,
vmx_vr11_ppc64le,
vmx_vr12_ppc64le,
vmx_vr13_ppc64le,
vmx_vr14_ppc64le,
vmx_vr15_ppc64le,
vmx_vr16_ppc64le,
vmx_vr17_ppc64le,
vmx_vr18_ppc64le,
vmx_vr19_ppc64le,
vmx_vr20_ppc64le,
vmx_vr21_ppc64le,
vmx_vr22_ppc64le,
vmx_vr23_ppc64le,
vmx_vr24_ppc64le,
vmx_vr25_ppc64le,
vmx_vr26_ppc64le,
vmx_vr27_ppc64le,
vmx_vr28_ppc64le,
vmx_vr29_ppc64le,
vmx_vr30_ppc64le,
vmx_vr31_ppc64le,
vmx_vscr_ppc64le,
vmx_vrsave_ppc64le,
k_last_vmx_ppc64le = vmx_vrsave_ppc64le,
k_first_vsx_ppc64le,
vsx_vs0_ppc64le = k_first_vsx_ppc64le,
vsx_vs1_ppc64le,
vsx_vs2_ppc64le,
vsx_vs3_ppc64le,
vsx_vs4_ppc64le,
vsx_vs5_ppc64le,
vsx_vs6_ppc64le,
vsx_vs7_ppc64le,
vsx_vs8_ppc64le,
vsx_vs9_ppc64le,
vsx_vs10_ppc64le,
vsx_vs11_ppc64le,
vsx_vs12_ppc64le,
vsx_vs13_ppc64le,
vsx_vs14_ppc64le,
vsx_vs15_ppc64le,
vsx_vs16_ppc64le,
vsx_vs17_ppc64le,
vsx_vs18_ppc64le,
vsx_vs19_ppc64le,
vsx_vs20_ppc64le,
vsx_vs21_ppc64le,
vsx_vs22_ppc64le,
vsx_vs23_ppc64le,
vsx_vs24_ppc64le,
vsx_vs25_ppc64le,
vsx_vs26_ppc64le,
vsx_vs27_ppc64le,
vsx_vs28_ppc64le,
vsx_vs29_ppc64le,
vsx_vs30_ppc64le,
vsx_vs31_ppc64le,
vsx_vs32_ppc64le,
vsx_vs33_ppc64le,
vsx_vs34_ppc64le,
vsx_vs35_ppc64le,
vsx_vs36_ppc64le,
vsx_vs37_ppc64le,
vsx_vs38_ppc64le,
vsx_vs39_ppc64le,
vsx_vs40_ppc64le,
vsx_vs41_ppc64le,
vsx_vs42_ppc64le,
vsx_vs43_ppc64le,
vsx_vs44_ppc64le,
vsx_vs45_ppc64le,
vsx_vs46_ppc64le,
vsx_vs47_ppc64le,
vsx_vs48_ppc64le,
vsx_vs49_ppc64le,
vsx_vs50_ppc64le,
vsx_vs51_ppc64le,
vsx_vs52_ppc64le,
vsx_vs53_ppc64le,
vsx_vs54_ppc64le,
vsx_vs55_ppc64le,
vsx_vs56_ppc64le,
vsx_vs57_ppc64le,
vsx_vs58_ppc64le,
vsx_vs59_ppc64le,
vsx_vs60_ppc64le,
vsx_vs61_ppc64le,
vsx_vs62_ppc64le,
vsx_vs63_ppc64le,
k_last_vsx_ppc64le = vsx_vs63_ppc64le,
k_num_registers_ppc64le,
k_num_gpr_registers_ppc64le = k_last_gpr_ppc64le - k_first_gpr_ppc64le + 1,
k_num_fpr_registers_ppc64le = k_last_fpr_ppc64le - k_first_fpr_ppc64le + 1,
k_num_vmx_registers_ppc64le = k_last_vmx_ppc64le - k_first_vmx_ppc64le + 1,
k_num_vsx_registers_ppc64le = k_last_vsx_ppc64le - k_first_vsx_ppc64le + 1,
};
#endif // #ifndef lldb_ppc64le_register_enums_h

131
lldb/source/Utility/PPC64LE_DWARF_Registers.h
View File

@ -47,15 +47,146 @@ enum {
dwarf_r29_ppc64le,
dwarf_r30_ppc64le,
dwarf_r31_ppc64le,
dwarf_f0_ppc64le,
dwarf_f1_ppc64le,
dwarf_f2_ppc64le,
dwarf_f3_ppc64le,
dwarf_f4_ppc64le,
dwarf_f5_ppc64le,
dwarf_f6_ppc64le,
dwarf_f7_ppc64le,
dwarf_f8_ppc64le,
dwarf_f9_ppc64le,
dwarf_f10_ppc64le,
dwarf_f11_ppc64le,
dwarf_f12_ppc64le,
dwarf_f13_ppc64le,
dwarf_f14_ppc64le,
dwarf_f15_ppc64le,
dwarf_f16_ppc64le,
dwarf_f17_ppc64le,
dwarf_f18_ppc64le,
dwarf_f19_ppc64le,
dwarf_f20_ppc64le,
dwarf_f21_ppc64le,
dwarf_f22_ppc64le,
dwarf_f23_ppc64le,
dwarf_f24_ppc64le,
dwarf_f25_ppc64le,
dwarf_f26_ppc64le,
dwarf_f27_ppc64le,
dwarf_f28_ppc64le,
dwarf_f29_ppc64le,
dwarf_f30_ppc64le,
dwarf_f31_ppc64le,
dwarf_lr_ppc64le = 65,
dwarf_ctr_ppc64le,
dwarf_cr_ppc64le = 68,
dwarf_xer_ppc64le = 76,
dwarf_vr0_ppc64le,
dwarf_vr1_ppc64le,
dwarf_vr2_ppc64le,
dwarf_vr3_ppc64le,
dwarf_vr4_ppc64le,
dwarf_vr5_ppc64le,
dwarf_vr6_ppc64le,
dwarf_vr7_ppc64le,
dwarf_vr8_ppc64le,
dwarf_vr9_ppc64le,
dwarf_vr10_ppc64le,
dwarf_vr11_ppc64le,
dwarf_vr12_ppc64le,
dwarf_vr13_ppc64le,
dwarf_vr14_ppc64le,
dwarf_vr15_ppc64le,
dwarf_vr16_ppc64le,
dwarf_vr17_ppc64le,
dwarf_vr18_ppc64le,
dwarf_vr19_ppc64le,
dwarf_vr20_ppc64le,
dwarf_vr21_ppc64le,
dwarf_vr22_ppc64le,
dwarf_vr23_ppc64le,
dwarf_vr24_ppc64le,
dwarf_vr25_ppc64le,
dwarf_vr26_ppc64le,
dwarf_vr27_ppc64le,
dwarf_vr28_ppc64le,
dwarf_vr29_ppc64le,
dwarf_vr30_ppc64le,
dwarf_vr31_ppc64le,
dwarf_vscr_ppc64le = 110,
dwarf_vrsave_ppc64le = 117,
dwarf_pc_ppc64le,
dwarf_softe_ppc64le,
dwarf_trap_ppc64le,
dwarf_origr3_ppc64le,
dwarf_fpscr_ppc64le,
dwarf_msr_ppc64le,
dwarf_vs0_ppc64le,
dwarf_vs1_ppc64le,
dwarf_vs2_ppc64le,
dwarf_vs3_ppc64le,
dwarf_vs4_ppc64le,
dwarf_vs5_ppc64le,
dwarf_vs6_ppc64le,
dwarf_vs7_ppc64le,
dwarf_vs8_ppc64le,
dwarf_vs9_ppc64le,
dwarf_vs10_ppc64le,
dwarf_vs11_ppc64le,
dwarf_vs12_ppc64le,
dwarf_vs13_ppc64le,
dwarf_vs14_ppc64le,
dwarf_vs15_ppc64le,
dwarf_vs16_ppc64le,
dwarf_vs17_ppc64le,
dwarf_vs18_ppc64le,
dwarf_vs19_ppc64le,
dwarf_vs20_ppc64le,
dwarf_vs21_ppc64le,
dwarf_vs22_ppc64le,
dwarf_vs23_ppc64le,
dwarf_vs24_ppc64le,
dwarf_vs25_ppc64le,
dwarf_vs26_ppc64le,
dwarf_vs27_ppc64le,
dwarf_vs28_ppc64le,
dwarf_vs29_ppc64le,
dwarf_vs30_ppc64le,
dwarf_vs31_ppc64le,
dwarf_vs32_ppc64le,
dwarf_vs33_ppc64le,
dwarf_vs34_ppc64le,
dwarf_vs35_ppc64le,
dwarf_vs36_ppc64le,
dwarf_vs37_ppc64le,
dwarf_vs38_ppc64le,
dwarf_vs39_ppc64le,
dwarf_vs40_ppc64le,
dwarf_vs41_ppc64le,
dwarf_vs42_ppc64le,
dwarf_vs43_ppc64le,
dwarf_vs44_ppc64le,
dwarf_vs45_ppc64le,
dwarf_vs46_ppc64le,
dwarf_vs47_ppc64le,
dwarf_vs48_ppc64le,
dwarf_vs49_ppc64le,
dwarf_vs50_ppc64le,
dwarf_vs51_ppc64le,
dwarf_vs52_ppc64le,
dwarf_vs53_ppc64le,
dwarf_vs54_ppc64le,
dwarf_vs55_ppc64le,
dwarf_vs56_ppc64le,
dwarf_vs57_ppc64le,
dwarf_vs58_ppc64le,
dwarf_vs59_ppc64le,
dwarf_vs60_ppc64le,
dwarf_vs61_ppc64le,
dwarf_vs62_ppc64le,
dwarf_vs63_ppc64le,
};
} // namespace ppc64le_dwarf

131
lldb/source/Utility/PPC64LE_ehframe_Registers.h
View File

@ -48,15 +48,146 @@ enum {
r29,
r30,
r31,
f0,
f1,
f2,
f3,
f4,
f5,
f6,
f7,
f8,
f9,
f10,
f11,
f12,
f13,
f14,
f15,
f16,
f17,
f18,
f19,
f20,
f21,
f22,
f23,
f24,
f25,
f26,
f27,
f28,
f29,
f30,
f31,
lr = 65,
ctr,
cr = 68,
xer = 76,
vr0,
vr1,
vr2,
vr3,
vr4,
vr5,
vr6,
vr7,
vr8,
vr9,
vr10,
vr11,
vr12,
vr13,
vr14,
vr15,
vr16,
vr17,
vr18,
vr19,
vr20,
vr21,
vr22,
vr23,
vr24,
vr25,
vr26,
vr27,
vr28,
vr29,
vr30,
vr31,
vscr = 110,
vrsave = 117,
pc,
softe,
trap,
origr3,
fpscr,
msr,
vs0,
vs1,
vs2,
vs3,
vs4,
vs5,
vs6,
vs7,
vs8,
vs9,
vs10,
vs11,
vs12,
vs13,
vs14,
vs15,
vs16,
vs17,
vs18,
vs19,
vs20,
vs21,
vs22,
vs23,
vs24,
vs25,
vs26,
vs27,
vs28,
vs29,
vs30,
vs31,
vs32,
vs33,
vs34,
vs35,
vs36,
vs37,
vs38,
vs39,
vs40,
vs41,
vs42,
vs43,
vs44,
vs45,
vs46,
vs47,
vs48,
vs49,
vs50,
vs51,
vs52,
vs53,
vs54,
vs55,
vs56,
vs57,
vs58,
vs59,
vs60,
vs61,
vs62,
vs63,
};
}