forked from OSchip/llvm-project
Simplify more cases of logical ops of masked icmps.
Summary: For example, ((X & 255) != 0) && ((X & 15) == 8) -> ((X & 15) == 8). ((X & 7) != 0) && ((X & 15) == 8) -> false. Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43835 llvm-svn: 327450
This commit is contained in:
Hiroshi Yamauchi
parent
f69d07e788
commit
e6a3dc7699
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@ -305,17 +305,21 @@ static bool decomposeBitTestICmp(Value *LHS, Value *RHS, CmpInst::Predicate &Pre
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}
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/// Handle (icmp(A & B) ==/!= C) &/| (icmp(A & D) ==/!= E).
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/// Return the set of pattern classes (from MaskedICmpType) that both LHS and
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/// RHS satisfy.
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static unsigned getMaskedTypeForICmpPair(Value *&A, Value *&B, Value *&C,
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Value *&D, Value *&E, ICmpInst *LHS,
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ICmpInst *RHS,
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ICmpInst::Predicate &PredL,
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ICmpInst::Predicate &PredR) {
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/// Return the pattern classes (from MaskedICmpType) for the left hand side and
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/// the right hand side as a pair.
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/// LHS and RHS are the left hand side and the right hand side ICmps and PredL
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/// and PredR are their predicates, respectively.
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static
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Optional<std::pair<unsigned, unsigned>>
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getMaskedTypeForICmpPair(Value *&A, Value *&B, Value *&C,
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Value *&D, Value *&E, ICmpInst *LHS,
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ICmpInst *RHS,
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ICmpInst::Predicate &PredL,
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ICmpInst::Predicate &PredR) {
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// vectors are not (yet?) supported. Don't support pointers either.
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if (!LHS->getOperand(0)->getType()->isIntegerTy() ||
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!RHS->getOperand(0)->getType()->isIntegerTy())
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return 0;
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return None;
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// Here comes the tricky part:
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// LHS might be of the form L11 & L12 == X, X == L21 & L22,
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@ -346,7 +350,7 @@ static unsigned getMaskedTypeForICmpPair(Value *&A, Value *&B, Value *&C,
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// Bail if LHS was a icmp that can't be decomposed into an equality.
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if (!ICmpInst::isEquality(PredL))
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return 0;
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return None;
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Value *R1 = RHS->getOperand(0);
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Value *R2 = RHS->getOperand(1);
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@ -360,7 +364,7 @@ static unsigned getMaskedTypeForICmpPair(Value *&A, Value *&B, Value *&C,
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A = R12;
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D = R11;
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} else {
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return 0;
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return None;
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}
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E = R2;
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R1 = nullptr;
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@ -388,7 +392,7 @@ static unsigned getMaskedTypeForICmpPair(Value *&A, Value *&B, Value *&C,
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// Bail if RHS was a icmp that can't be decomposed into an equality.
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if (!ICmpInst::isEquality(PredR))
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return 0;
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return None;
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// Look for ANDs on the right side of the RHS icmp.
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if (!Ok) {
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@ -408,11 +412,11 @@ static unsigned getMaskedTypeForICmpPair(Value *&A, Value *&B, Value *&C,
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E = R1;
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Ok = true;
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} else {
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return 0;
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return None;
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}
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}
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if (!Ok)
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return 0;
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return None;
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if (L11 == A) {
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B = L12;
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@ -430,7 +434,174 @@ static unsigned getMaskedTypeForICmpPair(Value *&A, Value *&B, Value *&C,
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unsigned LeftType = getMaskedICmpType(A, B, C, PredL);
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unsigned RightType = getMaskedICmpType(A, D, E, PredR);
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return LeftType & RightType;
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return Optional<std::pair<unsigned, unsigned>>(std::make_pair(LeftType, RightType));
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}
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/// Try to fold (icmp(A & B) ==/!= C) &/| (icmp(A & D) ==/!= E) into a single
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/// (icmp(A & X) ==/!= Y), where the left-hand side is of type Mask_NotAllZeros
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/// and the right hand side is of type BMask_Mixed. For example,
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/// (icmp (A & 12) != 0) & (icmp (A & 15) == 8) -> (icmp (A & 15) == 8).
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static Value * foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed(
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ICmpInst *LHS, ICmpInst *RHS, bool IsAnd,
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Value *A, Value *B, Value *C, Value *D, Value *E,
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ICmpInst::Predicate PredL, ICmpInst::Predicate PredR,
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llvm::InstCombiner::BuilderTy &Builder) {
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// We are given the canonical form:
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// (icmp ne (A & B), 0) & (icmp eq (A & D), E).
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// where D & E == E.
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//
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// If IsAnd is false, we get it in negated form:
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// (icmp eq (A & B), 0) | (icmp ne (A & D), E) ->
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// !((icmp ne (A & B), 0) & (icmp eq (A & D), E)).
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//
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// We currently handle the case of B, C, D, E are constant.
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//
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ConstantInt *BCst = dyn_cast<ConstantInt>(B);
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if (!BCst)
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return nullptr;
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ConstantInt *CCst = dyn_cast<ConstantInt>(C);
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if (!CCst)
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return nullptr;
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ConstantInt *DCst = dyn_cast<ConstantInt>(D);
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if (!DCst)
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return nullptr;
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ConstantInt *ECst = dyn_cast<ConstantInt>(E);
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if (!ECst)
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return nullptr;
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ICmpInst::Predicate NewCC = IsAnd ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_NE;
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// Update E to the canonical form when D is a power of two and RHS is
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// canonicalized as,
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// (icmp ne (A & D), 0) -> (icmp eq (A & D), D) or
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// (icmp ne (A & D), D) -> (icmp eq (A & D), 0).
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if (PredR != NewCC)
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ECst = cast<ConstantInt>(ConstantExpr::getXor(DCst, ECst));
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// If B or D is zero, skip because if LHS or RHS can be trivially folded by
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// other folding rules and this pattern won't apply any more.
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if (BCst->getValue() == 0 || DCst->getValue() == 0)
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return nullptr;
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// If B and D don't intersect, ie. (B & D) == 0, no folding because we can't
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// deduce anything from it.
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// For example,
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// (icmp ne (A & 12), 0) & (icmp eq (A & 3), 1) -> no folding.
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if ((BCst->getValue() & DCst->getValue()) == 0)
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return nullptr;
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// If the following two conditions are met:
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//
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// 1. mask B covers only a single bit that's not covered by mask D, that is,
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// (B & (B ^ D)) is a power of 2 (in other words, B minus the intersection of
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// B and D has only one bit set) and,
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//
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// 2. RHS (and E) indicates that the rest of B's bits are zero (in other
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// words, the intersection of B and D is zero), that is, ((B & D) & E) == 0
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//
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// then that single bit in B must be one and thus the whole expression can be
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// folded to
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// (A & (B | D)) == (B & (B ^ D)) | E.
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//
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// For example,
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// (icmp ne (A & 12), 0) & (icmp eq (A & 7), 1) -> (icmp eq (A & 15), 9)
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// (icmp ne (A & 15), 0) & (icmp eq (A & 7), 0) -> (icmp eq (A & 15), 8)
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if ((((BCst->getValue() & DCst->getValue()) & ECst->getValue()) == 0) &&
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(BCst->getValue() & (BCst->getValue() ^ DCst->getValue())).isPowerOf2()) {
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APInt BorD = BCst->getValue() | DCst->getValue();
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APInt BandBxorDorE = (BCst->getValue() & (BCst->getValue() ^ DCst->getValue())) |
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ECst->getValue();
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Value *NewMask = ConstantInt::get(BCst->getType(), BorD);
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Value *NewMaskedValue = ConstantInt::get(BCst->getType(), BandBxorDorE);
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Value *NewAnd = Builder.CreateAnd(A, NewMask);
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return Builder.CreateICmp(NewCC, NewAnd, NewMaskedValue);
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}
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auto IsSubSetOrEqual = [](ConstantInt *C1, ConstantInt *C2) {
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return (C1->getValue() & C2->getValue()) == C1->getValue();
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};
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auto IsSuperSetOrEqual = [](ConstantInt *C1, ConstantInt *C2) {
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return (C1->getValue() & C2->getValue()) == C2->getValue();
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};
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// In the following, we consider only the cases where B is a superset of D, B
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// is a subset of D, or B == D because otherwise there's at least one bit
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// covered by B but not D, in which case we can't deduce much from it, so
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// no folding (aside from the single must-be-one bit case right above.)
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// For example,
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// (icmp ne (A & 14), 0) & (icmp eq (A & 3), 1) -> no folding.
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if (!IsSubSetOrEqual(BCst, DCst) && !IsSuperSetOrEqual(BCst, DCst))
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return nullptr;
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// At this point, either B is a superset of D, B is a subset of D or B == D.
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// If E is zero, if B is a subset of (or equal to) D, LHS and RHS contradict
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// and the whole expression becomes false (or true if negated), otherwise, no
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// folding.
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// For example,
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// (icmp ne (A & 3), 0) & (icmp eq (A & 7), 0) -> false.
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// (icmp ne (A & 15), 0) & (icmp eq (A & 3), 0) -> no folding.
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if (ECst->isZero()) {
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if (IsSubSetOrEqual(BCst, DCst))
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return ConstantInt::get(LHS->getType(), !IsAnd);
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return nullptr;
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}
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// At this point, B, D, E aren't zero and (B & D) == B, (B & D) == D or B ==
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// D. If B is a superset of (or equal to) D, since E is not zero, LHS is
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// subsumed by RHS (RHS implies LHS.) So the whole expression becomes
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// RHS. For example,
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// (icmp ne (A & 255), 0) & (icmp eq (A & 15), 8) -> (icmp eq (A & 15), 8).
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// (icmp ne (A & 15), 0) & (icmp eq (A & 15), 8) -> (icmp eq (A & 15), 8).
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if (IsSuperSetOrEqual(BCst, DCst))
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return RHS;
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// Otherwise, B is a subset of D. If B and E have a common bit set,
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// ie. (B & E) != 0, then LHS is subsumed by RHS. For example.
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// (icmp ne (A & 12), 0) & (icmp eq (A & 15), 8) -> (icmp eq (A & 15), 8).
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assert(IsSubSetOrEqual(BCst, DCst) && "Precondition due to above code");
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if ((BCst->getValue() & ECst->getValue()) != 0)
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return RHS;
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// Otherwise, LHS and RHS contradict and the whole expression becomes false
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// (or true if negated.) For example,
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// (icmp ne (A & 7), 0) & (icmp eq (A & 15), 8) -> false.
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// (icmp ne (A & 6), 0) & (icmp eq (A & 15), 8) -> false.
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return ConstantInt::get(LHS->getType(), !IsAnd);
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}
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/// Try to fold (icmp(A & B) ==/!= 0) &/| (icmp(A & D) ==/!= E) into a single
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/// (icmp(A & X) ==/!= Y), where the left-hand side and the right hand side
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/// aren't of the common mask pattern type.
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static Value *foldLogOpOfMaskedICmpsAsymmetric(
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ICmpInst *LHS, ICmpInst *RHS, bool IsAnd,
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Value *A, Value *B, Value *C, Value *D, Value *E,
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ICmpInst::Predicate PredL, ICmpInst::Predicate PredR,
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unsigned LHSMask, unsigned RHSMask,
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llvm::InstCombiner::BuilderTy &Builder) {
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assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) &&
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"Expected equality predicates for masked type of icmps.");
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// Handle Mask_NotAllZeros-BMask_Mixed cases.
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// (icmp ne/eq (A & B), C) &/| (icmp eq/ne (A & D), E), or
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// (icmp eq/ne (A & B), C) &/| (icmp ne/eq (A & D), E)
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// which gets swapped to
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// (icmp ne/eq (A & D), E) &/| (icmp eq/ne (A & B), C).
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if (!IsAnd) {
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LHSMask = conjugateICmpMask(LHSMask);
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RHSMask = conjugateICmpMask(RHSMask);
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}
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if ((LHSMask & Mask_NotAllZeros) && (RHSMask & BMask_Mixed)) {
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if (Value *V = foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed(
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LHS, RHS, IsAnd, A, B, C, D, E,
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PredL, PredR, Builder)) {
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return V;
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}
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} else if ((LHSMask & BMask_Mixed) && (RHSMask & Mask_NotAllZeros)) {
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if (Value *V = foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed(
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RHS, LHS, IsAnd, A, D, E, B, C,
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PredR, PredL, Builder)) {
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return V;
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}
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}
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return nullptr;
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}
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/// Try to fold (icmp(A & B) ==/!= C) &/| (icmp(A & D) ==/!= E)
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@ -439,13 +610,24 @@ static Value *foldLogOpOfMaskedICmps(ICmpInst *LHS, ICmpInst *RHS, bool IsAnd,
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llvm::InstCombiner::BuilderTy &Builder) {
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Value *A = nullptr, *B = nullptr, *C = nullptr, *D = nullptr, *E = nullptr;
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ICmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate();
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unsigned Mask =
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Optional<std::pair<unsigned, unsigned>> MaskPair =
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getMaskedTypeForICmpPair(A, B, C, D, E, LHS, RHS, PredL, PredR);
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if (Mask == 0)
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if (!MaskPair)
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return nullptr;
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assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) &&
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"Expected equality predicates for masked type of icmps.");
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unsigned LHSMask = MaskPair->first;
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unsigned RHSMask = MaskPair->second;
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unsigned Mask = LHSMask & RHSMask;
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if (Mask == 0) {
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// Even if the two sides don't share a common pattern, check if folding can
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// still happen.
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if (Value *V = foldLogOpOfMaskedICmpsAsymmetric(
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LHS, RHS, IsAnd, A, B, C, D, E, PredL, PredR, LHSMask, RHSMask,
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Builder))
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return V;
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return nullptr;
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}
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// In full generality:
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// (icmp (A & B) Op C) | (icmp (A & D) Op E)
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@ -183,3 +183,697 @@ define <2 x i1> @cmpne_bitwise(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i6
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ret <2 x i1> %cmp
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}
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; ((X & 12) != 0 & (X & 3) == 1) -> no change
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_0(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_0(
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; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 12
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
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; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1
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; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP1]], [[CMP2]]
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; CHECK-NEXT: ret i1 [[AND3]]
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;
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%1 = and i32 %x, 12
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 3
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%4 = icmp eq i32 %3, 1
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 12) != 0 & (X & 7) == 1) -> (X & 15) == 9
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_1(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1(
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; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 9
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; CHECK-NEXT: ret i1 [[CMP1]]
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;
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%1 = and i32 %x, 12
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 7
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%4 = icmp eq i32 %3, 1
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 14) != 0 & (X & 3) == 1) -> no change
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_1b(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1b(
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; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 14
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
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; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1
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; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP1]], [[CMP2]]
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; CHECK-NEXT: ret i1 [[AND3]]
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;
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%1 = and i32 %x, 14
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 3
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%4 = icmp eq i32 %3, 1
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 3) != 0 & (X & 7) == 0) -> false
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_2(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_2(
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; CHECK-NEXT: ret i1 false
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;
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%1 = and i32 %x, 3
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 7
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%4 = icmp eq i32 %3, 0
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 15) != 0 & (X & 7) == 0) -> (X & 15) == 8
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_3(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_3(
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; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
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; CHECK-NEXT: ret i1 [[CMP1]]
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;
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%1 = and i32 %x, 15
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 7
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%4 = icmp eq i32 %3, 0
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%5 = and i1 %2, %4
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ret i1 %5
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}
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|
||||
; ((X & 15) != 0 & (X & 3) == 0) -> no change
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_3b(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_3b(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
|
||||
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
||||
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 0
|
||||
; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP1]], [[CMP2]]
|
||||
; CHECK-NEXT: ret i1 [[AND3]]
|
||||
;
|
||||
%1 = and i32 %x, 15
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 3
|
||||
%4 = icmp eq i32 %3, 0
|
||||
%5 = and i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 255) != 0 & (X & 15) == 8) -> (X & 15) == 8
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_4(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_4(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 255
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp eq i32 %3, 8
|
||||
%5 = and i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 15) != 0 & (X & 15) == 8) -> (X & 15) == 8
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_5(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_5(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 15
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp eq i32 %3, 8
|
||||
%5 = and i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 12) != 0 & (X & 15) == 8) -> (X & 15) == 8
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_6(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_6(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 12
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp eq i32 %3, 8
|
||||
%5 = and i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 7) != 0 & (X & 15) == 8) -> false
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_7(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_7(
|
||||
; CHECK-NEXT: ret i1 false
|
||||
;
|
||||
%1 = and i32 %x, 7
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp eq i32 %3, 8
|
||||
%5 = and i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 6) != 0 & (X & 15) == 8) -> false
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_7b(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_7b(
|
||||
; CHECK-NEXT: ret i1 false
|
||||
;
|
||||
%1 = and i32 %x, 6
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp eq i32 %3, 8
|
||||
%5 = and i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 12) == 0 | (X & 3) != 1) -> !((X & 12) != 0 & (X & 3) == 1)) ->
|
||||
; no change
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_0(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_0(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 12
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
|
||||
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
||||
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1
|
||||
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP1]], [[CMP2]]
|
||||
; CHECK-NEXT: ret i1 [[OR1]]
|
||||
;
|
||||
%1 = and i32 %x, 12
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 3
|
||||
%4 = icmp ne i32 %3, 1
|
||||
%5 = or i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 12) == 0 | (X & 7) != 1) -> !((X & 12) != 0 & (X & 7) == 1) ->
|
||||
; !((X & 15) == 9) -> (X & 15) != 9
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_1(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_1(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 9
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 12
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 7
|
||||
%4 = icmp ne i32 %3, 1
|
||||
%5 = or i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 14) == 0 | (X & 3) != 1) -> !((X & 14) != 0 & (X & 3) == 1) ->
|
||||
; no change.
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_1b(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_1b(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 14
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
|
||||
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
||||
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1
|
||||
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP1]], [[CMP2]]
|
||||
; CHECK-NEXT: ret i1 [[OR1]]
|
||||
;
|
||||
%1 = and i32 %x, 14
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 3
|
||||
%4 = icmp ne i32 %3, 1
|
||||
%5 = or i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 3) == 0 | (X & 7) != 0) -> !((X & 3) != 0 & (X & 7) == 0) ->
|
||||
; !(false) -> true
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_2(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_2(
|
||||
; CHECK-NEXT: ret i1 true
|
||||
;
|
||||
%1 = and i32 %x, 3
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 7
|
||||
%4 = icmp ne i32 %3, 0
|
||||
%5 = or i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 15) == 0 | (X & 7) != 0) -> !((X & 15) != 0 & (X & 7) == 0) ->
|
||||
; !((X & 15) == 8) -> (X & 15) != 8
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_3(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_3(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 15
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 7
|
||||
%4 = icmp ne i32 %3, 0
|
||||
%5 = or i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 15) == 0 | (X & 3) != 0) -> !((X & 15) != 0 & (X & 3) == 0) ->
|
||||
; no change.
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_3b(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_3b(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
|
||||
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
||||
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 0
|
||||
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP1]], [[CMP2]]
|
||||
; CHECK-NEXT: ret i1 [[OR1]]
|
||||
;
|
||||
%1 = and i32 %x, 15
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 3
|
||||
%4 = icmp ne i32 %3, 0
|
||||
%5 = or i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 255) == 0 | (X & 15) != 8) -> !(((X & 255) != 0 & (X & 15) == 8)) ->
|
||||
; !((X & 15) == 8) -> ((X & 15) != 8)
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_4(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_4(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 255
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp ne i32 %3, 8
|
||||
%5 = or i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 15) == 0 | (X & 15) != 8) -> !(((X & 15) != 0 & (X & 15) == 8)) ->
|
||||
; !((X & 15) == 8) -> ((X & 15) != 8)
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_5(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_5(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 15
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp ne i32 %3, 8
|
||||
%5 = or i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 12) == 0 | (X & 15) != 8) -> !(((X & 12) != 0 & (X & 15) == 8)) ->
|
||||
; !((X & 15) == 8) -> ((X & 15) != 8
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_6(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_6(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 12
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp ne i32 %3, 8
|
||||
%5 = or i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 7) == 0 | (X & 15) != 8) -> !(((X & 7) != 0 & (X & 15) == 8)) ->
|
||||
; !(false) -> true
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_7(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_7(
|
||||
; CHECK-NEXT: ret i1 true
|
||||
;
|
||||
%1 = and i32 %x, 7
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp ne i32 %3, 8
|
||||
%5 = or i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 6) == 0 | (X & 15) != 8) -> !(((X & 6) != 0 & (X & 15) == 8)) ->
|
||||
; !(false) -> true
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_7b(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_7b(
|
||||
; CHECK-NEXT: ret i1 true
|
||||
;
|
||||
%1 = and i32 %x, 6
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp ne i32 %3, 8
|
||||
%5 = or i1 %2, %4
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
|
||||
; ((X & 12) != 0 & (X & 3) == 1) -> no change
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_0(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_0(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 12
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
|
||||
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
||||
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1
|
||||
; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP2]], [[CMP1]]
|
||||
; CHECK-NEXT: ret i1 [[AND3]]
|
||||
;
|
||||
%1 = and i32 %x, 12
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 3
|
||||
%4 = icmp eq i32 %3, 1
|
||||
%5 = and i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 12) != 0 & (X & 7) == 1) -> (X & 15) == 9
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 9
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 12
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 7
|
||||
%4 = icmp eq i32 %3, 1
|
||||
%5 = and i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 14) != 0 & (X & 3) == 1) -> no change
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1b(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1b(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 14
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
|
||||
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
||||
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1
|
||||
; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP2]], [[CMP1]]
|
||||
; CHECK-NEXT: ret i1 [[AND3]]
|
||||
;
|
||||
%1 = and i32 %x, 14
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 3
|
||||
%4 = icmp eq i32 %3, 1
|
||||
%5 = and i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 3) != 0 & (X & 7) == 0) -> false
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_2(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_2(
|
||||
; CHECK-NEXT: ret i1 false
|
||||
;
|
||||
%1 = and i32 %x, 3
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 7
|
||||
%4 = icmp eq i32 %3, 0
|
||||
%5 = and i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 15) != 0 & (X & 7) == 0) -> (X & 15) == 8
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 15
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 7
|
||||
%4 = icmp eq i32 %3, 0
|
||||
%5 = and i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 15) != 0 & (X & 3) == 0) -> no change
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3b(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3b(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
|
||||
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
||||
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 0
|
||||
; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP2]], [[CMP1]]
|
||||
; CHECK-NEXT: ret i1 [[AND3]]
|
||||
;
|
||||
%1 = and i32 %x, 15
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 3
|
||||
%4 = icmp eq i32 %3, 0
|
||||
%5 = and i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 255) != 0 & (X & 15) == 8) -> (X & 15) == 8
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_4(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_4(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 255
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp eq i32 %3, 8
|
||||
%5 = and i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 15) != 0 & (X & 15) == 8) -> (X & 15) == 8
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_5(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_5(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 15
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp eq i32 %3, 8
|
||||
%5 = and i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 12) != 0 & (X & 15) == 8) -> (X & 15) == 8
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_6(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_6(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 12
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp eq i32 %3, 8
|
||||
%5 = and i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 7) != 0 & (X & 15) == 8) -> false
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7(
|
||||
; CHECK-NEXT: ret i1 false
|
||||
;
|
||||
%1 = and i32 %x, 7
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp eq i32 %3, 8
|
||||
%5 = and i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 6) != 0 & (X & 15) == 8) -> false
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7b(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7b(
|
||||
; CHECK-NEXT: ret i1 false
|
||||
;
|
||||
%1 = and i32 %x, 6
|
||||
%2 = icmp ne i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp eq i32 %3, 8
|
||||
%5 = and i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 12) == 0 | (X & 3) != 1) -> !((X & 12) != 0 & (X & 3) == 1)) ->
|
||||
; no change
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_0(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_0(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 12
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
|
||||
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
||||
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1
|
||||
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP2]], [[CMP1]]
|
||||
; CHECK-NEXT: ret i1 [[OR1]]
|
||||
;
|
||||
%1 = and i32 %x, 12
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 3
|
||||
%4 = icmp ne i32 %3, 1
|
||||
%5 = or i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 12) == 0 | (X & 7) != 1) -> !((X & 12) != 0 & (X & 7) == 1) ->
|
||||
; !((X & 15) == 9) -> (X & 15) != 9
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 9
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 12
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 7
|
||||
%4 = icmp ne i32 %3, 1
|
||||
%5 = or i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 14) == 0 | (X & 3) != 1) -> !((X & 14) != 0 & (X & 3) == 1) ->
|
||||
; no change.
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1b(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1b(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 14
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
|
||||
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
||||
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1
|
||||
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP2]], [[CMP1]]
|
||||
; CHECK-NEXT: ret i1 [[OR1]]
|
||||
;
|
||||
%1 = and i32 %x, 14
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 3
|
||||
%4 = icmp ne i32 %3, 1
|
||||
%5 = or i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 3) == 0 | (X & 7) != 0) -> !((X & 3) != 0 & (X & 7) == 0) ->
|
||||
; !(false) -> true
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_2(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_2(
|
||||
; CHECK-NEXT: ret i1 true
|
||||
;
|
||||
%1 = and i32 %x, 3
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 7
|
||||
%4 = icmp ne i32 %3, 0
|
||||
%5 = or i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 15) == 0 | (X & 7) != 0) -> !((X & 15) != 0 & (X & 7) == 0) ->
|
||||
; !((X & 15) == 8) -> (X & 15) != 8
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 15
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 7
|
||||
%4 = icmp ne i32 %3, 0
|
||||
%5 = or i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 15) == 0 | (X & 3) != 0) -> !((X & 15) != 0 & (X & 3) == 0) ->
|
||||
; no change.
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3b(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3b(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
|
||||
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
||||
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 0
|
||||
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP2]], [[CMP1]]
|
||||
; CHECK-NEXT: ret i1 [[OR1]]
|
||||
;
|
||||
%1 = and i32 %x, 15
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 3
|
||||
%4 = icmp ne i32 %3, 0
|
||||
%5 = or i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 255) == 0 | (X & 15) != 8) -> !(((X & 255) != 0 & (X & 15) == 8)) ->
|
||||
; !((X & 15) == 8) -> ((X & 15) != 8)
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_4(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_4(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 255
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp ne i32 %3, 8
|
||||
%5 = or i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 15) == 0 | (X & 15) != 8) -> !(((X & 15) != 0 & (X & 15) == 8)) ->
|
||||
; !((X & 15) == 8) -> ((X & 15) != 8)
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_5(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_5(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 15
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp ne i32 %3, 8
|
||||
%5 = or i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 12) == 0 | (X & 15) != 8) -> !(((X & 12) != 0 & (X & 15) == 8)) ->
|
||||
; !((X & 15) == 8) -> ((X & 15) != 8
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_6(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_6(
|
||||
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
||||
; CHECK-NEXT: ret i1 [[CMP1]]
|
||||
;
|
||||
%1 = and i32 %x, 12
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp ne i32 %3, 8
|
||||
%5 = or i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 7) == 0 | (X & 15) != 8) -> !(((X & 7) != 0 & (X & 15) == 8)) ->
|
||||
; !(false) -> true
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7(
|
||||
; CHECK-NEXT: ret i1 true
|
||||
;
|
||||
%1 = and i32 %x, 7
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp ne i32 %3, 8
|
||||
%5 = or i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
||||
; ((X & 6) == 0 | (X & 15) != 8) -> !(((X & 6) != 0 & (X & 15) == 8)) ->
|
||||
; !(false) -> true
|
||||
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7b(i32 %x) {
|
||||
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7b(
|
||||
; CHECK-NEXT: ret i1 true
|
||||
;
|
||||
%1 = and i32 %x, 6
|
||||
%2 = icmp eq i32 %1, 0
|
||||
%3 = and i32 %x, 15
|
||||
%4 = icmp ne i32 %3, 8
|
||||
%5 = or i1 %4, %2
|
||||
ret i1 %5
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue