forked from OSchip/llvm-project
Add emulation methods for "EOR (Immediate)", "EOR (register)",
"TEQ (immediate)", and "TEQ (register)" operations. llvm-svn: 126160
This commit is contained in:
Johnny Chen
parent
87a9f19f9c
commit
e69108a78f
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@ -5302,6 +5302,176 @@ EmulateInstructionARM::EmulateLDRBRegister (ARMEncoding encoding)
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return true;
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}
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// Bitwise Exclusive OR (immediate) performs a bitwise exclusive OR of a register value and an immediate value,
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// and writes the result to the destination register. It can optionally update the condition flags based on
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// the result.
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bool
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EmulateInstructionARM::EmulateEORImm (ARMEncoding encoding)
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{
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#if 0
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// ARM pseudo code...
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if ConditionPassed() then
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EncodingSpecificOperations();
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result = R[n] EOR imm32;
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if d == 15 then // Can only occur for ARM encoding
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ALUWritePC(result); // setflags is always FALSE here
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else
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R[d] = result;
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if setflags then
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APSR.N = result<31>;
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APSR.Z = IsZeroBit(result);
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APSR.C = carry;
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// APSR.V unchanged
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#endif
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bool success = false;
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const uint32_t opcode = OpcodeAsUnsigned (&success);
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if (!success)
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return false;
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if (ConditionPassed())
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{
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uint32_t Rd, Rn;
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uint32_t imm32; // the immediate value to be ORed to the value obtained from Rn
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bool setflags;
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uint32_t carry; // the carry bit after ARM/Thumb Expand operation
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switch (encoding)
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{
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case eEncodingT1:
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Rd = Bits32(opcode, 11, 8);
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Rn = Bits32(opcode, 19, 16);
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setflags = BitIsSet(opcode, 20);
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imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
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// if Rd == '1111' && S == '1' then SEE TEQ (immediate);
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if (Rd == 15 && setflags)
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return EmulateTEQImm(eEncodingT1);
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if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
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return false;
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break;
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case eEncodingA1:
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Rd = Bits32(opcode, 15, 12);
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Rn = Bits32(opcode, 19, 16);
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setflags = BitIsSet(opcode, 20);
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imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
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// if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
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// TODO: Emulate SUBS PC, LR and related instructions.
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if (Rd == 15 && setflags)
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return false;
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break;
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default:
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return false;
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}
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// Read the first operand.
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uint32_t val1 = ReadCoreReg(Rn, &success);
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if (!success)
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return false;
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uint32_t result = val1 ^ imm32;
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EmulateInstruction::Context context;
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context.type = EmulateInstruction::eContextImmediate;
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context.SetNoArgs ();
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if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
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return false;
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}
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return true;
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}
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// Bitwise Exclusive OR (register) performs a bitwise exclusive OR of a register value and an
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// optionally-shifted register value, and writes the result to the destination register.
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// It can optionally update the condition flags based on the result.
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bool
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EmulateInstructionARM::EmulateEORReg (ARMEncoding encoding)
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{
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#if 0
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// ARM pseudo code...
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if ConditionPassed() then
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EncodingSpecificOperations();
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(shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
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result = R[n] EOR shifted;
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if d == 15 then // Can only occur for ARM encoding
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ALUWritePC(result); // setflags is always FALSE here
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else
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R[d] = result;
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if setflags then
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APSR.N = result<31>;
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APSR.Z = IsZeroBit(result);
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APSR.C = carry;
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// APSR.V unchanged
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#endif
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bool success = false;
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const uint32_t opcode = OpcodeAsUnsigned (&success);
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if (!success)
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return false;
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if (ConditionPassed())
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{
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uint32_t Rd, Rn, Rm;
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ARM_ShifterType shift_t;
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uint32_t shift_n; // the shift applied to the value read from Rm
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bool setflags;
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uint32_t carry;
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switch (encoding)
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{
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case eEncodingT1:
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Rd = Rn = Bits32(opcode, 2, 0);
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Rm = Bits32(opcode, 5, 3);
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setflags = !InITBlock();
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shift_t = SRType_LSL;
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shift_n = 0;
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case eEncodingT2:
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Rd = Bits32(opcode, 11, 8);
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Rn = Bits32(opcode, 19, 16);
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Rm = Bits32(opcode, 3, 0);
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setflags = BitIsSet(opcode, 20);
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shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t);
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// if Rd == ‘1111’ && S == ‘1’ then SEE TEQ (register);
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if (Rd == 15 && setflags)
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return EmulateTEQReg(eEncodingT1);
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if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
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return false;
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break;
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case eEncodingA1:
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Rd = Bits32(opcode, 15, 12);
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Rn = Bits32(opcode, 19, 16);
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Rm = Bits32(opcode, 3, 0);
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setflags = BitIsSet(opcode, 20);
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shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t);
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// if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
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// TODO: Emulate SUBS PC, LR and related instructions.
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if (Rd == 15 && setflags)
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return false;
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break;
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default:
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return false;
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}
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// Read the first operand.
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uint32_t val1 = ReadCoreReg(Rn, &success);
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if (!success)
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return false;
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// Read the second operand.
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uint32_t val2 = ReadCoreReg(Rm, &success);
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if (!success)
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return false;
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uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry);
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uint32_t result = val1 ^ shifted;
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EmulateInstruction::Context context;
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context.type = EmulateInstruction::eContextImmediate;
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context.SetNoArgs ();
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if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
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return false;
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}
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return true;
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}
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// Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and
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// writes the result to the destination register. It can optionally update the condition flags based
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// on the result.
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@ -5458,7 +5628,7 @@ EmulateInstructionARM::EmulateORRReg (ARMEncoding encoding)
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return false;
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uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry);
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uint32_t result = val1 & shifted;
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uint32_t result = val1 | shifted;
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EmulateInstruction::Context context;
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context.type = EmulateInstruction::eContextImmediate;
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@ -5470,6 +5640,135 @@ EmulateInstructionARM::EmulateORRReg (ARMEncoding encoding)
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return true;
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}
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// Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an
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// immediate value. It updates the condition flags based on the result, and discards the result.
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bool
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EmulateInstructionARM::EmulateTEQImm (ARMEncoding encoding)
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{
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#if 0
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// ARM pseudo code...
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if ConditionPassed() then
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EncodingSpecificOperations();
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result = R[n] EOR imm32;
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APSR.N = result<31>;
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APSR.Z = IsZeroBit(result);
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APSR.C = carry;
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// APSR.V unchanged
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#endif
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bool success = false;
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const uint32_t opcode = OpcodeAsUnsigned (&success);
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if (!success)
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return false;
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if (ConditionPassed())
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{
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uint32_t Rn;
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uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn
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uint32_t carry; // the carry bit after ARM/Thumb Expand operation
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switch (encoding)
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{
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case eEncodingT1:
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Rn = Bits32(opcode, 19, 16);
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imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
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if (BadReg(Rn))
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return false;
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break;
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case eEncodingA1:
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Rn = Bits32(opcode, 19, 16);
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imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
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break;
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default:
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return false;
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}
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// Read the first operand.
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uint32_t val1 = ReadCoreReg(Rn, &success);
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if (!success)
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return false;
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uint32_t result = val1 ^ imm32;
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EmulateInstruction::Context context;
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context.type = EmulateInstruction::eContextImmediate;
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context.SetNoArgs ();
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if (!WriteFlags(context, result, carry))
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return false;
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}
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return true;
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}
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// Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an
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// optionally-shifted register value. It updates the condition flags based on the result, and discards
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// the result.
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bool
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EmulateInstructionARM::EmulateTEQReg (ARMEncoding encoding)
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{
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#if 0
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// ARM pseudo code...
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if ConditionPassed() then
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EncodingSpecificOperations();
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(shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
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result = R[n] EOR shifted;
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APSR.N = result<31>;
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APSR.Z = IsZeroBit(result);
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APSR.C = carry;
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// APSR.V unchanged
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#endif
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bool success = false;
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const uint32_t opcode = OpcodeAsUnsigned (&success);
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if (!success)
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return false;
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if (ConditionPassed())
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{
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uint32_t Rn, Rm;
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ARM_ShifterType shift_t;
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uint32_t shift_n; // the shift applied to the value read from Rm
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uint32_t carry;
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switch (encoding)
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{
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case eEncodingT1:
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Rn = Bits32(opcode, 19, 16);
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Rm = Bits32(opcode, 3, 0);
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shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t);
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if (BadReg(Rn) || BadReg(Rm))
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return false;
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break;
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case eEncodingA1:
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Rn = Bits32(opcode, 19, 16);
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Rm = Bits32(opcode, 3, 0);
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shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t);
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break;
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default:
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return false;
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}
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// Read the first operand.
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uint32_t val1 = ReadCoreReg(Rn, &success);
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if (!success)
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return false;
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// Read the second operand.
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uint32_t val2 = ReadCoreReg(Rm, &success);
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if (!success)
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return false;
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uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry);
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uint32_t result = val1 ^ shifted;
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EmulateInstruction::Context context;
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context.type = EmulateInstruction::eContextImmediate;
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context.SetNoArgs ();
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if (!WriteFlags(context, result, carry))
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return false;
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}
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return true;
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}
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// Test (immediate) performs a bitwise AND operation on a register value and an immediate value.
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// It updates the condition flags based on the result, and discards the result.
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bool
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@ -5676,10 +5975,18 @@ EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode)
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{ 0x0fe00000, 0x02000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #const"},
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// and (register)
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{ 0x0fe00010, 0x00000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
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// eor (immediate)
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{ 0x0fe00000, 0x02200000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #const"},
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// eor (register)
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{ 0x0fe00010, 0x00200000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
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// orr (immediate)
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{ 0x0fe00000, 0x03800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #const"},
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// orr (register)
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{ 0x0fe00010, 0x01800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
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// teq (immediate)
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{ 0x0ff0f000, 0x03300000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq<c> <Rn>, #const"},
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// teq (register)
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{ 0x0ff0f010, 0x01300000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"},
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// tst (immediate)
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{ 0x0ff0f000, 0x03100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tst<c> <Rn>, #const"},
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// tst (register)
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@ -5837,13 +6144,22 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode)
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// and (register)
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{ 0xffffffc0, 0x00004000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateANDReg, "ands|and<c> <Rdn>, <Rm>"},
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{ 0xffe08000, 0xea000000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
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// eor (immediate)
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{ 0xfbe08000, 0xf0800000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #<const>"},
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// eor (register)
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{ 0xffffffc0, 0x00004040, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateEORReg, "eors|eor<c> <Rdn>, <Rm>"},
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{ 0xffe08000, 0xea800000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
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// orr (immediate)
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{ 0xfbe08000, 0xf0400000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #<const>"},
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// orr (register)
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{ 0xffffffc0, 0x00004300, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateORRReg, "orrs|orr<c> <Rdn>, <Rm>"},
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{ 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
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// teq (immediate)
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{ 0xfbf08f00, 0xf0900f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq<c> <Rn>, #<const>"},
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// teq (register)
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{ 0xfff08f00, 0xea900f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"},
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// tst (immediate)
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{ 0xfbf08f00, 0xf0100f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tsts}<c> <Rn>, #<const>"},
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{ 0xfbf08f00, 0xf0100f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tst<c> <Rn>, #<const>"},
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// tst (register)
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{ 0xffffffc0, 0x00004200, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateTSTReg, "tst<c> <Rdn>, <Rm>"},
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{ 0xfff08f00, 0xea100f00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst<c>.w <Rn>, <Rm> {,<shift>}"},
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@ -563,11 +563,11 @@ protected:
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// A8.6.44 EOR (immediate)
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bool
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EmulateEORImmediate (ARMEncoding encoding);
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EmulateEORImm (ARMEncoding encoding);
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// A8.6.45 EOR (register)
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bool
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EmulateEORegister (ARMEncoding encoding);
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EmulateEORReg (ARMEncoding encoding);
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// A8.6.58 LDR (immediate, ARM) - Encoding A1
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bool
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@ -699,11 +699,11 @@ protected:
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// A8.6.227 TEQ (immediate) - Encoding A1
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bool
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EmulateTEQImmediate (ARMEncoding encoding);
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EmulateTEQImm (ARMEncoding encoding);
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// A8.6.228 TEQ (register) - Encoding A1
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bool
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EmulateTEQRegister (ARMEncoding encoding);
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EmulateTEQReg (ARMEncoding encoding);
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// A8.6.230 TST (immediate) - Encoding A1
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bool
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