diff --git a/llvm/lib/Target/SparcV8/Makefile b/llvm/lib/Target/SparcV8/Makefile
index 497d1a52f268..7d61984048e6 100644
--- a/llvm/lib/Target/SparcV8/Makefile
+++ b/llvm/lib/Target/SparcV8/Makefile
@@ -14,7 +14,7 @@ TARGET = SparcV8
 BUILT_SOURCES = SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
                 SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
                 SparcV8GenInstrInfo.inc SparcV8GenAsmWriter.inc \
-                SparcV8GenDAGISel.inc
+                SparcV8GenDAGISel.inc SparcV8GenSubtarget.inc
 
 include $(LEVEL)/Makefile.common
 
diff --git a/llvm/lib/Target/SparcV8/SparcV8.td b/llvm/lib/Target/SparcV8/SparcV8.td
index dabb0dc97606..cd06886e1b71 100644
--- a/llvm/lib/Target/SparcV8/SparcV8.td
+++ b/llvm/lib/Target/SparcV8/SparcV8.td
@@ -16,6 +16,14 @@
 
 include "../Target.td"
 
+//===----------------------------------------------------------------------===//
+// PowerPC Subtarget features.
+//
+ 
+def Feature64Bit     : SubtargetFeature<"64bit", "bool", "Is64Bit",
+                                        "Enable 64-bit instructions">;
+
+
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
@@ -36,6 +44,14 @@ def SparcV8InstrInfo : InstrInfo {
   let TSFlagsShifts = [];
 }
 
+//===----------------------------------------------------------------------===//
+// SPARC processors supported.
+//===----------------------------------------------------------------------===//
+
+def : Processor<"generic", NoItineraries, []>;
+def : Processor<"v8", NoItineraries, []>;
+def : Processor<"v9", NoItineraries, [Feature64Bit]>;
+
 //===----------------------------------------------------------------------===//
 // Declare the target which we are implementing
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp b/llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp
new file mode 100644
index 000000000000..53a7b5bbeb20
--- /dev/null
+++ b/llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp
@@ -0,0 +1,27 @@
+//===- SparcV8Subtarget.cpp - SPARC Subtarget Information -----------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by Chris Lattner and is distributed under the
+// University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the SPARC specific subclass of TargetSubtarget.
+//
+//===----------------------------------------------------------------------===//
+
+#include "SparcV8Subtarget.h"
+#include "SparcV8GenSubtarget.inc"
+using namespace llvm;
+
+SparcV8Subtarget::SparcV8Subtarget(const Module &M, const std::string &FS) {
+  // Determine default and user specified characteristics
+  std::string CPU = "generic";
+
+  // FIXME: autodetect host here!
+  
+  // Parse features string.
+  ParseSubtargetFeatures(FS, CPU);
+
+};
\ No newline at end of file
diff --git a/llvm/lib/Target/SparcV8/SparcV8Subtarget.h b/llvm/lib/Target/SparcV8/SparcV8Subtarget.h
new file mode 100644
index 000000000000..682c99b16a4d
--- /dev/null
+++ b/llvm/lib/Target/SparcV8/SparcV8Subtarget.h
@@ -0,0 +1,38 @@
+//=====-- SparcV8Subtarget.h - Define Subtarget for the SPARC -*- C++ -*--====//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by Chris Lattner and is distributed under the
+// University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the SPARC specific subclass of TargetSubtarget.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SPARC_SUBTARGET_H
+#define SPARC_SUBTARGET_H
+
+#include "llvm/Target/TargetSubtarget.h"
+#include <string>
+
+namespace llvm {
+  class Module;
+  
+class SparcV8Subtarget : public TargetSubtarget {
+  bool Is64Bit;
+public:
+  SparcV8Subtarget(const Module &M, const std::string &FS);
+
+  bool is64Bit() const { return Is64Bit; }
+  
+  /// ParseSubtargetFeatures - Parses features string setting specified 
+  /// subtarget options.  Definition of function is auto generated by tblgen.
+  void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+  
+};
+
+} // end namespace llvm
+
+#endif
diff --git a/llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp b/llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp
index 83cd308327a5..88f88f4acdee 100644
--- a/llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp
+++ b/llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp
@@ -35,6 +35,7 @@ SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
                                            IntrinsicLowering *IL,
                                            const std::string &FS)
   : TargetMachine("SparcV8", IL, false, 4, 4),
+    Subtarget(M, FS),
     FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
 }
 
diff --git a/llvm/lib/Target/SparcV8/SparcV8TargetMachine.h b/llvm/lib/Target/SparcV8/SparcV8TargetMachine.h
index 1f3096be2f6b..09777442b5ac 100644
--- a/llvm/lib/Target/SparcV8/SparcV8TargetMachine.h
+++ b/llvm/lib/Target/SparcV8/SparcV8TargetMachine.h
@@ -18,6 +18,7 @@
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/PassManager.h"
 #include "SparcV8InstrInfo.h"
+#include "SparcV8Subtarget.h"
 
 namespace llvm {
 
@@ -25,6 +26,7 @@ class IntrinsicLowering;
 class Module;
 
 class SparcV8TargetMachine : public TargetMachine {
+  SparcV8Subtarget Subtarget;
   SparcV8InstrInfo InstrInfo;
   TargetFrameInfo FrameInfo;
 public:
@@ -33,6 +35,7 @@ public:
 
   virtual const SparcV8InstrInfo *getInstrInfo() const { return &InstrInfo; }
   virtual const TargetFrameInfo  *getFrameInfo() const { return &FrameInfo; }
+  virtual const TargetSubtarget  *getSubtargetImpl() const{ return &Subtarget; }
   virtual const MRegisterInfo *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }