forked from OSchip/llvm-project
[AMDGPU] Precommit more vccz workaround tests
This commit is contained in:
Jay Foad
parent
0a1d315f9f
commit
e67d8859f2
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@ -163,3 +163,167 @@ body: |
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bb.1:
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...
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---
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# Test vcc definition in a previous basic block.
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# CHECK-LABEL: name: vcc_def_pred
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# CHECK: bb.1:
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# CHECK: S_CBRANCH_VCCZ %bb.2, implicit $vcc
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name: vcc_def_pred
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body: |
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bb.0:
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$vcc = S_MOV_B64 0
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bb.1:
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S_CBRANCH_VCCZ %bb.2, implicit $vcc
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bb.2:
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...
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# Test various ways that the live range of vccz can overlap with the live range
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# of an outstanding smem load.
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---
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# CHECK-LABEL: name: load_wait_def_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: load_wait_def_use
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body: |
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bb.0:
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_WAITCNT 127
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$vcc = S_MOV_B64 0
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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---
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# CHECK-LABEL: name: load_wait_nop_def_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: S_NOP 0
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: load_wait_nop_def_use
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body: |
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bb.0:
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_WAITCNT 127
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S_NOP 0
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$vcc = S_MOV_B64 0
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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---
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# CHECK-LABEL: name: load_def_wait_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: $vcc = S_MOV_B64 $vcc
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: load_def_wait_use
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body: |
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bb.0:
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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$vcc = S_MOV_B64 0
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S_WAITCNT 127
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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# CHECK-LABEL: name: load_def_wait_nop_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: S_NOP 0
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# FIXME should have $vcc = S_MOV_B64 $vcc
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: load_def_wait_nop_use
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body: |
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bb.0:
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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$vcc = S_MOV_B64 0
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S_WAITCNT 127
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S_NOP 0
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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---
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# CHECK-LABEL: name: load_def_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: $vcc = S_MOV_B64 $vcc
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: load_def_use
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body: |
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bb.0:
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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$vcc = S_MOV_B64 0
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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---
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# CHECK-LABEL: name: def_load_wait_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: $vcc = S_MOV_B64 $vcc
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: def_load_wait_use
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body: |
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bb.0:
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$vcc = S_MOV_B64 0
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_WAITCNT 127
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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---
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# CHECK-LABEL: name: def_load_wait_nop_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: S_NOP 0
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# FIXME should have $vcc = S_MOV_B64 $vcc
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: def_load_wait_nop_use
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body: |
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bb.0:
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$vcc = S_MOV_B64 0
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_WAITCNT 127
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S_NOP 0
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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---
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# CHECK-LABEL: name: def_load_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: $vcc = S_MOV_B64 $vcc
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: def_load_use
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body: |
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bb.0:
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$vcc = S_MOV_B64 0
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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