forked from OSchip/llvm-project
Add a separate name field to the Neon intrinsic table.
This is currently the same as a lowercase version of the record name, but it will allow us to have multiple records with the same name, which is needed for intrinsics (e.g., vmul and vmull) that are implemented differently depending on the type. llvm-svn: 120807
This commit is contained in:
Bob Wilson
parent
4fa993fc51
commit
e674f09c1e
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@ -48,7 +48,8 @@ def OP_REV64 : Op;
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def OP_REV32 : Op;
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def OP_REV16 : Op;
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class Inst <string p, string t, Op o> {
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class Inst <string n, string p, string t, Op o> {
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string Name = n;
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string Prototype = p;
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string Types = t;
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Op Operand = o;
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@ -59,9 +60,9 @@ class Inst <string p, string t, Op o> {
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// SInst: Instruction with signed/unsigned suffix (e.g., "s8", "u8", "p8")
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// IInst: Instruction with generic integer suffix (e.g., "i8")
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// WInst: Instruction with only bit size suffix (e.g., "8")
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class SInst<string p, string t> : Inst<p, t, OP_NONE> {}
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class IInst<string p, string t> : Inst<p, t, OP_NONE> {}
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class WInst<string p, string t> : Inst<p, t, OP_NONE> {}
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class SInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
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class IInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
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class WInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
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// prototype: return (arg, arg, ...)
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// v: void
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@ -99,252 +100,266 @@ class WInst<string p, string t> : Inst<p, t, OP_NONE> {}
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////////////////////////////////////////////////////////////////////////////////
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// E.3.1 Addition
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def VADD : Inst<"ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>;
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def VADDL : SInst<"wdd", "csiUcUsUi">;
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def VADDW : SInst<"wwd", "csiUcUsUi">;
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def VHADD : SInst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def VRHADD : SInst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def VQADD : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VADDHN : IInst<"dww", "csiUcUsUi">;
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def VRADDHN : IInst<"dww", "csiUcUsUi">;
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def VADD : Inst<"vadd", "ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>;
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def VADDL : SInst<"vaddl", "wdd", "csiUcUsUi">;
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def VADDW : SInst<"vaddw", "wwd", "csiUcUsUi">;
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def VHADD : SInst<"vhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def VRHADD : SInst<"vrhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def VQADD : SInst<"vqadd", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VADDHN : IInst<"vaddhn", "dww", "csiUcUsUi">;
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def VRADDHN : IInst<"vraddhn", "dww", "csiUcUsUi">;
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////////////////////////////////////////////////////////////////////////////////
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// E.3.2 Multiplication
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def VMUL : Inst<"ddd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_MUL>;
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def VMLA : Inst<"dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>;
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def VMLAL : SInst<"wwdd", "csiUcUsUi">;
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def VMLS : Inst<"dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>;
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def VMLSL : SInst<"wwdd", "csiUcUsUi">;
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def VQDMULH : SInst<"ddd", "siQsQi">;
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def VQRDMULH : SInst<"ddd", "siQsQi">;
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def VQDMLAL : SInst<"wwdd", "si">;
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def VQDMLSL : SInst<"wwdd", "si">;
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def VMULL : SInst<"wdd", "csiUcUsUiPc">;
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def VQDMULL : SInst<"wdd", "si">;
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def VMUL : Inst<"vmul", "ddd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_MUL>;
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def VMLA : Inst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>;
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def VMLAL : SInst<"vmlal", "wwdd", "csiUcUsUi">;
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def VMLS : Inst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>;
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def VMLSL : SInst<"vmlsl", "wwdd", "csiUcUsUi">;
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def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">;
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def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">;
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def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">;
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def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">;
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def VMULL : SInst<"vmull", "wdd", "csiUcUsUiPc">;
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def VQDMULL : SInst<"vqdmull", "wdd", "si">;
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////////////////////////////////////////////////////////////////////////////////
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// E.3.3 Subtraction
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def VSUB : Inst<"ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>;
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def VSUBL : SInst<"wdd", "csiUcUsUi">;
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def VSUBW : SInst<"wwd", "csiUcUsUi">;
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def VQSUB : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VHSUB : SInst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def VSUBHN : IInst<"dww", "csiUcUsUi">;
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def VRSUBHN : IInst<"dww", "csiUcUsUi">;
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def VSUB : Inst<"vsub", "ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>;
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def VSUBL : SInst<"vsubl", "wdd", "csiUcUsUi">;
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def VSUBW : SInst<"vsubw", "wwd", "csiUcUsUi">;
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def VQSUB : SInst<"vqsub", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VHSUB : SInst<"vhsub", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def VSUBHN : IInst<"vsubhn", "dww", "csiUcUsUi">;
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def VRSUBHN : IInst<"vrsubhn", "dww", "csiUcUsUi">;
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////////////////////////////////////////////////////////////////////////////////
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// E.3.4 Comparison
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def VCEQ : Inst<"udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>;
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def VCGE : Inst<"udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;
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def VCLE : Inst<"udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>;
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def VCGT : Inst<"udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>;
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def VCLT : Inst<"udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>;
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def VCAGE : IInst<"udd", "fQf">;
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def VCALE : IInst<"udd", "fQf">;
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def VCAGT : IInst<"udd", "fQf">;
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def VCALT : IInst<"udd", "fQf">;
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def VTST : WInst<"udd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc">;
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def VCEQ : Inst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>;
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def VCGE : Inst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;
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def VCLE : Inst<"vcle", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>;
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def VCGT : Inst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>;
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def VCLT : Inst<"vclt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>;
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def VCAGE : IInst<"vcage", "udd", "fQf">;
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def VCALE : IInst<"vcale", "udd", "fQf">;
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def VCAGT : IInst<"vcagt", "udd", "fQf">;
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def VCALT : IInst<"vcalt", "udd", "fQf">;
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def VTST : WInst<"vtst", "udd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc">;
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////////////////////////////////////////////////////////////////////////////////
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// E.3.5 Absolute Difference
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def VABD : SInst<"ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
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def VABDL : SInst<"wdd", "csiUcUsUi">;
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def VABA : SInst<"dddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def VABAL : SInst<"wwdd", "csiUcUsUi">;
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def VABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
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def VABDL : SInst<"vabdl", "wdd", "csiUcUsUi">;
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def VABA : SInst<"vaba", "dddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def VABAL : SInst<"vabal", "wwdd", "csiUcUsUi">;
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////////////////////////////////////////////////////////////////////////////////
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// E.3.6 Max/Min
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def VMAX : SInst<"ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
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def VMIN : SInst<"ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
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def VMAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
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def VMIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
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////////////////////////////////////////////////////////////////////////////////
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// E.3.7 Pairdise Addition
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def VPADD : IInst<"ddd", "csiUcUsUif">;
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def VPADDL : SInst<"nd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def VPADAL : SInst<"nnd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def VPADD : IInst<"vpadd", "ddd", "csiUcUsUif">;
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def VPADDL : SInst<"vpaddl", "nd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def VPADAL : SInst<"vpadal", "nnd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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////////////////////////////////////////////////////////////////////////////////
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// E.3.8-9 Folding Max/Min
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def VPMAX : SInst<"ddd", "csiUcUsUif">;
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def VPMIN : SInst<"ddd", "csiUcUsUif">;
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def VPMAX : SInst<"vpmax", "ddd", "csiUcUsUif">;
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def VPMIN : SInst<"vpmin", "ddd", "csiUcUsUif">;
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////////////////////////////////////////////////////////////////////////////////
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// E.3.10 Reciprocal/Sqrt
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def VRECPS : IInst<"ddd", "fQf">;
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def VRSQRTS : IInst<"ddd", "fQf">;
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def VRECPS : IInst<"vrecps", "ddd", "fQf">;
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def VRSQRTS : IInst<"vrsqrts", "ddd", "fQf">;
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////////////////////////////////////////////////////////////////////////////////
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// E.3.11 Shifts by signed variable
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def VSHL : SInst<"ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VQSHL : SInst<"ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VRSHL : SInst<"ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VQRSHL : SInst<"ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VSHL : SInst<"vshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VQSHL : SInst<"vqshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VRSHL : SInst<"vrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VQRSHL : SInst<"vqrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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////////////////////////////////////////////////////////////////////////////////
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// E.3.12 Shifts by constant
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let isShift = 1 in {
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def VSHR_N : SInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VSHL_N : IInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VRSHR_N : SInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VSRA_N : SInst<"dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VRSRA_N : SInst<"dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VQSHL_N : SInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VQSHLU_N : SInst<"udi", "csilQcQsQiQl">;
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def VSHRN_N : IInst<"hki", "silUsUiUl">;
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def VQSHRUN_N : SInst<"eki", "sil">;
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def VQRSHRUN_N : SInst<"eki", "sil">;
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def VQSHRN_N : SInst<"hki", "silUsUiUl">;
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def VRSHRN_N : IInst<"hki", "silUsUiUl">;
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def VQRSHRN_N : SInst<"hki", "silUsUiUl">;
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def VSHLL_N : SInst<"wdi", "csiUcUsUi">;
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def VSHR_N : SInst<"vshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VSHL_N : IInst<"vshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VRSHR_N : SInst<"vrshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VSRA_N : SInst<"vsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VRSRA_N : SInst<"vrsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VQSHL_N : SInst<"vqshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
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def VQSHLU_N : SInst<"vqshlu_n", "udi", "csilQcQsQiQl">;
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def VSHRN_N : IInst<"vshrn_n", "hki", "silUsUiUl">;
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def VQSHRUN_N : SInst<"vqshrun_n", "eki", "sil">;
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def VQRSHRUN_N : SInst<"vqrshrun_n", "eki", "sil">;
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def VQSHRN_N : SInst<"vqshrn_n", "hki", "silUsUiUl">;
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def VRSHRN_N : IInst<"vrshrn_n", "hki", "silUsUiUl">;
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def VQRSHRN_N : SInst<"vqrshrn_n", "hki", "silUsUiUl">;
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def VSHLL_N : SInst<"vshll_n", "wdi", "csiUcUsUi">;
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////////////////////////////////////////////////////////////////////////////////
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// E.3.13 Shifts with insert
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def VSRI_N : WInst<"dddi", "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
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def VSLI_N : WInst<"dddi", "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
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def VSRI_N : WInst<"vsri_n", "dddi",
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"csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
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def VSLI_N : WInst<"vsli_n", "dddi",
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"csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
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}
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////////////////////////////////////////////////////////////////////////////////
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// E.3.14 Loads and stores of a single vector
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def VLD1 : WInst<"dc", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VLD1_LANE : WInst<"dcdi", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VLD1_DUP : WInst<"dc", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VST1 : WInst<"vpd", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VST1_LANE : WInst<"vpdi", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VLD1 : WInst<"vld1", "dc",
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"QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VLD1_LANE : WInst<"vld1_lane", "dcdi",
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"QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VLD1_DUP : WInst<"vld1_dup", "dc",
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"QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VST1 : WInst<"vst1", "vpd",
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"QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VST1_LANE : WInst<"vst1_lane", "vpdi",
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"QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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////////////////////////////////////////////////////////////////////////////////
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// E.3.15 Loads and stores of an N-element structure
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def VLD2 : WInst<"2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VLD3 : WInst<"3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VLD4 : WInst<"4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VLD2_DUP : WInst<"2c", "UcUsUiUlcsilhfPcPs">;
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def VLD3_DUP : WInst<"3c", "UcUsUiUlcsilhfPcPs">;
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def VLD4_DUP : WInst<"4c", "UcUsUiUlcsilhfPcPs">;
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def VLD2_LANE : WInst<"2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
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def VLD3_LANE : WInst<"3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
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def VLD4_LANE : WInst<"4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
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def VST2 : WInst<"vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VST3 : WInst<"vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VST4 : WInst<"vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
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def VST2_LANE : WInst<"vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
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def VST3_LANE : WInst<"vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
|
||||
def VST4_LANE : WInst<"vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
|
||||
def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
|
||||
def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
|
||||
def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
|
||||
def VLD2_DUP : WInst<"vld2_dup", "2c", "UcUsUiUlcsilhfPcPs">;
|
||||
def VLD3_DUP : WInst<"vld3_dup", "3c", "UcUsUiUlcsilhfPcPs">;
|
||||
def VLD4_DUP : WInst<"vld4_dup", "4c", "UcUsUiUlcsilhfPcPs">;
|
||||
def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
|
||||
def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
|
||||
def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
|
||||
def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
|
||||
def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
|
||||
def VST4 : WInst<"vst4", "vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
|
||||
def VST2_LANE : WInst<"vst2_lane", "vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
|
||||
def VST3_LANE : WInst<"vst3_lane", "vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
|
||||
def VST4_LANE : WInst<"vst4_lane", "vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.16 Extract lanes from a vector
|
||||
def VGET_LANE : IInst<"sdi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
|
||||
def VGET_LANE : IInst<"vget_lane", "sdi",
|
||||
"UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.17 Set lanes within a vector
|
||||
def VSET_LANE : IInst<"dsdi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
|
||||
def VSET_LANE : IInst<"vset_lane", "dsdi",
|
||||
"UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.18 Initialize a vector from bit pattern
|
||||
def VCREATE: Inst<"dl", "csihfUcUsUiUlPcPsl", OP_CAST>;
|
||||
def VCREATE: Inst<"vcreate", "dl", "csihfUcUsUiUlPcPsl", OP_CAST>;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.19 Set all lanes to same value
|
||||
def VDUP_N : Inst<"ds", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>;
|
||||
def VMOV_N : Inst<"ds", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>;
|
||||
def VDUP_LANE : WInst<"dgi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
|
||||
def VDUP_N : Inst<"vdup_n", "ds",
|
||||
"UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>;
|
||||
def VMOV_N : Inst<"vmov_n", "ds",
|
||||
"UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>;
|
||||
def VDUP_LANE : WInst<"vdup_lane", "dgi",
|
||||
"UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.20 Combining vectors
|
||||
def VCOMBINE : Inst<"kdd", "csilhfUcUsUiUlPcPs", OP_CONC>;
|
||||
def VCOMBINE : Inst<"vcombine", "kdd", "csilhfUcUsUiUlPcPs", OP_CONC>;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.21 Splitting vectors
|
||||
def VGET_HIGH : Inst<"dk", "csilhfUcUsUiUlPcPs", OP_HI>;
|
||||
def VGET_LOW : Inst<"dk", "csilhfUcUsUiUlPcPs", OP_LO>;
|
||||
def VGET_HIGH : Inst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>;
|
||||
def VGET_LOW : Inst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.22 Converting vectors
|
||||
def VCVT_S32 : SInst<"xd", "fQf">;
|
||||
def VCVT_U32 : SInst<"ud", "fQf">;
|
||||
def VCVT_F16 : SInst<"hk", "f">;
|
||||
def VCVT_N_S32 : SInst<"xdi", "fQf">;
|
||||
def VCVT_N_U32 : SInst<"udi", "fQf">;
|
||||
def VCVT_F32 : SInst<"fd", "iUiQiQUi">;
|
||||
def VCVT_F32_F16 : SInst<"kh", "f">;
|
||||
def VCVT_N_F32 : SInst<"fdi", "iUiQiQUi">;
|
||||
def VMOVN : IInst<"hk", "silUsUiUl">;
|
||||
def VMOVL : SInst<"wd", "csiUcUsUi">;
|
||||
def VQMOVN : SInst<"hk", "silUsUiUl">;
|
||||
def VQMOVUN : SInst<"ek", "sil">;
|
||||
def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">;
|
||||
def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">;
|
||||
def VCVT_F16 : SInst<"vcvt_f16", "hk", "f">;
|
||||
def VCVT_N_S32 : SInst<"vcvt_n_s32", "xdi", "fQf">;
|
||||
def VCVT_N_U32 : SInst<"vcvt_n_u32", "udi", "fQf">;
|
||||
def VCVT_F32 : SInst<"vcvt_f32", "fd", "iUiQiQUi">;
|
||||
def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "kh", "f">;
|
||||
def VCVT_N_F32 : SInst<"vcvt_n_f32", "fdi", "iUiQiQUi">;
|
||||
def VMOVN : IInst<"vmovn", "hk", "silUsUiUl">;
|
||||
def VMOVL : SInst<"vmovl", "wd", "csiUcUsUi">;
|
||||
def VQMOVN : SInst<"vqmovn", "hk", "silUsUiUl">;
|
||||
def VQMOVUN : SInst<"vqmovun", "ek", "sil">;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.23-24 Table lookup, Extended table lookup
|
||||
def VTBL1 : WInst<"ddt", "UccPc">;
|
||||
def VTBL2 : WInst<"d2t", "UccPc">;
|
||||
def VTBL3 : WInst<"d3t", "UccPc">;
|
||||
def VTBL4 : WInst<"d4t", "UccPc">;
|
||||
def VTBX1 : WInst<"dddt", "UccPc">;
|
||||
def VTBX2 : WInst<"dd2t", "UccPc">;
|
||||
def VTBX3 : WInst<"dd3t", "UccPc">;
|
||||
def VTBX4 : WInst<"dd4t", "UccPc">;
|
||||
def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">;
|
||||
def VTBL2 : WInst<"vtbl2", "d2t", "UccPc">;
|
||||
def VTBL3 : WInst<"vtbl3", "d3t", "UccPc">;
|
||||
def VTBL4 : WInst<"vtbl4", "d4t", "UccPc">;
|
||||
def VTBX1 : WInst<"vtbx1", "dddt", "UccPc">;
|
||||
def VTBX2 : WInst<"vtbx2", "dd2t", "UccPc">;
|
||||
def VTBX3 : WInst<"vtbx3", "dd3t", "UccPc">;
|
||||
def VTBX4 : WInst<"vtbx4", "dd4t", "UccPc">;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.25 Operations with a scalar value
|
||||
def VMLA_LANE : Inst<"ddddi", "siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
|
||||
def VMLAL_LANE : SInst<"wwddi", "siUsUi">;
|
||||
def VQDMLAL_LANE : SInst<"wwddi", "si">;
|
||||
def VMLS_LANE : Inst<"ddddi", "siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
|
||||
def VMLSL_LANE : SInst<"wwddi", "siUsUi">;
|
||||
def VQDMLSL_LANE : SInst<"wwddi", "si">;
|
||||
def VMUL_N : Inst<"dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>;
|
||||
def VMUL_LANE : Inst<"dddi", "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>;
|
||||
def VMULL_N : SInst<"wda", "siUsUi">;
|
||||
def VMULL_LANE : SInst<"wddi", "siUsUi">;
|
||||
def VQDMULL_N : SInst<"wda", "si">;
|
||||
def VQDMULL_LANE : SInst<"wddi", "si">;
|
||||
def VQDMULH_N : SInst<"dda", "siQsQi">;
|
||||
def VQDMULH_LANE : SInst<"dddi", "siQsQi">;
|
||||
def VQRDMULH_N : SInst<"dda", "siQsQi">;
|
||||
def VQRDMULH_LANE : SInst<"dddi", "siQsQi">;
|
||||
def VMLA_N : Inst<"ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>;
|
||||
def VMLAL_N : SInst<"wwda", "siUsUi">;
|
||||
def VQDMLAL_N : SInst<"wwda", "si">;
|
||||
def VMLS_N : Inst<"ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>;
|
||||
def VMLSL_N : SInst<"wwda", "siUsUi">;
|
||||
def VQDMLSL_N : SInst<"wwda", "si">;
|
||||
def VMLA_LANE : Inst<"vmla_lane", "ddddi", "siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
|
||||
def VMLAL_LANE : SInst<"vmlal_lane", "wwddi", "siUsUi">;
|
||||
def VQDMLAL_LANE : SInst<"vqdmlal_lane", "wwddi", "si">;
|
||||
def VMLS_LANE : Inst<"vmls_lane", "ddddi", "siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
|
||||
def VMLSL_LANE : SInst<"vmlsl_lane", "wwddi", "siUsUi">;
|
||||
def VQDMLSL_LANE : SInst<"vqdmlsl_lane", "wwddi", "si">;
|
||||
def VMUL_N : Inst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>;
|
||||
def VMUL_LANE : Inst<"vmul_lane", "dddi", "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>;
|
||||
def VMULL_N : SInst<"vmull_n", "wda", "siUsUi">;
|
||||
def VMULL_LANE : SInst<"vmull_lane", "wddi", "siUsUi">;
|
||||
def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">;
|
||||
def VQDMULL_LANE : SInst<"vqdmull_lane", "wddi", "si">;
|
||||
def VQDMULH_N : SInst<"vqdmulh_n", "dda", "siQsQi">;
|
||||
def VQDMULH_LANE : SInst<"vqdmulh_lane", "dddi", "siQsQi">;
|
||||
def VQRDMULH_N : SInst<"vqrdmulh_n", "dda", "siQsQi">;
|
||||
def VQRDMULH_LANE : SInst<"vqrdmulh_lane", "dddi", "siQsQi">;
|
||||
def VMLA_N : Inst<"vmla_n", "ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>;
|
||||
def VMLAL_N : SInst<"vmlal_n", "wwda", "siUsUi">;
|
||||
def VQDMLAL_N : SInst<"vqdmlal_n", "wwda", "si">;
|
||||
def VMLS_N : Inst<"vmls_n", "ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>;
|
||||
def VMLSL_N : SInst<"vmlsl_n", "wwda", "siUsUi">;
|
||||
def VQDMLSL_N : SInst<"vqdmlsl_n", "wwda", "si">;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.26 Vector Extract
|
||||
def VEXT : WInst<"dddi", "cUcPcsUsPsiUilUlQcQUcQPcQsQUsQPsQiQUiQlQUl">;
|
||||
def VEXT : WInst<"vext", "dddi", "cUcPcsUsPsiUilUlQcQUcQPcQsQUsQPsQiQUiQlQUl">;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.27 Reverse vector elements (sdap endianness)
|
||||
def VREV64 : Inst<"dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf", OP_REV64>;
|
||||
def VREV32 : Inst<"dd", "csUcUsPcQcQsQUcQUsQPc", OP_REV32>;
|
||||
def VREV16 : Inst<"dd", "cUcPcQcQUcQPc", OP_REV16>;
|
||||
def VREV64 : Inst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf",
|
||||
OP_REV64>;
|
||||
def VREV32 : Inst<"vrev32", "dd", "csUcUsPcQcQsQUcQUsQPc", OP_REV32>;
|
||||
def VREV16 : Inst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.28 Other single operand arithmetic
|
||||
def VABS : SInst<"dd", "csifQcQsQiQf">;
|
||||
def VQABS : SInst<"dd", "csiQcQsQi">;
|
||||
def VNEG : Inst<"dd", "csifQcQsQiQf", OP_NEG>;
|
||||
def VQNEG : SInst<"dd", "csiQcQsQi">;
|
||||
def VCLS : SInst<"dd", "csiQcQsQi">;
|
||||
def VCLZ : IInst<"dd", "csiUcUsUiQcQsQiQUcQUsQUi">;
|
||||
def VCNT : WInst<"dd", "UccPcQUcQcQPc">;
|
||||
def VRECPE : SInst<"dd", "fUiQfQUi">;
|
||||
def VRSQRTE : SInst<"dd", "fUiQfQUi">;
|
||||
def VABS : SInst<"vabs", "dd", "csifQcQsQiQf">;
|
||||
def VQABS : SInst<"vqabs", "dd", "csiQcQsQi">;
|
||||
def VNEG : Inst<"vneg", "dd", "csifQcQsQiQf", OP_NEG>;
|
||||
def VQNEG : SInst<"vqneg", "dd", "csiQcQsQi">;
|
||||
def VCLS : SInst<"vcls", "dd", "csiQcQsQi">;
|
||||
def VCLZ : IInst<"vclz", "dd", "csiUcUsUiQcQsQiQUcQUsQUi">;
|
||||
def VCNT : WInst<"vcnt", "dd", "UccPcQUcQcQPc">;
|
||||
def VRECPE : SInst<"vrecpe", "dd", "fUiQfQUi">;
|
||||
def VRSQRTE : SInst<"vrsqrte", "dd", "fUiQfQUi">;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.29 Logical operations
|
||||
def VMVN : Inst<"dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>;
|
||||
def VAND : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>;
|
||||
def VORR : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>;
|
||||
def VEOR : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>;
|
||||
def VBIC : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>;
|
||||
def VORN : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>;
|
||||
def VBSL : Inst<"dudd", "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs", OP_SEL>;
|
||||
def VMVN : Inst<"vmvn", "dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>;
|
||||
def VAND : Inst<"vand", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>;
|
||||
def VORR : Inst<"vorr", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>;
|
||||
def VEOR : Inst<"veor", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>;
|
||||
def VBIC : Inst<"vbic", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>;
|
||||
def VORN : Inst<"vorn", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>;
|
||||
def VBSL : Inst<"vbsl", "dudd",
|
||||
"csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs", OP_SEL>;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.30 Transposition operations
|
||||
def VTRN: WInst<"2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
|
||||
def VZIP: WInst<"2dd", "csUcUsfPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
|
||||
def VUZP: WInst<"2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
|
||||
def VTRN: WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
|
||||
def VZIP: WInst<"vzip", "2dd", "csUcUsfPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
|
||||
def VUZP: WInst<"vuzp", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.31 Vector reinterpret cast operations
|
||||
|
|
|
|||
Loading…
Reference in New Issue