maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions 

Differential Revision: http://reviews.llvm.org/D18352

llvm-svn: 270030
This commit is contained in:
Zlatko Buljan 2016-05-19 07:31:28 +00:00
parent 5dbcd3bd07
commit e663e34e79
10 changed files with 111 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -1566,6 +1566,10 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
case Mips::BLTZAL_MM:
case Mips::BC1F_MM:
case Mips::BC1T_MM:
case Mips::BC1EQZC_MMR6:
case Mips::BC1NEZC_MMR6:
case Mips::BC2EQZC_MMR6:
case Mips::BC2NEZC_MMR6:
assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
Offset = Inst.getOperand(1);
if (!Offset.isImm())

13
llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td
View File

@ -1004,3 +1004,16 @@ class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst {
let Inst{25-21} = rs;
let Inst{20-0} = offset;
}
class POOL32I_BRANCH_COP_1_2_FM_MMR6<string instr_asm, bits<5> funct>
: MMR6Arch<instr_asm> {
bits<5> rt;
bits<16> offset;
bits<32> Inst;
let Inst{31-26} = 0b010000;
let Inst{25-21} = funct;
let Inst{20-16} = rt;
let Inst{15-0} = offset;
}

32
llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
View File

@ -208,6 +208,10 @@ class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>;
class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>;
class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>;
class BC1NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1nezc", 0b01001>;
class BC2EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2eqzc", 0b01010>;
class BC2NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2nezc", 0b01011>;
class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
RegisterOperand GPROpnd>
@ -1169,6 +1173,26 @@ class BNEZC_MMR6_DESC
: CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>,
MMR6Arch<"bnezc">;
class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset),
!strconcat(opstr, "\t$rt, $offset"), [], II_BC1CCZ, FrmI>,
HARDFLOAT, BRANCH_DESC_BASE {
list<Register> Defs = [AT];
}
class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">;
class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">;
class BRANCH_COP2_MMR6_DESC_BASE<string opstr> : BRANCH_DESC_BASE {
dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset);
dag OutOperandList = (outs);
string AsmString = !strconcat(opstr, "\t$rt, $offset");
list<Register> Defs = [AT];
}
class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc">;
class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc">;
//===----------------------------------------------------------------------===//
//
// Instruction Definitions
@ -1474,6 +1498,14 @@ def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
ISA_MICROMIPS32R6;
def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6;
def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6;
def BC1EQZC_MMR6 : R6MMR6Rel, BC1EQZC_MMR6_DESC, BC1EQZC_MMR6_ENC,
ISA_MICROMIPS32R6;
def BC1NEZC_MMR6 : R6MMR6Rel, BC1NEZC_MMR6_DESC, BC1NEZC_MMR6_ENC,
ISA_MICROMIPS32R6;
def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2EQZC_MMR6_ENC, BC2EQZC_MMR6_DESC,
ISA_MICROMIPS32R6;
def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
ISA_MICROMIPS32R6;
}
def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6;

10
llvm/lib/Target/Mips/Mips32r6InstrInfo.td
View File

@ -715,10 +715,12 @@ def AUI : R6MMR6Rel, AUI_ENC, AUI_DESC, ISA_MIPS32R6;
def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6;
def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6;
def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT;
def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT;
def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT;
def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT;
def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
}
def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6;
def BEQC : R6MMR6Rel, BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;

4
llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt
View File

@ -315,3 +315,7 @@
0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
0x22 0x04 0x10 0x08 # CHECK: lwp $16, 8($4)
0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4)
0x41 0x1f 0x00 0x02 # CHECK: bc1eqzc $f31, 4
0x41 0x3f 0x00 0x02 # CHECK: bc1nezc $f31, 4
0x41 0x5f 0x00 0x04 # CHECK: bc2eqzc $31, 8
0x41 0x7f 0x00 0x04 # CHECK: bc2nezc $31, 8

4
llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt
View File

@ -269,3 +269,7 @@
0x58 0xa6 0x20 0x10 # CHECK: dsllv $4, $5, $6
0x58 0x85 0x28 0x80 # CHECK: dsra $4, $5, 5
0x58 0xa6 0x20 0x90 # CHECK: dsrav $4, $5, $6
0x41 0x1f 0x00 0x02 # CHECK: bc1eqzc $f31, 4
0x41 0x3f 0x00 0x02 # CHECK: bc1nezc $f31, 4
0x41 0x5f 0x00 0x04 # CHECK: bc2eqzc $31, 8
0x41 0x7f 0x00 0x04 # CHECK: bc2nezc $31, 8

20
llvm/test/MC/Mips/micromips32r6/invalid.s
View File

@ -214,3 +214,23 @@
swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
# bposge32 is microMIPS DSP instruction
bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc1eqzc $f32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc1eqzc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1eqzc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc1eqzc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1eqzc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc1nezc $f32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc1nezc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1nezc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc1nezc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1nezc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2eqzc $32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc2eqzc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2eqzc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2eqzc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2eqzc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2nezc $32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc2nezc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2nezc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2nezc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2nezc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range

4
llvm/test/MC/Mips/micromips32r6/valid.s
View File

@ -335,3 +335,7 @@
srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40]
lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
swp $16, 8($4) # CHECK: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08]
bc1eqzc $f31, 4 # CHECK: bc1eqzc $f31, 4 # encoding: [0x41,0x1f,0x00,0x02]
bc1nezc $f31, 4 # CHECK: bc1nezc $f31, 4 # encoding: [0x41,0x3f,0x00,0x02]
bc2eqzc $31, 8 # CHECK: bc2eqzc $31, 8 # encoding: [0x41,0x5f,0x00,0x04]
bc2nezc $31, 8 # CHECK: bc2nezc $31, 8 # encoding: [0x41,0x7f,0x00,0x04]

20
llvm/test/MC/Mips/micromips64r6/invalid.s
View File

@ -254,3 +254,23 @@
dsra32 $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
# bposge32 is microMIPS DSP instruction
bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc1eqzc $f32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc1eqzc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1eqzc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc1eqzc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1eqzc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc1nezc $f32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc1nezc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1nezc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc1nezc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1nezc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2eqzc $32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc2eqzc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2eqzc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2eqzc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2eqzc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2nezc $32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc2nezc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2nezc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2nezc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2nezc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range

4
llvm/test/MC/Mips/micromips64r6/valid.s
View File

@ -273,5 +273,9 @@ a:
dsra $4, $5, 5 # CHECK: dsra $4, $5, 5 # encoding: [0x58,0x85,0x28,0x80]
dsra32 $4, $5, 5 # CHECK: dsra32 $4, $5, 5 # encoding: [0x58,0x85,0x28,0x84]
dsrav $4, $5, $6 # CHECK: dsrav $4, $5, $6 # encoding: [0x58,0xa6,0x20,0x90]
bc1eqzc $f31, 4 # CHECK: bc1eqzc $f31, 4 # encoding: [0x41,0x1f,0x00,0x02]
bc1nezc $f31, 4 # CHECK: bc1nezc $f31, 4 # encoding: [0x41,0x3f,0x00,0x02]
bc2eqzc $31, 8 # CHECK: bc2eqzc $31, 8 # encoding: [0x41,0x5f,0x00,0x04]
bc2nezc $31, 8 # CHECK: bc2nezc $31, 8 # encoding: [0x41,0x7f,0x00,0x04]
1: