forked from OSchip/llvm-project
[mips] MIPS32/64 itineraries
Itineraries for some pre MIPSR6 and EVA instructions. Some pseudo expanded instructions are marked as having no scheduling info. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D20418 llvm-svn: 272648
This commit is contained in:
Simon Dardis
parent
435a653437
commit
e661e528db
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@ -635,7 +635,7 @@ def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIM16Alu>, cbranch16;
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// Purpose: Breakpoint
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// To cause a Breakpoint exception.
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def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>;
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def Break16: FRRBreakNull16_ins<"break 0", IIM16Alu>;
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//
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// Format: BTEQZ offset MIPS16e
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// Purpose: Branch on T Equal to Zero (Extended)
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@ -82,7 +82,7 @@ let usesCustomInserter = 1 in {
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}
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/// Pseudo instructions for loading and storing accumulator registers.
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let isPseudo = 1, isCodeGenOnly = 1 in {
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let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
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def LOAD_ACC128 : Load<"", ACC128>;
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def STORE_ACC128 : Store<"", ACC128>;
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}
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@ -92,8 +92,8 @@ let isPseudo = 1, isCodeGenOnly = 1 in {
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "Mips64" in {
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/// Arithmetic Instructions (ALU Immediate)
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def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
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ISA_MIPS3_NOT_32R6_64R6;
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def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd, II_DADDI>,
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ADDI_FM<0x18>, ISA_MIPS3_NOT_32R6_64R6;
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let AdditionalPredicates = [NotInMicroMips] in {
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def DADDiu : StdMMR6Rel, ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
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II_DADDIU, immSExt16, add>,
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@ -276,8 +276,10 @@ def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
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}
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/// Count Leading
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def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
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def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
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def DCLZ : CountLeading0<"dclz", GPR64Opnd, II_DCLZ>, CLO_FM<0x24>,
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ISA_MIPS64_NOT_64R6;
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def DCLO : CountLeading1<"dclo", GPR64Opnd, II_DCLO>, CLO_FM<0x25>,
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ISA_MIPS64_NOT_64R6;
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/// Double Word Swap Bytes/HalfWords
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let AdditionalPredicates = [NotInMicroMips] in {
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@ -460,10 +462,14 @@ def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>, ASE_CNMIPS;
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/// Move between CPU and coprocessor registers
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let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
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def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd>, MFC3OP_FM<0x10, 1>, ISA_MIPS3;
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def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
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def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
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def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
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def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd, II_DMFC0>, MFC3OP_FM<0x10, 1>,
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ISA_MIPS3;
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def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd, II_DMTC0>, MFC3OP_FM<0x10, 5>,
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ISA_MIPS3;
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def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd, II_DMFC2>, MFC3OP_FM<0x12, 1>,
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ISA_MIPS3;
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def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd, II_DMTC2>, MFC3OP_FM<0x12, 5>,
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ISA_MIPS3;
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}
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//===----------------------------------------------------------------------===//
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@ -1273,7 +1273,7 @@ def BALIGN : DspMMRel, BALIGN_ENC, BALIGN_DESC, ISA_DSPR2;
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def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC, ISA_DSPR2;
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// Pseudos.
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let isPseudo = 1, isCodeGenOnly = 1 in {
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let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
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// Pseudo instructions for loading and storing accumulator registers.
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def LOAD_ACC64DSP : Load<"", ACC64DSPOpnd>;
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def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
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@ -51,7 +51,8 @@ class PREFE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_PREFE>;
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//===----------------------------------------------------------------------===//
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// Memory Load/Store EVA descriptions
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class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs GPROpnd:$rt);
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dag InOperandList = (ins mem_simm9:$addr);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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@ -59,30 +60,34 @@ class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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string DecoderMethod = "DecodeMemEVA";
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bit canFoldAsLoad = 1;
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bit mayLoad = 1;
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InstrItinClass Itinerary = itin;
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}
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class LBE_DESC : LOAD_EVA_DESC_BASE<"lbe", GPR32Opnd>;
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class LBuE_DESC : LOAD_EVA_DESC_BASE<"lbue", GPR32Opnd>;
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class LHE_DESC : LOAD_EVA_DESC_BASE<"lhe", GPR32Opnd>;
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class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd>;
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class LWE_DESC : LOAD_EVA_DESC_BASE<"lwe", GPR32Opnd>;
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class LBE_DESC : LOAD_EVA_DESC_BASE<"lbe", GPR32Opnd, II_LBE>;
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class LBuE_DESC : LOAD_EVA_DESC_BASE<"lbue", GPR32Opnd, II_LBUE>;
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class LHE_DESC : LOAD_EVA_DESC_BASE<"lhe", GPR32Opnd, II_LHE>;
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class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd, II_LHUE>;
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class LWE_DESC : LOAD_EVA_DESC_BASE<"lwe", GPR32Opnd, II_LWE>;
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class STORE_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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SDPatternOperator OpNode = null_frag> {
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SDPatternOperator OpNode = null_frag,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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list<dag> Pattern = [];
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string DecoderMethod = "DecodeMemEVA";
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bit mayStore = 1;
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InstrItinClass Itinerary = itin;
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}
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class SBE_DESC : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd>;
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class SHE_DESC : STORE_EVA_DESC_BASE<"she", GPR32Opnd>;
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class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd>;
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class SBE_DESC : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd, null_frag, II_SBE>;
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class SHE_DESC : STORE_EVA_DESC_BASE<"she", GPR32Opnd, null_frag, II_SHE>;
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class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd, null_frag, II_SWE>;
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// Load/Store Left/Right EVA descriptions
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class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs GPROpnd:$rt);
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dag InOperandList = (ins mem_simm9:$addr, GPROpnd:$src);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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@ -90,35 +95,41 @@ class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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string DecoderMethod = "DecodeMemEVA";
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string Constraints = "$src = $rt";
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bit canFoldAsLoad = 1;
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InstrItinClass Itinerary = itin;
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}
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class LWLE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwle", GPR32Opnd>;
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class LWRE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwre", GPR32Opnd>;
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class LWLE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwle", GPR32Opnd, II_LWLE>;
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class LWRE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwre", GPR32Opnd, II_LWRE>;
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class STORE_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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class STORE_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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list<dag> Pattern = [];
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string DecoderMethod = "DecodeMemEVA";
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InstrItinClass Itinerary = itin;
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}
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class SWLE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"swle", GPR32Opnd>;
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class SWRE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"swre", GPR32Opnd>;
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class SWLE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"swle", GPR32Opnd, II_SWLE>;
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class SWRE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"swre", GPR32Opnd, II_SWRE>;
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// Load-linked EVA, Store-conditional EVA descriptions
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class LLE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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class LLE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs GPROpnd:$rt);
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dag InOperandList = (ins mem_simm9:$addr);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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list<dag> Pattern = [];
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bit mayLoad = 1;
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string DecoderMethod = "DecodeMemEVA";
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InstrItinClass Itinerary = itin;
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}
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class LLE_DESC : LLE_DESC_BASE<"lle", GPR32Opnd>;
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class LLE_DESC : LLE_DESC_BASE<"lle", GPR32Opnd, II_LLE>;
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class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs GPROpnd:$dst);
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dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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@ -126,30 +137,34 @@ class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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bit mayStore = 1;
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string Constraints = "$rt = $dst";
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string DecoderMethod = "DecodeMemEVA";
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InstrItinClass Itinerary = itin;
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}
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class SCE_DESC : SCE_DESC_BASE<"sce", GPR32Opnd>;
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class SCE_DESC : SCE_DESC_BASE<"sce", GPR32Opnd, II_SCE>;
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class TLB_DESC_BASE<string instr_asm> {
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class TLB_DESC_BASE<string instr_asm, InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins);
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string AsmString = instr_asm;
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list<dag> Pattern = [];
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InstrItinClass Itinerary = itin;
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}
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class TLBINV_DESC : TLB_DESC_BASE<"tlbinv">;
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class TLBINVF_DESC : TLB_DESC_BASE<"tlbinvf">;
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class TLBINV_DESC : TLB_DESC_BASE<"tlbinv", II_TLBINV>;
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class TLBINVF_DESC : TLB_DESC_BASE<"tlbinvf", II_TLBINVF>;
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class CACHEE_DESC_BASE<string instr_asm, Operand MemOpnd> {
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class CACHEE_DESC_BASE<string instr_asm, Operand MemOpnd,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
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string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
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list<dag> Pattern = [];
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string DecoderMethod = "DecodeCacheeOp_CacheOpR6";
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InstrItinClass Itinerary = itin;
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}
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class CACHEE_DESC : CACHEE_DESC_BASE<"cachee", mem_simm9>;
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class PREFE_DESC : CACHEE_DESC_BASE<"prefe", mem_simm9>;
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class CACHEE_DESC : CACHEE_DESC_BASE<"cachee", mem_simm9, II_CACHEE>;
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class PREFE_DESC : CACHEE_DESC_BASE<"prefe", mem_simm9, II_PREFE>;
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//===----------------------------------------------------------------------===//
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//
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@ -543,7 +543,8 @@ def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
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// allocation.
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class BuildPairF64Base<RegisterOperand RO> :
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PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
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[(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
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[(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))],
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II_MTC1>;
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def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
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def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
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@ -552,9 +553,12 @@ def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
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// allocation.
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// if n is 0, lower part of src is extracted.
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// if n is 1, higher part of src is extracted.
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// This node has associated scheduling information as the pre RA scheduler
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// asserts otherwise.
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class ExtractElementF64Base<RegisterOperand RO> :
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PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
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[(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>;
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[(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))],
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II_MFC1>;
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def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
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def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
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@ -1351,52 +1351,54 @@ class BAL_BR_Pseudo<Instruction RealInst> :
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let isCTI = 1 in {
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// Syscall
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class SYS_FT<string opstr, Operand ImmOp> :
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class SYS_FT<string opstr, Operand ImmOp, InstrItinClass itin = NoItinerary> :
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InstSE<(outs), (ins ImmOp:$code_),
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!strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
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!strconcat(opstr, "\t$code_"), [], itin, FrmI, opstr>;
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// Break
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class BRK_FT<string opstr> :
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InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
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!strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
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!strconcat(opstr, "\t$code_1, $code_2"), [], II_BREAK,
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FrmOther, opstr>;
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// (D)Eret
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class ER_FT<string opstr> :
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class ER_FT<string opstr, InstrItinClass itin = NoItinerary> :
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InstSE<(outs), (ins),
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opstr, [], NoItinerary, FrmOther, opstr>;
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opstr, [], itin, FrmOther, opstr>;
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// Wait
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class WAIT_FT<string opstr> :
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InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
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InstSE<(outs), (ins), opstr, [], II_WAIT, FrmOther, opstr>;
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}
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// Interrupts
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class DEI_FT<string opstr, RegisterOperand RO> :
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class DEI_FT<string opstr, RegisterOperand RO,
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InstrItinClass itin = NoItinerary> :
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InstSE<(outs RO:$rt), (ins),
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!strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
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!strconcat(opstr, "\t$rt"), [], itin, FrmOther, opstr>;
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// Sync
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let hasSideEffects = 1 in
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class SYNC_FT<string opstr> :
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InstSE<(outs), (ins uimm5:$stype), "sync $stype",
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[(MipsSync immZExt5:$stype)], NoItinerary, FrmOther, opstr>;
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[(MipsSync immZExt5:$stype)], II_SYNC, FrmOther, opstr>;
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class SYNCI_FT<string opstr> :
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InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
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NoItinerary, FrmOther, opstr> {
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II_SYNCI, FrmOther, opstr> {
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let hasSideEffects = 1;
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let DecoderMethod = "DecodeSyncI";
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}
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let hasSideEffects = 1, isCTI = 1 in {
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class TEQ_FT<string opstr, RegisterOperand RO, Operand ImmOp> :
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class TEQ_FT<string opstr, RegisterOperand RO, Operand ImmOp,
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InstrItinClass itin = NoItinerary> :
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InstSE<(outs), (ins RO:$rs, RO:$rt, ImmOp:$code_),
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!strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
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FrmI, opstr>;
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!strconcat(opstr, "\t$rs, $rt, $code_"), [], itin, FrmI, opstr>;
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class TEQI_FT<string opstr, RegisterOperand RO> :
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class TEQI_FT<string opstr, RegisterOperand RO,
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InstrItinClass itin = NoItinerary> :
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InstSE<(outs), (ins RO:$rs, simm16:$imm16),
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!strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
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!strconcat(opstr, "\t$rs, $imm16"), [], itin, FrmOther, opstr>;
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}
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// Mul, Div
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@ -1469,20 +1471,23 @@ class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
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|
||||
class EffectiveAddress<string opstr, RegisterOperand RO> :
|
||||
InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
||||
[(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
|
||||
[(set RO:$rt, addr:$addr)], II_ADDIU, FrmI,
|
||||
!strconcat(opstr, "_lea")> {
|
||||
let isCodeGenOnly = 1;
|
||||
let hasNoSchedulingInfo = 1;
|
||||
let DecoderMethod = "DecodeMem";
|
||||
}
|
||||
|
||||
// Count Leading Ones/Zeros in Word
|
||||
class CountLeading0<string opstr, RegisterOperand RO>:
|
||||
class CountLeading0<string opstr, RegisterOperand RO,
|
||||
InstrItinClass itin = NoItinerary>:
|
||||
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
|
||||
[(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
|
||||
[(set RO:$rd, (ctlz RO:$rs))], itin, FrmR, opstr>;
|
||||
|
||||
class CountLeading1<string opstr, RegisterOperand RO>:
|
||||
class CountLeading1<string opstr, RegisterOperand RO,
|
||||
InstrItinClass itin = NoItinerary>:
|
||||
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
|
||||
[(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
|
||||
[(set RO:$rd, (ctlz (not RO:$rs)))], itin, FrmR, opstr>;
|
||||
|
||||
// Sign Extend in Register.
|
||||
class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
|
||||
|
|
@ -1533,29 +1538,31 @@ class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
|
|||
|
||||
class LLBase<string opstr, RegisterOperand RO> :
|
||||
InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
||||
[], NoItinerary, FrmI> {
|
||||
[], II_LL, FrmI> {
|
||||
let DecoderMethod = "DecodeMem";
|
||||
let mayLoad = 1;
|
||||
}
|
||||
|
||||
class SCBase<string opstr, RegisterOperand RO> :
|
||||
InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
|
||||
!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
|
||||
!strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> {
|
||||
let DecoderMethod = "DecodeMem";
|
||||
let mayStore = 1;
|
||||
let Constraints = "$rt = $dst";
|
||||
}
|
||||
|
||||
class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
|
||||
class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD,
|
||||
InstrItinClass itin> :
|
||||
InstSE<(outs RO:$rt), (ins RD:$rd, uimm3:$sel),
|
||||
!strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
|
||||
!strconcat(asmstr, "\t$rt, $rd, $sel"), [], itin, FrmFR>;
|
||||
|
||||
class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
|
||||
class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD,
|
||||
InstrItinClass itin> :
|
||||
InstSE<(outs RO:$rd), (ins RD:$rt, uimm3:$sel),
|
||||
!strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
|
||||
!strconcat(asmstr, "\t$rt, $rd, $sel"), [], itin, FrmFR>;
|
||||
|
||||
class TrapBase<Instruction RealInst>
|
||||
: PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
|
||||
: PseudoSE<(outs), (ins), [(trap)], II_TRAP>,
|
||||
PseudoInstExpansion<(RealInst 0, 0)> {
|
||||
let isBarrier = 1;
|
||||
let isTerminator = 1;
|
||||
|
|
@ -1613,7 +1620,7 @@ let usesCustomInserter = 1 in {
|
|||
}
|
||||
|
||||
/// Pseudo instructions for loading and storing accumulator registers.
|
||||
let isPseudo = 1, isCodeGenOnly = 1 in {
|
||||
let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
|
||||
def LOAD_ACC64 : Load<"", ACC64>;
|
||||
def STORE_ACC64 : Store<"", ACC64>;
|
||||
}
|
||||
|
|
@ -1643,7 +1650,7 @@ def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd,
|
|||
II_ADDIU, immSExt16, add>,
|
||||
ADDI_FM<0x9>, IsAsCheapAsAMove;
|
||||
}
|
||||
def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd>, ADDI_FM<0x8>,
|
||||
def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, ADDI_FM<0x8>,
|
||||
ISA_MIPS1_NOT_32R6_64R6;
|
||||
def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
|
||||
SLTI_FM<0xa>;
|
||||
|
|
@ -1671,8 +1678,8 @@ def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
|
|||
let Defs = [HI0, LO0] in
|
||||
def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
|
||||
ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
|
||||
def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
|
||||
def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
|
||||
def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, ADD_FM<0, 0x20>;
|
||||
def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, ADD_FM<0, 0x22>;
|
||||
def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
|
||||
def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
|
|
@ -1745,22 +1752,22 @@ def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
|
|||
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
// COP2 Memory Instructions
|
||||
def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
|
||||
def LWC2 : LW_FT2<"lwc2", COP2Opnd, II_LWC2, load>, LW_FM<0x32>,
|
||||
ISA_MIPS1_NOT_32R6_64R6;
|
||||
def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
|
||||
def SWC2 : SW_FT2<"swc2", COP2Opnd, II_SWC2, store>, LW_FM<0x3a>,
|
||||
ISA_MIPS1_NOT_32R6_64R6;
|
||||
def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
|
||||
def LDC2 : LW_FT2<"ldc2", COP2Opnd, II_LDC2, load>, LW_FM<0x36>,
|
||||
ISA_MIPS2_NOT_32R6_64R6;
|
||||
def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
|
||||
def SDC2 : SW_FT2<"sdc2", COP2Opnd, II_SDC2, store>, LW_FM<0x3e>,
|
||||
ISA_MIPS2_NOT_32R6_64R6;
|
||||
|
||||
// COP3 Memory Instructions
|
||||
let DecoderNamespace = "COP3_" in {
|
||||
def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
|
||||
def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
|
||||
def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
|
||||
def LWC3 : LW_FT3<"lwc3", COP3Opnd, II_LWC3, load>, LW_FM<0x33>;
|
||||
def SWC3 : SW_FT3<"swc3", COP3Opnd, II_SWC3, store>, LW_FM<0x3b>;
|
||||
def LDC3 : LW_FT3<"ldc3", COP3Opnd, II_LDC3, load>, LW_FM<0x37>,
|
||||
ISA_MIPS2;
|
||||
def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
|
||||
def SDC3 : SW_FT3<"sdc3", COP3Opnd, II_SDC3, store>, LW_FM<0x3f>,
|
||||
ISA_MIPS2;
|
||||
}
|
||||
}
|
||||
|
|
@ -1770,45 +1777,45 @@ def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM,
|
|||
def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
|
||||
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10>, TEQ_FM<0x34>, ISA_MIPS2;
|
||||
def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10>, TEQ_FM<0x30>, ISA_MIPS2;
|
||||
def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10>, TEQ_FM<0x31>, ISA_MIPS2;
|
||||
def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm10>, TEQ_FM<0x32>, ISA_MIPS2;
|
||||
def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10>, TEQ_FM<0x33>, ISA_MIPS2;
|
||||
def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm10>, TEQ_FM<0x36>, ISA_MIPS2;
|
||||
def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>, ISA_MIPS2;
|
||||
def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10, II_TGE>, TEQ_FM<0x30>, ISA_MIPS2;
|
||||
def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10, II_TGEU>, TEQ_FM<0x31>, ISA_MIPS2;
|
||||
def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm10, II_TLT>, TEQ_FM<0x32>, ISA_MIPS2;
|
||||
def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10, II_TLTU>, TEQ_FM<0x33>, ISA_MIPS2;
|
||||
def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm10, II_TNE>, TEQ_FM<0x36>, ISA_MIPS2;
|
||||
}
|
||||
|
||||
def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
|
||||
def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM<0xc>,
|
||||
ISA_MIPS2_NOT_32R6_64R6;
|
||||
def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
|
||||
def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM<0x8>,
|
||||
ISA_MIPS2_NOT_32R6_64R6;
|
||||
def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
|
||||
def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>, TEQI_FM<0x9>,
|
||||
ISA_MIPS2_NOT_32R6_64R6;
|
||||
def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
|
||||
def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM<0xa>,
|
||||
ISA_MIPS2_NOT_32R6_64R6;
|
||||
def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
|
||||
def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>, TEQI_FM<0xb>,
|
||||
ISA_MIPS2_NOT_32R6_64R6;
|
||||
def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
|
||||
def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM<0xe>,
|
||||
ISA_MIPS2_NOT_32R6_64R6;
|
||||
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>;
|
||||
def SYSCALL : MMRel, SYS_FT<"syscall", uimm20>, SYS_FM<0xc>;
|
||||
def SYSCALL : MMRel, SYS_FT<"syscall", uimm20, II_SYSCALL>, SYS_FM<0xc>;
|
||||
}
|
||||
def TRAP : TrapBase<BREAK>;
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20>, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
|
||||
def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20, II_SDBBP>, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
|
||||
}
|
||||
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
|
||||
def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
|
||||
def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
|
||||
def ERET : MMRel, ER_FT<"eret", II_ERET>, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
|
||||
def ERETNC : MMRel, ER_FT<"eretnc", II_ERETNC>, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
|
||||
def DERET : MMRel, ER_FT<"deret", II_DERET>, ER_FM<0x1f, 0x0>, ISA_MIPS32;
|
||||
}
|
||||
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
|
||||
def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
|
||||
def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM<1>, ISA_MIPS32R2;
|
||||
def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM<0>, ISA_MIPS32R2;
|
||||
}
|
||||
|
||||
let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
|
||||
|
|
@ -1952,9 +1959,9 @@ def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
|
|||
SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
|
||||
|
||||
/// Count Leading
|
||||
def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
|
||||
def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>,
|
||||
ISA_MIPS32_NOT_32R6_64R6;
|
||||
def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
|
||||
def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>,
|
||||
ISA_MIPS32_NOT_32R6_64R6;
|
||||
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
|
|
@ -2016,21 +2023,23 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
|||
}
|
||||
/// Move Control Registers From/To CPU Registers
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>,
|
||||
def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd, II_MTC0>, MFC3OP_FM<0x10, 4>,
|
||||
ISA_MIPS32;
|
||||
def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>,
|
||||
def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd, II_MFC0>, MFC3OP_FM<0x10, 0>,
|
||||
ISA_MIPS32;
|
||||
}
|
||||
def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
|
||||
def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
|
||||
def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd, II_MFC2>, MFC3OP_FM<0x12, 0>;
|
||||
def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd, II_MTC2>, MFC3OP_FM<0x12, 4>;
|
||||
|
||||
class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
|
||||
FrmOther, asmstr>;
|
||||
def SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop">, BARRIER_FM<1>;
|
||||
def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
|
||||
class Barrier<string asmstr, InstrItinClass itin = NoItinerary> :
|
||||
InstSE<(outs), (ins), asmstr, [], itin, FrmOther, asmstr>;
|
||||
|
||||
def SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM<1>;
|
||||
def EHB : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM<3>;
|
||||
|
||||
let isCTI = 1 in
|
||||
def PAUSE : MMRel, StdMMR6Rel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
|
||||
def PAUSE : MMRel, StdMMR6Rel, Barrier<"pause", II_PAUSE>, BARRIER_FM<5>,
|
||||
ISA_MIPS32R2;
|
||||
|
||||
// JR_HB and JALR_HB are defined here using the new style naming
|
||||
// scheme because some of this code is shared with Mips32r6InstrInfo.td
|
||||
|
|
@ -2051,7 +2060,7 @@ class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
|
|||
list<dag> Pattern = [];
|
||||
}
|
||||
|
||||
class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
|
||||
class JR_HB_DESC : InstSE<(outs), (ins), "", [], II_JR_HB, FrmJ>,
|
||||
JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
|
||||
let isBranch=1;
|
||||
let isIndirectBranch=1;
|
||||
|
|
@ -2061,7 +2070,7 @@ class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
|
|||
bit isCTI = 1;
|
||||
}
|
||||
|
||||
class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
|
||||
class JALR_HB_DESC : InstSE<(outs), (ins), "", [], II_JALR_HB, FrmJ>,
|
||||
JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
|
||||
let isIndirectBranch=1;
|
||||
let hasDelaySlot=1;
|
||||
|
|
@ -2074,24 +2083,25 @@ class JALR_HB_ENC : JALR_HB_FM<9>;
|
|||
def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
|
||||
def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
|
||||
|
||||
class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
|
||||
FrmOther, asmstr>;
|
||||
class TLB<string asmstr, InstrItinClass itin = NoItinerary> :
|
||||
InstSE<(outs), (ins), asmstr, [], itin, FrmOther, asmstr>;
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
|
||||
def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
|
||||
def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
|
||||
def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
|
||||
def TLBP : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM<0x08>;
|
||||
def TLBR : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM<0x01>;
|
||||
def TLBWI : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM<0x02>;
|
||||
def TLBWR : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM<0x06>;
|
||||
}
|
||||
class CacheOp<string instr_asm, Operand MemOpnd> :
|
||||
class CacheOp<string instr_asm, Operand MemOpnd,
|
||||
InstrItinClass itin = NoItinerary> :
|
||||
InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
|
||||
!strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther,
|
||||
!strconcat(instr_asm, "\t$hint, $addr"), [], itin, FrmOther,
|
||||
instr_asm> {
|
||||
let DecoderMethod = "DecodeCacheOp";
|
||||
}
|
||||
|
||||
def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
|
||||
def CACHE : MMRel, CacheOp<"cache", mem, II_CACHE>, CACHEOP_FM<0b101111>,
|
||||
INSN_MIPS3_32_NOT_32R6_64R6;
|
||||
def PREF : MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
|
||||
def PREF : MMRel, CacheOp<"pref", mem, II_PREF>, CACHEOP_FM<0b110011>,
|
||||
INSN_MIPS3_32_NOT_32R6_64R6;
|
||||
|
||||
def ROL : MipsAsmPseudoInst<(outs),
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ def II_ABS : InstrItinClass;
|
|||
def II_ADDI : InstrItinClass;
|
||||
def II_ADDIU : InstrItinClass;
|
||||
def II_ADDIUPC : InstrItinClass;
|
||||
def II_ADD : InstrItinClass;
|
||||
def II_ADDU : InstrItinClass;
|
||||
def II_ADD_D : InstrItinClass;
|
||||
def II_ADD_S : InstrItinClass;
|
||||
|
|
@ -60,6 +61,7 @@ def II_C_CC_D : InstrItinClass; // Any c.<cc>.d instruction
|
|||
def II_C_CC_S : InstrItinClass; // Any c.<cc>.s instruction
|
||||
def II_DADDIU : InstrItinClass;
|
||||
def II_DADDU : InstrItinClass;
|
||||
def II_DADDI : InstrItinClass;
|
||||
def II_DADD : InstrItinClass;
|
||||
def II_DAHI : InstrItinClass;
|
||||
def II_DATI : InstrItinClass;
|
||||
|
|
@ -74,12 +76,16 @@ def II_DIV : InstrItinClass;
|
|||
def II_DIVU : InstrItinClass;
|
||||
def II_DIV_D : InstrItinClass;
|
||||
def II_DIV_S : InstrItinClass;
|
||||
def II_DMFC0 : InstrItinClass;
|
||||
def II_DMTC0 : InstrItinClass;
|
||||
def II_DMFC1 : InstrItinClass;
|
||||
def II_DMTC1 : InstrItinClass;
|
||||
def II_DMOD : InstrItinClass;
|
||||
def II_DMODU : InstrItinClass;
|
||||
def II_DMUH : InstrItinClass;
|
||||
def II_DMUHU : InstrItinClass;
|
||||
def II_DMFC2 : InstrItinClass;
|
||||
def II_DMTC2 : InstrItinClass;
|
||||
def II_DMUL : InstrItinClass;
|
||||
def II_DMULU : InstrItinClass;
|
||||
def II_DMULT : InstrItinClass;
|
||||
|
|
@ -96,6 +102,8 @@ def II_DSRAV : InstrItinClass;
|
|||
def II_DSRL : InstrItinClass;
|
||||
def II_DSRL32 : InstrItinClass;
|
||||
def II_DSRLV : InstrItinClass;
|
||||
def II_DSBH : InstrItinClass;
|
||||
def II_DSHD : InstrItinClass;
|
||||
def II_DSUBU : InstrItinClass;
|
||||
def II_DSUB : InstrItinClass;
|
||||
def II_EXT : InstrItinClass; // Any EXT instruction
|
||||
|
|
@ -105,21 +113,56 @@ def II_IndirectBranchPseudo : InstrItinClass; // Indirect branch pseudo.
|
|||
def II_J : InstrItinClass;
|
||||
def II_JAL : InstrItinClass;
|
||||
def II_JALR : InstrItinClass;
|
||||
def II_JALR_HB : InstrItinClass;
|
||||
def II_JALRC : InstrItinClass;
|
||||
def II_JALRS : InstrItinClass;
|
||||
def II_JALS : InstrItinClass;
|
||||
def II_JIC : InstrItinClass;
|
||||
def II_JIALC : InstrItinClass;
|
||||
def II_JR : InstrItinClass;
|
||||
def II_JR_HB : InstrItinClass;
|
||||
def II_JRADDIUSP : InstrItinClass;
|
||||
def II_JRC : InstrItinClass;
|
||||
def II_ReturnPseudo : InstrItinClass; // Return pseudo.
|
||||
def II_ERET : InstrItinClass;
|
||||
def II_DERET : InstrItinClass;
|
||||
def II_ERETNC : InstrItinClass;
|
||||
def II_EHB : InstrItinClass;
|
||||
def II_SDBBP : InstrItinClass;
|
||||
def II_SSNOP : InstrItinClass;
|
||||
def II_SYSCALL : InstrItinClass;
|
||||
def II_PAUSE : InstrItinClass;
|
||||
def II_WAIT : InstrItinClass;
|
||||
def II_EI : InstrItinClass;
|
||||
def II_DI : InstrItinClass;
|
||||
def II_TEQ : InstrItinClass;
|
||||
def II_TEQI : InstrItinClass;
|
||||
def II_TGE : InstrItinClass;
|
||||
def II_TGEI : InstrItinClass;
|
||||
def II_TGEIU : InstrItinClass;
|
||||
def II_TGEU : InstrItinClass;
|
||||
def II_TNE : InstrItinClass;
|
||||
def II_TNEI : InstrItinClass;
|
||||
def II_TLT : InstrItinClass;
|
||||
def II_TLTI : InstrItinClass;
|
||||
def II_TLTU : InstrItinClass;
|
||||
def II_TTLTIU : InstrItinClass;
|
||||
def II_TLBP : InstrItinClass;
|
||||
def II_TLBR : InstrItinClass;
|
||||
def II_TLBWI : InstrItinClass;
|
||||
def II_TLBWR : InstrItinClass;
|
||||
def II_TRAP : InstrItinClass;
|
||||
def II_BREAK : InstrItinClass;
|
||||
def II_SYNC : InstrItinClass;
|
||||
def II_SYNCI : InstrItinClass;
|
||||
def II_LB : InstrItinClass;
|
||||
def II_LBE : InstrItinClass;
|
||||
def II_LBU : InstrItinClass;
|
||||
def II_LBUE : InstrItinClass;
|
||||
def II_LD : InstrItinClass;
|
||||
def II_LDC1 : InstrItinClass;
|
||||
def II_LDC2 : InstrItinClass;
|
||||
def II_LDC3 : InstrItinClass;
|
||||
def II_LDL : InstrItinClass;
|
||||
def II_LDR : InstrItinClass;
|
||||
def II_LDPC : InstrItinClass;
|
||||
|
|
@ -128,11 +171,15 @@ def II_LH : InstrItinClass;
|
|||
def II_LHE : InstrItinClass;
|
||||
def II_LHU : InstrItinClass;
|
||||
def II_LHUE : InstrItinClass;
|
||||
def II_LL : InstrItinClass;
|
||||
def II_LLD : InstrItinClass;
|
||||
def II_LUI : InstrItinClass;
|
||||
def II_LUXC1 : InstrItinClass;
|
||||
def II_LW : InstrItinClass;
|
||||
def II_LWE : InstrItinClass;
|
||||
def II_LWC1 : InstrItinClass;
|
||||
def II_LWC2 : InstrItinClass;
|
||||
def II_LWC3 : InstrItinClass;
|
||||
def II_LWL : InstrItinClass;
|
||||
def II_LWLE : InstrItinClass;
|
||||
def II_LWPC : InstrItinClass;
|
||||
|
|
@ -141,8 +188,6 @@ def II_LWRE : InstrItinClass;
|
|||
def II_LWU : InstrItinClass;
|
||||
def II_LWUPC : InstrItinClass;
|
||||
def II_LWXC1 : InstrItinClass;
|
||||
def II_LL : InstrItinClass;
|
||||
def II_LLD : InstrItinClass;
|
||||
def II_LSA : InstrItinClass;
|
||||
def II_DLSA : InstrItinClass;
|
||||
def II_MADD : InstrItinClass;
|
||||
|
|
@ -151,8 +196,10 @@ def II_MADD_D : InstrItinClass;
|
|||
def II_MADD_S : InstrItinClass;
|
||||
def II_MADDF_D : InstrItinClass;
|
||||
def II_MADDF_S : InstrItinClass;
|
||||
def II_MFC0 : InstrItinClass;
|
||||
def II_MFC1 : InstrItinClass;
|
||||
def II_MFHC1 : InstrItinClass;
|
||||
def II_MFC2 : InstrItinClass;
|
||||
def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo
|
||||
def II_MOD : InstrItinClass;
|
||||
def II_MODU : InstrItinClass;
|
||||
|
|
@ -176,8 +223,10 @@ def II_MSUB_D : InstrItinClass;
|
|||
def II_MSUB_S : InstrItinClass;
|
||||
def II_MSUBF_D : InstrItinClass;
|
||||
def II_MSUBF_S : InstrItinClass;
|
||||
def II_MTC0 : InstrItinClass;
|
||||
def II_MTC1 : InstrItinClass;
|
||||
def II_MTHC1 : InstrItinClass;
|
||||
def II_MTC2 : InstrItinClass;
|
||||
def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo
|
||||
def II_MUL : InstrItinClass;
|
||||
def II_MUH : InstrItinClass;
|
||||
|
|
@ -208,6 +257,8 @@ def II_SB : InstrItinClass;
|
|||
def II_SBE : InstrItinClass;
|
||||
def II_SD : InstrItinClass;
|
||||
def II_SDC1 : InstrItinClass;
|
||||
def II_SDC2 : InstrItinClass;
|
||||
def II_SDC3 : InstrItinClass;
|
||||
def II_SDL : InstrItinClass;
|
||||
def II_SDR : InstrItinClass;
|
||||
def II_SDXC1 : InstrItinClass;
|
||||
|
|
@ -228,6 +279,7 @@ def II_SRA : InstrItinClass;
|
|||
def II_SRAV : InstrItinClass;
|
||||
def II_SRL : InstrItinClass;
|
||||
def II_SRLV : InstrItinClass;
|
||||
def II_SUB : InstrItinClass;
|
||||
def II_SUBU : InstrItinClass;
|
||||
def II_SUB_D : InstrItinClass;
|
||||
def II_SUB_S : InstrItinClass;
|
||||
|
|
@ -235,6 +287,8 @@ def II_SUXC1 : InstrItinClass;
|
|||
def II_SW : InstrItinClass;
|
||||
def II_SWE : InstrItinClass;
|
||||
def II_SWC1 : InstrItinClass;
|
||||
def II_SWC2 : InstrItinClass;
|
||||
def II_SWC3 : InstrItinClass;
|
||||
def II_SWL : InstrItinClass;
|
||||
def II_SWLE : InstrItinClass;
|
||||
def II_SWR : InstrItinClass;
|
||||
|
|
@ -244,6 +298,14 @@ def II_TRUNC : InstrItinClass;
|
|||
def II_WSBH : InstrItinClass;
|
||||
def II_XOR : InstrItinClass;
|
||||
def II_XORI : InstrItinClass;
|
||||
def II_CACHE : InstrItinClass;
|
||||
def II_PREF : InstrItinClass;
|
||||
def II_CACHEE : InstrItinClass;
|
||||
def II_PREFE : InstrItinClass;
|
||||
def II_LLE : InstrItinClass;
|
||||
def II_SCE : InstrItinClass;
|
||||
def II_TLBINV : InstrItinClass;
|
||||
def II_TLBINVF : InstrItinClass;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Mips Generic instruction itineraries.
|
||||
|
|
@ -253,6 +315,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
|||
InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_ADDIUPC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_ADD , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_AUI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
|
||||
|
|
@ -273,6 +336,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
|||
InstrItinData<II_CLZ , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DADDIU , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DADDU , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DADDI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DADD , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DALIGN , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DAHI , [InstrStage<1, [ALU]>]>,
|
||||
|
|
@ -284,15 +348,23 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
|||
InstrItinData<II_DMOD , [InstrStage<17, [IMULDIV]>]>,
|
||||
InstrItinData<II_DMODU , [InstrStage<17, [IMULDIV]>]>,
|
||||
InstrItinData<II_DSLL , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DSLL32 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DSRL , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DSRL32 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DSRA , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DSRA32 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DSLLV , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DSRLV , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DSRAV , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DSUBU , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DSUB , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DROTR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DROTR32 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DROTRV , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DSBH , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DSHD , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DCLO , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DCLZ , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_EXT , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_INS , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_LUI , [InstrStage<1, [ALU]>]>,
|
||||
|
|
@ -306,19 +378,25 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
|||
InstrItinData<II_OR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_POP , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_RDHWR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SUB , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SUBU , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_XOR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_ANDI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_ORI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_XORI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_LB , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LBE , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LBU , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LBUE , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LH , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LHU , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LHUE , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LW , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWPC , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWL , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWLE , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWR , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWRE , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWUPC , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LD , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LDL , [InstrStage<3, [ALU]>]>,
|
||||
|
|
@ -329,18 +407,21 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
|||
InstrItinData<II_RESTORE , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_SB , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SH , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SHE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SW , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SWL , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SWR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SDL , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SDR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SD , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SCD , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SAVE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SELCCZ , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SEQ_SNE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SEQI_SNEI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SCD , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SLTI_SLTIU , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SLT_SLTU , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_B , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_BALC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_BBIT , [InstrStage<1, [ALU]>]>,
|
||||
|
|
@ -360,17 +441,51 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
|||
InstrItinData<II_J , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_JAL , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_JALR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_JALR_HB , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_JALRC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_JALRS , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_JALS , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_JIC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_JIALC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_JR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_JR_HB , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_JRADDIUSP , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_JRC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_ReturnPseudo , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<IIPseudo , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DMUH , [InstrStage<17, [IMULDIV]>]>,
|
||||
InstrItinData<II_DMUHU , [InstrStage<17, [IMULDIV]>]>,
|
||||
InstrItinData<II_ERET , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DERET , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_ERETNC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_EHB , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SDBBP , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SSNOP , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SYSCALL , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_WAIT , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_EI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TEQ , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TEQI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TGE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TGEI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TGEIU , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TGEU , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TNE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TNEI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TLT , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TLTI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TLTU , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TTLTIU , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TLBP , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TLBR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TLBWI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TLBWR , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TRAP , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_BREAK , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SYNC , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SYNCI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DMUL , [InstrStage<17, [IMULDIV]>]>,
|
||||
InstrItinData<II_DMULT , [InstrStage<17, [IMULDIV]>]>,
|
||||
InstrItinData<II_DMULTU , [InstrStage<17, [IMULDIV]>]>,
|
||||
|
|
@ -436,24 +551,49 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
|||
InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>,
|
||||
InstrItinData<II_SQRT_S , [InstrStage<54, [ALU]>]>,
|
||||
InstrItinData<II_SQRT_D , [InstrStage<12, [ALU]>]>,
|
||||
InstrItinData<II_WSBH , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_LSA , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DLSA , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_LDC1 , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LDC2 , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LDC3 , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWC1 , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWC2 , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWC3 , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LDXC1 , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LWXC1 , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_LUXC1 , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_SDC1 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SDC2 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SDC3 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SWC1 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SWC2 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SWC3 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SDXC1 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SWXC1 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_SUXC1 , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_DMFC0 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_DMFC1 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_DMFC2 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_DMTC0 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_DMTC1 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_DMTC2 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MFC0 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MFC1 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MFC2 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MTC0 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MTC1 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MTC2 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MFHC1 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MTHC1 , [InstrStage<2, [ALU]>]>
|
||||
InstrItinData<II_MTHC1 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_CACHE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_PREF , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_CACHEE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_PREFE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TLBINV , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_TLBINVF , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_LLE , [InstrStage<3, [ALU]>]>,
|
||||
InstrItinData<II_SCE , [InstrStage<1, [ALU]>]>
|
||||
]>;
|
||||
|
||||
include "MipsScheduleP5600.td"
|
||||
|
|
|
|||
|
|
@ -521,14 +521,14 @@ entry:
|
|||
; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4
|
||||
; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]]
|
||||
|
||||
; 64-CMP-DAG: daddiu $[[I5:[0-9]+]], $zero, 5
|
||||
; 64-CMP-DAG: daddiu $[[I4:2]], $zero, 4
|
||||
; 64-CMP-DAG: daddiu $[[I4:[0-9]+]], $zero, 4
|
||||
; 64-CMP-DAG: daddiu $[[I5:2]], $zero, 5
|
||||
; 64-CMP-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766
|
||||
; 64-CMP-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4
|
||||
; FIXME: We can do better than this by using selccz to choose between -0 and -2
|
||||
; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I5]], $[[R0]]
|
||||
; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I4]], $[[R0]]
|
||||
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
|
||||
; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I4]], $[[R0]]
|
||||
; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
|
||||
; 64-CMP-DAG: or $2, $[[T1]], $[[T0]]
|
||||
|
||||
define i64 @slti64_3(i64 %a) {
|
||||
entry:
|
||||
|
|
|
|||
|
|
@ -132,13 +132,13 @@ entry:
|
|||
; GP32: lw $[[T3:[0-9]+]], 24($sp)
|
||||
; GP32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
|
||||
; GP32: addu $[[T5:[0-9]+]], $6, $[[T4]]
|
||||
; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
|
||||
; GP32: lw $[[T6:[0-9]+]], 16($sp)
|
||||
; GP32: lw $[[T7:[0-9]+]], 20($sp)
|
||||
; GP32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]]
|
||||
; GP32: lw $[[T9:[0-9]+]], 16($sp)
|
||||
; GP32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]]
|
||||
; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T7]]
|
||||
; GP32: addu $3, $5, $[[T8]]
|
||||
; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]]
|
||||
; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T9]]
|
||||
; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T6]]
|
||||
; GP32: addu $2, $4, $[[T11]]
|
||||
; GP32: move $4, $[[T5]]
|
||||
; GP32: move $5, $[[T1]]
|
||||
|
|
@ -158,9 +158,9 @@ entry:
|
|||
; MM32: lw $[[T7:[0-9]+]], 20($sp)
|
||||
; MM32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]]
|
||||
; MM32: addu $[[T9:[0-9]+]], $5, $[[T8]]
|
||||
; MM32: sltu $[[T10:[0-9]+]], $[[T9]], $[[T7]]
|
||||
; MM32: lw $[[T11:[0-9]+]], 16($sp)
|
||||
; MM32: addu $[[T12:[0-9]+]], $[[T10]], $[[T11]]
|
||||
; MM32: lw $[[T10:[0-9]+]], 16($sp)
|
||||
; MM32: sltu $[[T11:[0-9]+]], $[[T9]], $[[T7]]
|
||||
; MM32: addu $[[T12:[0-9]+]], $[[T11]], $[[T10]]
|
||||
; MM32: addu $[[T13:[0-9]+]], $4, $[[T12]]
|
||||
; MM32: move $4, $[[T5]]
|
||||
; MM32: move $5, $[[T1]]
|
||||
|
|
|
|||
Loading…
Reference in New Issue