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[X86] Add a pattern for (i64 (and (anyext def32:), 0x00000000FFFFFFFF)) to produce SUBREG_TO_REG 

def32 here means the producing instruction zeroed bits 63:32. We already do this for zext, but it looks like we can get an and+anyext sometimes.

Spotted in the diffs from D33587.

llvm-svn: 352303
This commit is contained in:
Craig Topper 2019-01-27 03:37:05 +00:00
parent 6cff0cb35a
commit e65d4c5525
2 changed files with 2 additions and 1 deletions
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2
llvm/lib/Target/X86/X86InstrCompiler.td
View File

@ -1350,6 +1350,8 @@ def def32 : PatLeaf<(i32 GR32:$src), [{
// we can use a SUBREG_TO_REG.
def : Pat<(i64 (zext def32:$src)),
(SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)),
(SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
//===----------------------------------------------------------------------===//
// Pattern match OR as ADD

1
llvm/test/CodeGen/X86/zext-logicop-shift-load.ll
View File

@ -103,7 +103,6 @@ define i64 @test8(i8* %data) {
; CHECK-NEXT: movzwl %ax, %eax
; CHECK-NEXT: shrl $2, %eax
; CHECK-NEXT: orl $60, %eax
; CHECK-NEXT: movl %eax, %eax
; CHECK-NEXT: retq
entry:
%bf.load = load i8, i8* %data, align 4