diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 78fd09fbf387..12e002fe5215 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1263,10 +1263,14 @@ def : Pat<(seteq GPR:$rs1, 0), (SLTIU GPR:$rs1, 1)>;
 def : Pat<(seteq GPR:$rs1, GPR:$rs2), (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>;
 def : Pat<(seteq GPR:$rs1, simm12_plus1:$imm12),
           (SLTIU (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)), 1)>;
+def : Pat<(seteq GPR:$rs1, -2048),
+          (SLTIU (XORI GPR:$rs1, -2048), 1)>;
 def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>;
 def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>;
 def : Pat<(setne GPR:$rs1, simm12_plus1:$imm12),
           (SLTU X0, (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)))>;
+def : Pat<(setne GPR:$rs1, -2048),
+          (SLTU X0, (XORI GPR:$rs1, -2048))>;
 def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>;
 def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>;
 def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>;
diff --git a/llvm/test/CodeGen/RISCV/i32-icmp.ll b/llvm/test/CodeGen/RISCV/i32-icmp.ll
index deb7dfd883bf..3120f3a9b511 100644
--- a/llvm/test/CodeGen/RISCV/i32-icmp.ll
+++ b/llvm/test/CodeGen/RISCV/i32-icmp.ll
@@ -51,8 +51,7 @@ define i32 @icmp_eq_constant_2048(i32 %a) nounwind {
 define i32 @icmp_eq_constant_neg_2048(i32 %a) nounwind {
 ; RV32I-LABEL: icmp_eq_constant_neg_2048:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    li a1, -2048
-; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    xori a0, a0, -2048
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    ret
   %1 = icmp eq i32 %a, -2048
@@ -130,8 +129,7 @@ define i32 @icmp_ne_constant_2048(i32 %a) nounwind {
 define i32 @icmp_ne_constant_neg_2048(i32 %a) nounwind {
 ; RV32I-LABEL: icmp_ne_constant_neg_2048:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    li a1, -2048
-; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    xori a0, a0, -2048
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    ret
   %1 = icmp ne i32 %a, -2048
diff --git a/llvm/test/CodeGen/RISCV/i64-icmp.ll b/llvm/test/CodeGen/RISCV/i64-icmp.ll
index 503a4f1aff87..10d660af92f5 100644
--- a/llvm/test/CodeGen/RISCV/i64-icmp.ll
+++ b/llvm/test/CodeGen/RISCV/i64-icmp.ll
@@ -51,8 +51,7 @@ define i64 @icmp_eq_constant_2048(i64 %a) nounwind {
 define i64 @icmp_eq_constant_neg_2048(i64 %a) nounwind {
 ; RV64I-LABEL: icmp_eq_constant_neg_2048:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, -2048
-; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    xori a0, a0, -2048
 ; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    ret
   %1 = icmp eq i64 %a, -2048
@@ -130,8 +129,7 @@ define i64 @icmp_ne_constant_2048(i64 %a) nounwind {
 define i64 @icmp_ne_constant_neg_2048(i64 %a) nounwind {
 ; RV64I-LABEL: icmp_ne_constant_neg_2048:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, -2048
-; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    xori a0, a0, -2048
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    ret
   %1 = icmp ne i64 %a, -2048