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[RISCV] Add isel pattern for (setne/eq GPR, -2048) 

For constants in the range [-2047, 2048] we use addi. If the constant
is -2048 we can use xori. If we don't match this explicitly, we'll
emit an LI for the -2048 followed by an XOR.
This commit is contained in:
Craig Topper 2022-07-29 14:01:14 -07:00
parent b0f18af30b
commit e637feee80
3 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/RISCV/RISCVInstrInfo.td
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@ -1263,10 +1263,14 @@ def : Pat<(seteq GPR:$rs1, 0), (SLTIU GPR:$rs1, 1)>;
def : Pat<(seteq GPR:$rs1, GPR:$rs2), (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>;
def : Pat<(seteq GPR:$rs1, simm12_plus1:$imm12),
(SLTIU (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)), 1)>;
def : Pat<(seteq GPR:$rs1, -2048),
(SLTIU (XORI GPR:$rs1, -2048), 1)>;
def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>;
def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>;
def : Pat<(setne GPR:$rs1, simm12_plus1:$imm12),
(SLTU X0, (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)))>;
def : Pat<(setne GPR:$rs1, -2048),
(SLTU X0, (XORI GPR:$rs1, -2048))>;
def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>;
def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>;
def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>;

6
llvm/test/CodeGen/RISCV/i32-icmp.ll
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@ -51,8 +51,7 @@ define i32 @icmp_eq_constant_2048(i32 %a) nounwind {
define i32 @icmp_eq_constant_neg_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_eq_constant_neg_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: li a1, -2048
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: xori a0, a0, -2048
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret
%1 = icmp eq i32 %a, -2048
@ -130,8 +129,7 @@ define i32 @icmp_ne_constant_2048(i32 %a) nounwind {
define i32 @icmp_ne_constant_neg_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_ne_constant_neg_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: li a1, -2048
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: xori a0, a0, -2048
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: ret
%1 = icmp ne i32 %a, -2048

6
llvm/test/CodeGen/RISCV/i64-icmp.ll
View File

@ -51,8 +51,7 @@ define i64 @icmp_eq_constant_2048(i64 %a) nounwind {
define i64 @icmp_eq_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_constant_neg_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -2048
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: xori a0, a0, -2048
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = icmp eq i64 %a, -2048
@ -130,8 +129,7 @@ define i64 @icmp_ne_constant_2048(i64 %a) nounwind {
define i64 @icmp_ne_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_constant_neg_2048:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -2048
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: xori a0, a0, -2048
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%1 = icmp ne i64 %a, -2048