forked from OSchip/llvm-project
parent
a503fc0494
commit
e632cb3600
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@ -1361,7 +1361,7 @@ void Verifier::visitFenceInst(FenceInst &FI) {
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Assert1(Ordering == Acquire || Ordering == Release ||
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Ordering == AcquireRelease || Ordering == SequentiallyConsistent,
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"fence instructions may only have "
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" acquire, release, acq_rel, or seq_cst ordering.", &FI);
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"acquire, release, acq_rel, or seq_cst ordering.", &FI);
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visitInstruction(FI);
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}
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