forked from OSchip/llvm-project
[X86][SSE] Add partial dereferenceable vector load test inspired by PR21780
llvm-svn: 365145
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@ -4,10 +4,10 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
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;
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; Partial Vector Loads - PR16739
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;
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;
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; Partial Vector Loads - PR16739
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;
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define <4 x float> @load_float4_float3(<4 x float>* nocapture readonly dereferenceable(16)) {
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; SSE2-LABEL: load_float4_float3:
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@ -174,3 +174,41 @@ define <4 x float> @load_float4_float3_trunc(<4 x float>* nocapture readonly der
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%16 = insertelement <4 x float> %13, float %15, i32 2
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ret <4 x float> %16
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}
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; PR21780
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define <4 x double> @load_double4_0u2u(double* nocapture readonly dereferenceable(32)) {
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; SSE2-LABEL: load_double4_0u2u:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; SSE2-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
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; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
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; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0,0]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: load_double4_0u2u:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
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; SSSE3-NEXT: movddup {{.*#+}} xmm1 = mem[0,0]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: load_double4_0u2u:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
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; SSE41-NEXT: movddup {{.*#+}} xmm1 = mem[0,0]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: load_double4_0u2u:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
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; AVX-NEXT: retq
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%2 = load double, double* %0, align 8
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%3 = insertelement <4 x double> undef, double %2, i32 0
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%4 = getelementptr inbounds double, double* %0, i64 2
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%5 = load double, double* %4, align 8
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%6 = insertelement <4 x double> %3, double %5, i32 2
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%7 = shufflevector <4 x double> %6, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
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ret <4 x double> %7
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}
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