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[MSP430] Add RTLIB::[SRL/SRA/SHL]_I32 lowering to EABI lib calls 

Patch by Kristina Bessonova!

Differential Revision: https://reviews.llvm.org/D54626

llvm-svn: 347080
This commit is contained in:
Anton Korobeynikov 2018-11-16 19:36:15 +00:00
parent 3a38175723
commit e5cb1c35b4
2 changed files with 42 additions and 2 deletions
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9
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -217,8 +217,6 @@ MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
// { RTLIB::NEG_F64, "__mspabi_negd", ISD::SETCC_INVALID },
// { RTLIB::NEG_F32, "__mspabi_negf", ISD::SETCC_INVALID },
// TODO: SLL/SRA/SRL are in libgcc, RLL isn't
// Universal Integer Operations - EABI Table 9
{ RTLIB::SDIV_I16, "__mspabi_divi", ISD::SETCC_INVALID },
{ RTLIB::SDIV_I32, "__mspabi_divli", ISD::SETCC_INVALID },
@ -233,6 +231,13 @@ MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
{ RTLIB::UREM_I32, "__mspabi_remul", ISD::SETCC_INVALID },
{ RTLIB::UREM_I64, "__mspabi_remull", ISD::SETCC_INVALID },
// Bitwise Operations - EABI Table 10
// TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc
{ RTLIB::SRL_I32, "__mspabi_srll", ISD::SETCC_INVALID },
{ RTLIB::SRA_I32, "__mspabi_sral", ISD::SETCC_INVALID },
{ RTLIB::SHL_I32, "__mspabi_slll", ISD::SETCC_INVALID },
// __mspabi_[srlll/srall/sllll/rlli/rlll] are NOT implemented in libgcc
};
for (const auto &LC : LibraryCalls) {

35
llvm/test/CodeGen/MSP430/libcalls.ll
View File

@ -604,4 +604,39 @@ entry:
ret i64 %1
}
@i = external global i32, align 2
define i32 @srll() #0 {
entry:
; CHECK-LABEL: srll:
; CHECK: call #__mspabi_srll
%0 = load volatile i32, i32* @g_i32, align 2
%1 = load volatile i32, i32* @i, align 2
%shr = lshr i32 %0, %1
ret i32 %shr
}
define i32 @sral() #0 {
entry:
; CHECK-LABEL: sral:
; CHECK: call #__mspabi_sral
%0 = load volatile i32, i32* @g_i32, align 2
%1 = load volatile i32, i32* @i, align 2
%shr = ashr i32 %0, %1
ret i32 %shr
}
define i32 @slll() #0 {
entry:
; CHECK-LABEL: slll:
; CHECK: call #__mspabi_slll
%0 = load volatile i32, i32* @g_i32, align 2
%1 = load volatile i32, i32* @i, align 2
%shr = shl i32 %0, %1
ret i32 %shr
}
attributes #0 = { nounwind }