forked from OSchip/llvm-project
remove some damaged sign extend patterns that can never match.
llvm-svn: 98932
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6d984166fc
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@ -1133,16 +1133,14 @@ class XSBHInst<dag OOL, dag IOL, list<dag> pattern>:
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"xsbh\t$rDst, $rSrc",
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IntegerOp, pattern>;
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class XSBHVecInst<ValueType vectype>:
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XSBHInst<(outs VECREG:$rDst), (ins VECREG:$rSrc),
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[(set (v8i16 VECREG:$rDst), (sext (vectype VECREG:$rSrc)))]>;
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class XSBHInRegInst<RegisterClass rclass, list<dag> pattern>:
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XSBHInst<(outs rclass:$rDst), (ins rclass:$rSrc),
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pattern>;
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multiclass ExtendByteHalfword {
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def v16i8: XSBHVecInst<v8i16>;
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def v16i8: XSBHInst<(outs VECREG:$rDst), (ins VECREG:$rSrc),
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[
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/*(set (v8i16 VECREG:$rDst), (sext (v8i16 VECREG:$rSrc)))*/]>;
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def r8: XSBHInst<(outs R16C:$rDst), (ins R8C:$rSrc),
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[(set R16C:$rDst, (sext R8C:$rSrc))]>;
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def r16: XSBHInRegInst<R16C,
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@ -1200,8 +1198,8 @@ class XSWDInst<dag OOL, dag IOL, list<dag> pattern>:
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class XSWDVecInst<ValueType in_vectype, ValueType out_vectype>:
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XSWDInst<(outs VECREG:$rDst), (ins VECREG:$rSrc),
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[(set (out_vectype VECREG:$rDst),
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(sext (out_vectype VECREG:$rSrc)))]>;
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[/*(set (out_vectype VECREG:$rDst),
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(sext (out_vectype VECREG:$rSrc)))*/]>;
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class XSWDRegInst<RegisterClass in_rclass, RegisterClass out_rclass>:
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XSWDInst<(outs out_rclass:$rDst), (ins in_rclass:$rSrc),
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@ -4146,7 +4144,7 @@ def CFSif32 :
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def FESDvec :
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RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA),
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"fesd\t$rT, $rA", SPrecFP,
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[(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))]>;
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[/*(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))*/]>;
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def FESDf32 :
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RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA),
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