forked from OSchip/llvm-project
Add inc + dec patterns which fold load + stores.
llvm-svn: 24686
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@ -715,9 +715,12 @@ def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst",
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[(set R32:$dst, (add R32:$src, 1))]>;
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}
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let isTwoAddress = 0 in {
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def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst", []>;
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def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst", []>, OpSize;
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def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst", []>;
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def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst",
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[(store (add (i8 (load addr:$dst)), 1), addr:$dst)]>;
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def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst",
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[(store (add (i16 (load addr:$dst)), 1), addr:$dst)]>, OpSize;
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def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst",
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[(store (add (i32 (load addr:$dst)), 1), addr:$dst)]>;
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}
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def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst",
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@ -730,9 +733,12 @@ def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst",
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}
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let isTwoAddress = 0 in {
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def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst", []>;
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def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst", []>, OpSize;
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def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst", []>;
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def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst",
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[(store (add (i8 (load addr:$dst)), -1), addr:$dst)]>;
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def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst",
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[(store (add (i16 (load addr:$dst)), -1), addr:$dst)]>, OpSize;
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def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst",
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[(store (add (i32 (load addr:$dst)), -1), addr:$dst)]>;
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}
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// Logical operators...
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