[X86][NFC] Generate fields and getters for subtarget features

Non-duplicated comments are moved from X86Subtarget.h to X86.td.
This is a follow-up patch for D120906.

llvm/lib/Target/X86/X86.td

@@ -18,7 +18,7 @@ include "llvm/Target/Target.td"
 //===----------------------------------------------------------------------===//
 // X86 Subtarget state
 //
-
+// disregarding specific ABI / programming model
 def Is64Bit : SubtargetFeature<"64bit-mode", "Is64Bit", "true",
                                "64-bit mode (x86_64)">;
 def Is32Bit : SubtargetFeature<"32bit-mode", "Is32Bit", "true",
@@ -34,7 +34,7 @@ def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
                                       "Enable X87 float instructions">;
 
 def FeatureNOPL    : SubtargetFeature<"nopl", "HasNOPL", "true",
-                                      "Enable NOPL instruction">;
+                                      "Enable NOPL instruction (generally pentium pro+)">;
 
 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMOV", "true",
                                       "Enable conditional move instructions">;
@@ -43,7 +43,7 @@ def FeatureCX8     : SubtargetFeature<"cx8", "HasCX8", "true",
                                       "Support CMPXCHG8B instructions">;
 
 def FeatureCRC32   : SubtargetFeature<"crc32", "HasCRC32", "true",
-                                      "Enable SSE 4.2 CRC32 instruction">;
+                                      "Enable SSE 4.2 CRC32 instruction (used when SSE4.2 is supported but function is GPR only)">;
 
 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
                                        "Support POPCNT instruction">;
@@ -101,7 +101,7 @@ def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
 def FeatureX86_64   : SubtargetFeature<"64bit", "HasX86_64", "true",
                                       "Support 64-bit instructions">;
 def FeatureCX16     : SubtargetFeature<"cx16", "HasCX16", "true",
-                                       "64-bit with cmpxchg16b",
+                                       "64-bit with cmpxchg16b (this is true for most x86-64 chips, but not the first AMD chips)",
                                        [FeatureCX8]>;
 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
                                       "Support SSE 4a instructions",
@@ -198,7 +198,7 @@ def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
                                       [FeatureFMA4]>;
 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
                                           "HasSSEUnalignedMem", "true",
-                      "Allow unaligned memory operands with SSE instructions">;
+                      "Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)">;
 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
                                       "Enable AES instructions",
                                       [FeatureSSE2]>;
@@ -228,6 +228,8 @@ def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
                                       "Enable SHA instructions",
                                       [FeatureSSE2]>;
+// Processor supports CET SHSTK - Control-Flow Enforcement Technology
+// using Shadow Stack
 def FeatureSHSTK   : SubtargetFeature<"shstk", "HasSHSTK", "true",
                        "Support CET Shadow-Stack instructions">;
 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
@@ -241,7 +243,7 @@ def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
 def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
                                       "Enable Cache Line Zero">;
 def FeatureCLDEMOTE  : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
-                                      "Enable Cache Demote">;
+                                      "Enable Cache Line Demote">;
 def FeaturePTWRITE  : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
                                       "Support ptwrite instruction">;
 def FeatureAMXTILE     : SubtargetFeature<"amx-tile", "HasAMXTILE", "true",
@@ -285,9 +287,9 @@ def FeatureUINTR : SubtargetFeature<"uintr", "HasUINTR", "true",
 def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",
                                       "platform configuration instruction">;
 def FeatureMOVDIRI  : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
-                                       "Support movdiri instruction">;
+                                       "Support movdiri instruction (direct store integer)">;
 def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",
-                                        "Support movdir64b instruction">;
+                                        "Support movdir64b instruction (direct store 64 bytes)">;
 
 // Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
 // "string operations"). See "REP String Enhancement" in the Intel Software
@@ -388,7 +390,7 @@ def TuningSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
                                        "SHLD instruction is slow">;
 
 def TuningSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
-                                        "PMULLD instruction is slow">;
+                                        "PMULLD instruction is slow (compared to PMULLW/PMULHW and PMULUDQ)">;
 
 def TuningSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow",
                                           "true",
@@ -404,19 +406,23 @@ def TuningSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
                                 "Slow unaligned 32-byte memory access">;
 
 def TuningLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
-                                     "Use LEA for adjusting the stack pointer">;
+                                     "Use LEA for adjusting the stack pointer (this is an optimization for Intel Atom processors)">;
 
+// True if 8-bit divisions are significantly faster than
+// 32-bit divisions and should be used when possible.
 def TuningSlowDivide32 : SubtargetFeature<"idivl-to-divb",
                                      "HasSlowDivide32", "true",
                                      "Use 8-bit divide for positive values less than 256">;
 
+// True if 32-bit divides are significantly faster than
+// 64-bit divisions and should be used when possible.
 def TuningSlowDivide64 : SubtargetFeature<"idivq-to-divl",
                                      "HasSlowDivide64", "true",
                                      "Use 32-bit divide for positive values less than 2^32">;
 
 def TuningPadShortFunctions : SubtargetFeature<"pad-short-functions",
                                      "PadShortFunctions", "true",
-                                     "Pad short functions">;
+                                     "Pad short functions (to prevent a stall when returning too early)">;
 
 // On some processors, instructions that implicitly take two memory operands are
 // slow. In practice, this means that CALL, PUSH, and POP with memory operands
@@ -425,15 +431,21 @@ def TuningSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
                                      "SlowTwoMemOps", "true",
                                      "Two memory operand instructions are slow">;
 
+// True if the LEA instruction inputs have to be ready at address generation
+// (AG) time.
 def TuningLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LeaUsesAG", "true",
                                    "LEA instruction needs inputs at AG stage">;
 
 def TuningSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
                                    "LEA instruction with certain arguments is slow">;
 
+// True if the LEA instruction has all three source operands: base, index,
+// and offset or if the LEA instruction uses base and index registers where
+// the base is EBP, RBP,or R13
 def TuningSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
                                    "LEA instruction with 3 ops or certain registers is slow">;
 
+// True if INC and DEC instructions are slow when writing to flags
 def TuningSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
                                    "INC and DEC instructions are slower than ADD and SUB">;
 
@@ -474,9 +486,14 @@ def TuningInsertVZEROUPPER
 // vectorized code we should care about the throughput of SQRT operations.
 // But if the code is scalar that probably means that the code has some kind of
 // dependency and we should care more about reducing the latency.
+
+// True if hardware SQRTSS instruction is at least as fast (latency) as
+// RSQRTSS followed by a Newton-Raphson iteration.
 def TuningFastScalarFSQRT
     : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
                        "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
+// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
+// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
 def TuningFastVectorFSQRT
     : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
                        "true", "Vector SQRT is fast (disable Newton-Raphson)">;
@@ -533,7 +550,7 @@ def TuningMacroFusion
 // similar to Skylake Server (AVX-512).
 def TuningFastGather
     : SubtargetFeature<"fast-gather", "HasFastGather", "true",
-                       "Indicates if gather is reasonably fast">;
+                       "Indicates if gather is reasonably fast (this is true for Skylake client and all AVX-512 CPUs)">;
 
 def TuningPrefer128Bit
     : SubtargetFeature<"prefer-128-bit", "Prefer128Bit", "true",

llvm/lib/Target/X86/X86Subtarget.h

@@ -69,416 +69,9 @@ class X86Subtarget final : public X86GenSubtargetInfo {
   /// MMX, 3DNow, 3DNow Athlon, or none supported.
   X863DNowEnum X863DNowLevel = NoThreeDNow;
 
-  /// Is this a Intel Atom processor?
+#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER)                    \
-  bool IsAtom = false;
+  bool ATTRIBUTE = DEFAULT;
-
+#include "X86GenSubtargetInfo.inc"
-  /// True if the processor supports X87 instructions.
-  bool HasX87 = false;
-
-  /// True if the processor supports CMPXCHG8B.
-  bool HasCX8 = false;
-
-  /// True if this processor has NOPL instruction
-  /// (generally pentium pro+).
-  bool HasNOPL = false;
-
-  /// True if this processor has conditional move instructions
-  /// (generally pentium pro+).
-  bool HasCMOV = false;
-
-  /// True if the processor supports X86-64 instructions.
-  bool HasX86_64 = false;
-
-  /// True if the processor supports POPCNT.
-  bool HasPOPCNT = false;
-
-  /// True if the processor supports SSE4A instructions.
-  bool HasSSE4A = false;
-
-  /// Target has AES instructions
-  bool HasAES = false;
-  bool HasVAES = false;
-
-  /// Target has FXSAVE/FXRESTOR instructions
-  bool HasFXSR = false;
-
-  /// Target has XSAVE instructions
-  bool HasXSAVE = false;
-
-  /// Target has XSAVEOPT instructions
-  bool HasXSAVEOPT = false;
-
-  /// Target has XSAVEC instructions
-  bool HasXSAVEC = false;
-
-  /// Target has XSAVES instructions
-  bool HasXSAVES = false;
-
-  /// Target has carry-less multiplication
-  bool HasPCLMUL = false;
-  bool HasVPCLMULQDQ = false;
-
-  /// Target has Galois Field Arithmetic instructions
-  bool HasGFNI = false;
-
-  /// Target has 3-operand fused multiply-add
-  bool HasFMA = false;
-
-  /// Target has 4-operand fused multiply-add
-  bool HasFMA4 = false;
-
-  /// Target has XOP instructions
-  bool HasXOP = false;
-
-  /// Target has TBM instructions.
-  bool HasTBM = false;
-
-  /// Target has LWP instructions
-  bool HasLWP = false;
-
-  /// True if the processor has the MOVBE instruction.
-  bool HasMOVBE = false;
-
-  /// True if the processor has the RDRAND instruction.
-  bool HasRDRAND = false;
-
-  /// Processor has 16-bit floating point conversion instructions.
-  bool HasF16C = false;
-
-  /// Processor has FS/GS base insturctions.
-  bool HasFSGSBase = false;
-
-  /// Processor has LZCNT instruction.
-  bool HasLZCNT = false;
-
-  /// Processor has BMI1 instructions.
-  bool HasBMI = false;
-
-  /// Processor has BMI2 instructions.
-  bool HasBMI2 = false;
-
-  /// Processor has VBMI instructions.
-  bool HasVBMI = false;
-
-  /// Processor has VBMI2 instructions.
-  bool HasVBMI2 = false;
-
-  /// Processor has Integer Fused Multiply Add
-  bool HasIFMA = false;
-
-  /// Processor has RTM instructions.
-  bool HasRTM = false;
-
-  /// Processor has ADX instructions.
-  bool HasADX = false;
-
-  /// Processor has SHA instructions.
-  bool HasSHA = false;
-
-  /// Processor has PRFCHW instructions.
-  bool HasPRFCHW = false;
-
-  /// Processor has RDSEED instructions.
-  bool HasRDSEED = false;
-
-  /// Processor has LAHF/SAHF instructions in 64-bit mode.
-  bool HasLAHFSAHF64 = false;
-
-  /// Processor has MONITORX/MWAITX instructions.
-  bool HasMWAITX = false;
-
-  /// Processor has Cache Line Zero instruction
-  bool HasCLZERO = false;
-
-  /// Processor has Cache Line Demote instruction
-  bool HasCLDEMOTE = false;
-
-  /// Processor has MOVDIRI instruction (direct store integer).
-  bool HasMOVDIRI = false;
-
-  /// Processor has MOVDIR64B instruction (direct store 64 bytes).
-  bool HasMOVDIR64B = false;
-
-  /// Processor has ptwrite instruction.
-  bool HasPTWRITE = false;
-
-  /// Processor has Prefetch with intent to Write instruction
-  bool HasPREFETCHWT1 = false;
-
-  /// True if SHLD instructions are slow.
-  bool IsSHLDSlow = false;
-
-  /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
-  //  PMULUDQ.
-  bool IsPMULLDSlow = false;
-
-  /// True if the PMADDWD instruction is slow compared to PMULLD.
-  bool IsPMADDWDSlow = false;
-
-  /// True if unaligned memory accesses of 16-bytes are slow.
-  bool IsUnalignedMem16Slow = false;
-
-  /// True if unaligned memory accesses of 32-bytes are slow.
-  bool IsUnalignedMem32Slow = false;
-
-  /// True if SSE operations can have unaligned memory operands.
-  /// This may require setting a configuration bit in the processor.
-  bool HasSSEUnalignedMem = false;
-
-  /// True if this processor has the CMPXCHG16B instruction;
-  /// this is true for most x86-64 chips, but not the first AMD chips.
-  bool HasCX16 = false;
-
-  /// True if the LEA instruction should be used for adjusting
-  /// the stack pointer. This is an optimization for Intel Atom processors.
-  bool UseLeaForSP = false;
-
-  /// True if POPCNT instruction has a false dependency on the destination register.
-  bool HasPOPCNTFalseDeps = false;
-
-  /// True if LZCNT/TZCNT instructions have a false dependency on the destination register.
-  bool HasLZCNTFalseDeps = false;
-
-  /// True if an SBB instruction with same source register is recognized as
-  /// having no dependency on that register.
-  bool HasSBBDepBreaking = false;
-
-  /// True if its preferable to combine to a single cross-lane shuffle
-  /// using a variable mask over multiple fixed shuffles.
-  bool HasFastVariableCrossLaneShuffle = false;
-
-  /// True if its preferable to combine to a single per-lane shuffle
-  /// using a variable mask over multiple fixed shuffles.
-  bool HasFastVariablePerLaneShuffle = false;
-
-  /// True if vzeroupper instructions should be inserted after code that uses
-  /// ymm or zmm registers.
-  bool InsertVZEROUPPER = false;
-
-  /// True if there is no performance penalty for writing NOPs with up to
-  /// 7 bytes.
-  bool HasFast7ByteNOP = false;
-
-  /// True if there is no performance penalty for writing NOPs with up to
-  /// 11 bytes.
-  bool HasFast11ByteNOP = false;
-
-  /// True if there is no performance penalty for writing NOPs with up to
-  /// 15 bytes.
-  bool HasFast15ByteNOP = false;
-
-  /// True if gather is reasonably fast. This is true for Skylake client and
-  /// all AVX-512 CPUs.
-  bool HasFastGather = false;
-
-  /// True if hardware SQRTSS instruction is at least as fast (latency) as
-  /// RSQRTSS followed by a Newton-Raphson iteration.
-  bool HasFastScalarFSQRT = false;
-
-  /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
-  /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
-  bool HasFastVectorFSQRT = false;
-
-  /// True if 8-bit divisions are significantly faster than
-  /// 32-bit divisions and should be used when possible.
-  bool HasSlowDivide32 = false;
-
-  /// True if 32-bit divides are significantly faster than
-  /// 64-bit divisions and should be used when possible.
-  bool HasSlowDivide64 = false;
-
-  /// True if LZCNT instruction is fast.
-  bool HasFastLZCNT = false;
-
-  /// True if SHLD based rotate is fast.
-  bool HasFastSHLDRotate = false;
-
-  /// True if the processor supports macrofusion.
-  bool HasMacroFusion = false;
-
-  /// True if the processor supports branch fusion.
-  bool HasBranchFusion = false;
-
-  /// True if the processor has enhanced REP MOVSB/STOSB.
-  bool HasERMSB = false;
-
-  /// True if the processor has fast short REP MOV.
-  bool HasFSRM = false;
-
-  /// True if the short functions should be padded to prevent
-  /// a stall when returning too early.
-  bool PadShortFunctions = false;
-
-  /// True if two memory operand instructions should use a temporary register
-  /// instead.
-  bool SlowTwoMemOps = false;
-
-  /// True if the LEA instruction inputs have to be ready at address generation
-  /// (AG) time.
-  bool LeaUsesAG = false;
-
-  /// True if the LEA instruction with certain arguments is slow
-  bool SlowLEA = false;
-
-  /// True if the LEA instruction has all three source operands: base, index,
-  /// and offset or if the LEA instruction uses base and index registers where
-  /// the base is EBP, RBP,or R13
-  bool Slow3OpsLEA = false;
-
-  /// True if INC and DEC instructions are slow when writing to flags
-  bool SlowIncDec = false;
-
-  /// Processor has AVX-512 PreFetch Instructions
-  bool HasPFI = false;
-
-  /// Processor has AVX-512 Exponential and Reciprocal Instructions
-  bool HasERI = false;
-
-  /// Processor has AVX-512 Conflict Detection Instructions
-  bool HasCDI = false;
-
-  /// Processor has AVX-512 population count Instructions
-  bool HasVPOPCNTDQ = false;
-
-  /// Processor has AVX-512 Doubleword and Quadword instructions
-  bool HasDQI = false;
-
-  /// Processor has AVX-512 Byte and Word instructions
-  bool HasBWI = false;
-
-  /// Processor has AVX-512 Vector Length eXtenstions
-  bool HasVLX = false;
-
-  /// Processor has AVX-512 16 bit floating-point extenstions
-  bool HasFP16 = false;
-
-  /// Processor has PKU extenstions
-  bool HasPKU = false;
-
-  /// Processor has AVX-512 Vector Neural Network Instructions
-  bool HasVNNI = false;
-
-  /// Processor has AVX Vector Neural Network Instructions
-  bool HasAVXVNNI = false;
-
-  /// Processor has AVX-512 bfloat16 floating-point extensions
-  bool HasBF16 = false;
-
-  /// Processor supports ENQCMD instructions
-  bool HasENQCMD = false;
-
-  /// Processor has AVX-512 Bit Algorithms instructions
-  bool HasBITALG = false;
-
-  /// Processor has AVX-512 vp2intersect instructions
-  bool HasVP2INTERSECT = false;
-
-  /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
-  /// using Shadow Stack
-  bool HasSHSTK = false;
-
-  /// Processor supports Invalidate Process-Context Identifier
-  bool HasINVPCID = false;
-
-  /// Processor has Software Guard Extensions
-  bool HasSGX = false;
-
-  /// Processor supports Flush Cache Line instruction
-  bool HasCLFLUSHOPT = false;
-
-  /// Processor supports Cache Line Write Back instruction
-  bool HasCLWB = false;
-
-  /// Processor supports Write Back No Invalidate instruction
-  bool HasWBNOINVD = false;
-
-  /// Processor support RDPID instruction
-  bool HasRDPID = false;
-
-  /// Processor supports WaitPKG instructions
-  bool HasWAITPKG = false;
-
-  /// Processor supports PCONFIG instruction
-  bool HasPCONFIG = false;
-
-  /// Processor support key locker instructions
-  bool HasKL = false;
-
-  /// Processor support key locker wide instructions
-  bool HasWIDEKL = false;
-
-  /// Processor supports HRESET instruction
-  bool HasHRESET = false;
-
-  /// Processor supports SERIALIZE instruction
-  bool HasSERIALIZE = false;
-
-  /// Processor supports TSXLDTRK instruction
-  bool HasTSXLDTRK = false;
-
-  /// Processor has AMX support
-  bool HasAMXTILE = false;
-  bool HasAMXBF16 = false;
-  bool HasAMXINT8 = false;
-
-  /// Processor supports User Level Interrupt instructions
-  bool HasUINTR = false;
-
-  /// Enable SSE4.2 CRC32 instruction (Used when SSE4.2 is supported but
-  /// function is GPR only)
-  bool HasCRC32 = false;
-
-  /// Processor has a single uop BEXTR implementation.
-  bool HasFastBEXTR = false;
-
-  /// Try harder to combine to horizontal vector ops if they are fast.
-  bool HasFastHorizontalOps = false;
-
-  /// Prefer a left/right scalar logical shifts pair over a shift+and pair.
-  bool HasFastScalarShiftMasks = false;
-
-  /// Prefer a left/right vector logical shifts pair over a shift+and pair.
-  bool HasFastVectorShiftMasks = false;
-
-  /// Prefer a movbe over a single-use load + bswap / single-use bswap + store.
-  bool HasFastMOVBE = false;
-
-  /// Use a retpoline thunk rather than indirect calls to block speculative
-  /// execution.
-  bool UseRetpolineIndirectCalls = false;
-
-  /// Use a retpoline thunk or remove any indirect branch to block speculative
-  /// execution.
-  bool UseRetpolineIndirectBranches = false;
-
-  /// Deprecated flag, query `UseRetpolineIndirectCalls` and
-  /// `UseRetpolineIndirectBranches` instead.
-  bool DeprecatedUseRetpoline = false;
-
-  /// When using a retpoline thunk, call an externally provided thunk rather
-  /// than emitting one inside the compiler.
-  bool UseRetpolineExternalThunk = false;
-
-  /// Prevent generation of indirect call/branch instructions from memory,
-  /// and force all indirect call/branch instructions from a register to be
-  /// preceded by an LFENCE. Also decompose RET instructions into a
-  /// POP+LFENCE+JMP sequence.
-  bool UseLVIControlFlowIntegrity = false;
-
-  /// Enable Speculative Execution Side Effect Suppression
-  bool UseSpeculativeExecutionSideEffectSuppression = false;
-
-  /// Insert LFENCE instructions to prevent data speculatively injected into
-  /// loads from being used maliciously.
-  bool UseLVILoadHardening = false;
-
-  /// Use an instruction sequence for taking the address of a global that allows
-  /// a memory tag in the upper address bits.
-  bool AllowTaggedGlobals = false;
-
-  /// Use software floating point for code generation.
-  bool UseSoftFloat = false;
-
   /// The minimum alignment known to hold of the stack frame on
   /// entry to the function and which must be maintained by every function.
   Align stackAlignment = Align(4);
@@ -490,21 +83,6 @@ class X86Subtarget final : public X86GenSubtargetInfo {
   // FIXME: this is a known good value for Yonah. How about others?
   unsigned MaxInlineSizeThreshold = 128;
 
-  /// Indicates target prefers 128 bit instructions.
-  bool Prefer128Bit = false;
-
-  /// Indicates target prefers 256 bit instructions.
-  bool Prefer256Bit = false;
-
-  /// Indicates target prefers AVX512 mask registers.
-  bool PreferMaskRegisters = false;
-
-  /// Use Silvermont specific arithmetic costs.
-  bool UseSLMArithCosts = false;
-
-  /// Use Goldmont specific floating point div/sqrt costs.
-  bool UseGLMDivSqrtCosts = false;
-
   /// What processor and OS we're targeting.
   Triple TargetTriple;
 
@@ -514,7 +92,6 @@ class X86Subtarget final : public X86GenSubtargetInfo {
   std::unique_ptr<RegisterBankInfo> RegBankInfo;
   std::unique_ptr<InstructionSelector> InstSelector;
 
-private:
   /// Override the stack alignment.
   MaybeAlign StackAlignOverride;
 
@@ -528,15 +105,6 @@ private:
   /// Required vector width from function attribute.
   unsigned RequiredVectorWidth;
 
-  /// True if compiling for 64-bit, false for 16-bit or 32-bit.
-  bool Is64Bit = false;
-
-  /// True if compiling for 32-bit, false for 16-bit or 64-bit.
-  bool Is32Bit = false;
-
-  /// True if compiling for 16-bit, false for 32-bit or 64-bit.
-  bool Is16Bit = false;
-
   X86SelectionDAGInfo TSInfo;
   // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
   // X86TargetLowering needs.
@@ -602,18 +170,10 @@ private:
   void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 
 public:
-  /// Is this x86_64? (disregarding specific ABI / programming model)
-  bool is64Bit() const {
-    return Is64Bit;
-  }
 
-  bool is32Bit() const {
+#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER)                    \
-    return Is32Bit;
+  bool GETTER() const { return ATTRIBUTE; }
-  }
+#include "X86GenSubtargetInfo.inc"
-
-  bool is16Bit() const {
-    return Is16Bit;
-  }
 
   /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
   bool isTarget64BitILP32() const {
@@ -628,16 +188,11 @@ public:
   PICStyles::Style getPICStyle() const { return PICStyle; }
   void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
 
-  bool hasX87() const { return HasX87; }
-  bool hasCX8() const { return HasCX8; }
-  bool hasCX16() const { return HasCX16; }
   bool canUseCMPXCHG8B() const { return hasCX8(); }
   bool canUseCMPXCHG16B() const {
     // CX16 is just the CPUID bit, instruction requires 64-bit mode too.
     return hasCX16() && is64Bit();
   }
-  bool hasNOPL() const { return HasNOPL; }
-  bool hasCMOV() const { return HasCMOV; }
   // SSE codegen depends on cmovs, and all SSE1+ processors support them.
   // All 64-bit processors support cmov.
   bool canUseCMOV() const { return hasCMOV() || hasSSE1() || is64Bit(); }
@@ -651,44 +206,10 @@ public:
   bool hasAVX2() const { return X86SSELevel >= AVX2; }
   bool hasAVX512() const { return X86SSELevel >= AVX512; }
   bool hasInt256() const { return hasAVX2(); }
-  bool hasSSE4A() const { return HasSSE4A; }
   bool hasMMX() const { return X863DNowLevel >= MMX; }
   bool hasThreeDNow() const { return X863DNowLevel >= ThreeDNow; }
   bool hasThreeDNowA() const { return X863DNowLevel >= ThreeDNowA; }
-  bool hasPOPCNT() const { return HasPOPCNT; }
-  bool hasAES() const { return HasAES; }
-  bool hasVAES() const { return HasVAES; }
-  bool hasFXSR() const { return HasFXSR; }
-  bool hasXSAVE() const { return HasXSAVE; }
-  bool hasXSAVEOPT() const { return HasXSAVEOPT; }
-  bool hasXSAVEC() const { return HasXSAVEC; }
-  bool hasXSAVES() const { return HasXSAVES; }
-  bool hasPCLMUL() const { return HasPCLMUL; }
-  bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
-  bool hasGFNI() const { return HasGFNI; }
-  // Prefer FMA4 to FMA - its better for commutation/memory folding and
-  // has equal or better performance on all supported targets.
-  bool hasFMA() const { return HasFMA; }
-  bool hasFMA4() const { return HasFMA4; }
   bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
-  bool hasXOP() const { return HasXOP; }
-  bool hasTBM() const { return HasTBM; }
-  bool hasLWP() const { return HasLWP; }
-  bool hasMOVBE() const { return HasMOVBE; }
-  bool hasRDRAND() const { return HasRDRAND; }
-  bool hasF16C() const { return HasF16C; }
-  bool hasFSGSBase() const { return HasFSGSBase; }
-  bool hasLZCNT() const { return HasLZCNT; }
-  bool hasBMI() const { return HasBMI; }
-  bool hasBMI2() const { return HasBMI2; }
-  bool hasVBMI() const { return HasVBMI; }
-  bool hasVBMI2() const { return HasVBMI2; }
-  bool hasIFMA() const { return HasIFMA; }
-  bool hasRTM() const { return HasRTM; }
-  bool hasADX() const { return HasADX; }
-  bool hasSHA() const { return HasSHA; }
-  bool hasPRFCHW() const { return HasPRFCHW; }
-  bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
   bool hasPrefetchW() const {
     // The PREFETCHW instruction was added with 3DNow but later CPUs gave it
     // its own CPUID bit as part of deprecating 3DNow. Intel eventually added
@@ -702,94 +223,7 @@ public:
     // 3dnow.
     return hasSSE1() || (hasPRFCHW() && !hasThreeDNow()) || hasPREFETCHWT1();
   }
-  bool hasRDSEED() const { return HasRDSEED; }
+  bool canUseLAHFSAHF() const { return hasLAHFSAHF64() || !is64Bit(); }
-  bool hasLAHFSAHF() const { return HasLAHFSAHF64; }
-  bool canUseLAHFSAHF() const { return hasLAHFSAHF() || !is64Bit(); }
-  bool hasMWAITX() const { return HasMWAITX; }
-  bool hasCLZERO() const { return HasCLZERO; }
-  bool hasCLDEMOTE() const { return HasCLDEMOTE; }
-  bool hasMOVDIRI() const { return HasMOVDIRI; }
-  bool hasMOVDIR64B() const { return HasMOVDIR64B; }
-  bool hasPTWRITE() const { return HasPTWRITE; }
-  bool isSHLDSlow() const { return IsSHLDSlow; }
-  bool isPMULLDSlow() const { return IsPMULLDSlow; }
-  bool isPMADDWDSlow() const { return IsPMADDWDSlow; }
-  bool isUnalignedMem16Slow() const { return IsUnalignedMem16Slow; }
-  bool isUnalignedMem32Slow() const { return IsUnalignedMem32Slow; }
-  bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
-  bool useLeaForSP() const { return UseLeaForSP; }
-  bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; }
-  bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; }
-  bool hasSBBDepBreaking() const { return HasSBBDepBreaking; }
-  bool hasFastVariableCrossLaneShuffle() const {
-    return HasFastVariableCrossLaneShuffle;
-  }
-  bool hasFastVariablePerLaneShuffle() const {
-    return HasFastVariablePerLaneShuffle;
-  }
-  bool insertVZEROUPPER() const { return InsertVZEROUPPER; }
-  bool hasFastGather() const { return HasFastGather; }
-  bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
-  bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
-  bool hasFastLZCNT() const { return HasFastLZCNT; }
-  bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
-  bool hasFastBEXTR() const { return HasFastBEXTR; }
-  bool hasFastHorizontalOps() const { return HasFastHorizontalOps; }
-  bool hasFastScalarShiftMasks() const { return HasFastScalarShiftMasks; }
-  bool hasFastVectorShiftMasks() const { return HasFastVectorShiftMasks; }
-  bool hasFastMOVBE() const { return HasFastMOVBE; }
-  bool hasMacroFusion() const { return HasMacroFusion; }
-  bool hasBranchFusion() const { return HasBranchFusion; }
-  bool hasERMSB() const { return HasERMSB; }
-  bool hasFSRM() const { return HasFSRM; }
-  bool hasSlowDivide32() const { return HasSlowDivide32; }
-  bool hasSlowDivide64() const { return HasSlowDivide64; }
-  bool padShortFunctions() const { return PadShortFunctions; }
-  bool slowTwoMemOps() const { return SlowTwoMemOps; }
-  bool leaUsesAG() const { return LeaUsesAG; }
-  bool slowLEA() const { return SlowLEA; }
-  bool slow3OpsLEA() const { return Slow3OpsLEA; }
-  bool slowIncDec() const { return SlowIncDec; }
-  bool hasCDI() const { return HasCDI; }
-  bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
-  bool hasPFI() const { return HasPFI; }
-  bool hasERI() const { return HasERI; }
-  bool hasDQI() const { return HasDQI; }
-  bool hasBWI() const { return HasBWI; }
-  bool hasVLX() const { return HasVLX; }
-  bool hasFP16() const { return HasFP16; }
-  bool hasPKU() const { return HasPKU; }
-  bool hasVNNI() const { return HasVNNI; }
-  bool hasBF16() const { return HasBF16; }
-  bool hasVP2INTERSECT() const { return HasVP2INTERSECT; }
-  bool hasBITALG() const { return HasBITALG; }
-  bool hasSHSTK() const { return HasSHSTK; }
-  bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
-  bool hasCLWB() const { return HasCLWB; }
-  bool hasWBNOINVD() const { return HasWBNOINVD; }
-  bool hasRDPID() const { return HasRDPID; }
-  bool hasWAITPKG() const { return HasWAITPKG; }
-  bool hasPCONFIG() const { return HasPCONFIG; }
-  bool hasSGX() const { return HasSGX; }
-  bool hasINVPCID() const { return HasINVPCID; }
-  bool hasENQCMD() const { return HasENQCMD; }
-  bool hasKL() const { return HasKL; }
-  bool hasWIDEKL() const { return HasWIDEKL; }
-  bool hasHRESET() const { return HasHRESET; }
-  bool hasSERIALIZE() const { return HasSERIALIZE; }
-  bool hasTSXLDTRK() const { return HasTSXLDTRK; }
-  bool hasUINTR() const { return HasUINTR; }
-  bool hasCRC32() const { return HasCRC32; }
-  bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
-  bool useRetpolineIndirectBranches() const {
-    return UseRetpolineIndirectBranches;
-  }
-  bool hasAVXVNNI() const { return HasAVXVNNI; }
-  bool hasAMXTILE() const { return HasAMXTILE; }
-  bool hasAMXBF16() const { return HasAMXBF16; }
-  bool hasAMXINT8() const { return HasAMXINT8; }
-  bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
-
   // These are generic getters that OR together all of the thunk types
   // supported by the subtarget. Therefore useIndirectThunk*() will return true
   // if any respective thunk feature is enabled.
@@ -800,16 +234,6 @@ public:
     return useRetpolineIndirectBranches() || useLVIControlFlowIntegrity();
   }
 
-  bool preferMaskRegisters() const { return PreferMaskRegisters; }
-  bool useSLMArithCosts() const { return UseSLMArithCosts; }
-  bool useGLMDivSqrtCosts() const { return UseGLMDivSqrtCosts; }
-  bool useLVIControlFlowIntegrity() const { return UseLVIControlFlowIntegrity; }
-  bool allowTaggedGlobals() const { return AllowTaggedGlobals; }
-  bool useLVILoadHardening() const { return UseLVILoadHardening; }
-  bool useSpeculativeExecutionSideEffectSuppression() const {
-    return UseSpeculativeExecutionSideEffectSuppression;
-  }
-
   unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
   unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
 
@@ -836,10 +260,6 @@ public:
 
   bool isXRaySupported() const override { return is64Bit(); }
 
-  /// TODO: to be removed later and replaced with suitable properties
-  bool isAtom() const { return IsAtom; }
-  bool useSoftFloat() const { return UseSoftFloat; }
-
   /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
   /// no-sse2). There isn't any reason to disable it if the target processor
   /// supports it.