forked from OSchip/llvm-project
[X86][NFC] Generate fields and getters for subtarget features
Non-duplicated comments are moved from X86Subtarget.h to X86.td. This is a follow-up patch for D120906.
This commit is contained in:
Shengchen Kan
parent
8271220a99
commit
e58dadf3e2
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@ -18,7 +18,7 @@ include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// X86 Subtarget state
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//
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// disregarding specific ABI / programming model
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def Is64Bit : SubtargetFeature<"64bit-mode", "Is64Bit", "true",
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"64-bit mode (x86_64)">;
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def Is32Bit : SubtargetFeature<"32bit-mode", "Is32Bit", "true",
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@ -34,7 +34,7 @@ def FeatureX87 : SubtargetFeature<"x87","HasX87", "true",
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"Enable X87 float instructions">;
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def FeatureNOPL : SubtargetFeature<"nopl", "HasNOPL", "true",
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"Enable NOPL instruction">;
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"Enable NOPL instruction (generally pentium pro+)">;
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def FeatureCMOV : SubtargetFeature<"cmov","HasCMOV", "true",
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"Enable conditional move instructions">;
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@ -43,7 +43,7 @@ def FeatureCX8 : SubtargetFeature<"cx8", "HasCX8", "true",
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"Support CMPXCHG8B instructions">;
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def FeatureCRC32 : SubtargetFeature<"crc32", "HasCRC32", "true",
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"Enable SSE 4.2 CRC32 instruction">;
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"Enable SSE 4.2 CRC32 instruction (used when SSE4.2 is supported but function is GPR only)">;
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def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
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"Support POPCNT instruction">;
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@ -101,7 +101,7 @@ def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
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def FeatureX86_64 : SubtargetFeature<"64bit", "HasX86_64", "true",
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"Support 64-bit instructions">;
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def FeatureCX16 : SubtargetFeature<"cx16", "HasCX16", "true",
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"64-bit with cmpxchg16b",
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"64-bit with cmpxchg16b (this is true for most x86-64 chips, but not the first AMD chips)",
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[FeatureCX8]>;
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def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
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"Support SSE 4a instructions",
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@ -198,7 +198,7 @@ def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
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[FeatureFMA4]>;
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def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
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"HasSSEUnalignedMem", "true",
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"Allow unaligned memory operands with SSE instructions">;
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"Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)">;
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def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
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"Enable AES instructions",
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[FeatureSSE2]>;
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@ -228,6 +228,8 @@ def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
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def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
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"Enable SHA instructions",
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[FeatureSSE2]>;
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// Processor supports CET SHSTK - Control-Flow Enforcement Technology
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// using Shadow Stack
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def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true",
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"Support CET Shadow-Stack instructions">;
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def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
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@ -241,7 +243,7 @@ def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
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def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true",
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"Enable Cache Line Zero">;
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def FeatureCLDEMOTE : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
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"Enable Cache Demote">;
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"Enable Cache Line Demote">;
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def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
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"Support ptwrite instruction">;
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def FeatureAMXTILE : SubtargetFeature<"amx-tile", "HasAMXTILE", "true",
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@ -285,9 +287,9 @@ def FeatureUINTR : SubtargetFeature<"uintr", "HasUINTR", "true",
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def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",
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"platform configuration instruction">;
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def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
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"Support movdiri instruction">;
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"Support movdiri instruction (direct store integer)">;
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def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",
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"Support movdir64b instruction">;
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"Support movdir64b instruction (direct store 64 bytes)">;
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// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
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// "string operations"). See "REP String Enhancement" in the Intel Software
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@ -388,7 +390,7 @@ def TuningSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
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"SHLD instruction is slow">;
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def TuningSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
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"PMULLD instruction is slow">;
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"PMULLD instruction is slow (compared to PMULLW/PMULHW and PMULUDQ)">;
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def TuningSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow",
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"true",
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@ -404,19 +406,23 @@ def TuningSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
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"Slow unaligned 32-byte memory access">;
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def TuningLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
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"Use LEA for adjusting the stack pointer">;
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"Use LEA for adjusting the stack pointer (this is an optimization for Intel Atom processors)">;
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// True if 8-bit divisions are significantly faster than
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// 32-bit divisions and should be used when possible.
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def TuningSlowDivide32 : SubtargetFeature<"idivl-to-divb",
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"HasSlowDivide32", "true",
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"Use 8-bit divide for positive values less than 256">;
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// True if 32-bit divides are significantly faster than
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// 64-bit divisions and should be used when possible.
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def TuningSlowDivide64 : SubtargetFeature<"idivq-to-divl",
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"HasSlowDivide64", "true",
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"Use 32-bit divide for positive values less than 2^32">;
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def TuningPadShortFunctions : SubtargetFeature<"pad-short-functions",
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"PadShortFunctions", "true",
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"Pad short functions">;
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"Pad short functions (to prevent a stall when returning too early)">;
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// On some processors, instructions that implicitly take two memory operands are
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// slow. In practice, this means that CALL, PUSH, and POP with memory operands
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@ -425,15 +431,21 @@ def TuningSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
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"SlowTwoMemOps", "true",
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"Two memory operand instructions are slow">;
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// True if the LEA instruction inputs have to be ready at address generation
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// (AG) time.
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def TuningLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LeaUsesAG", "true",
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"LEA instruction needs inputs at AG stage">;
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def TuningSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
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"LEA instruction with certain arguments is slow">;
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// True if the LEA instruction has all three source operands: base, index,
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// and offset or if the LEA instruction uses base and index registers where
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// the base is EBP, RBP,or R13
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def TuningSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
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"LEA instruction with 3 ops or certain registers is slow">;
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// True if INC and DEC instructions are slow when writing to flags
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def TuningSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
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"INC and DEC instructions are slower than ADD and SUB">;
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@ -474,9 +486,14 @@ def TuningInsertVZEROUPPER
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// vectorized code we should care about the throughput of SQRT operations.
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// But if the code is scalar that probably means that the code has some kind of
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// dependency and we should care more about reducing the latency.
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// True if hardware SQRTSS instruction is at least as fast (latency) as
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// RSQRTSS followed by a Newton-Raphson iteration.
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def TuningFastScalarFSQRT
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: SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
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"true", "Scalar SQRT is fast (disable Newton-Raphson)">;
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// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
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// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
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def TuningFastVectorFSQRT
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: SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
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"true", "Vector SQRT is fast (disable Newton-Raphson)">;
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@ -533,7 +550,7 @@ def TuningMacroFusion
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// similar to Skylake Server (AVX-512).
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def TuningFastGather
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: SubtargetFeature<"fast-gather", "HasFastGather", "true",
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"Indicates if gather is reasonably fast">;
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"Indicates if gather is reasonably fast (this is true for Skylake client and all AVX-512 CPUs)">;
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def TuningPrefer128Bit
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: SubtargetFeature<"prefer-128-bit", "Prefer128Bit", "true",
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@ -69,416 +69,9 @@ class X86Subtarget final : public X86GenSubtargetInfo {
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/// MMX, 3DNow, 3DNow Athlon, or none supported.
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X863DNowEnum X863DNowLevel = NoThreeDNow;
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/// Is this a Intel Atom processor?
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bool IsAtom = false;
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/// True if the processor supports X87 instructions.
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bool HasX87 = false;
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/// True if the processor supports CMPXCHG8B.
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bool HasCX8 = false;
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/// True if this processor has NOPL instruction
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/// (generally pentium pro+).
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bool HasNOPL = false;
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/// True if this processor has conditional move instructions
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/// (generally pentium pro+).
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bool HasCMOV = false;
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/// True if the processor supports X86-64 instructions.
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bool HasX86_64 = false;
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/// True if the processor supports POPCNT.
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bool HasPOPCNT = false;
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/// True if the processor supports SSE4A instructions.
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bool HasSSE4A = false;
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/// Target has AES instructions
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bool HasAES = false;
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bool HasVAES = false;
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/// Target has FXSAVE/FXRESTOR instructions
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bool HasFXSR = false;
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/// Target has XSAVE instructions
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bool HasXSAVE = false;
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/// Target has XSAVEOPT instructions
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bool HasXSAVEOPT = false;
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/// Target has XSAVEC instructions
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bool HasXSAVEC = false;
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/// Target has XSAVES instructions
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bool HasXSAVES = false;
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/// Target has carry-less multiplication
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bool HasPCLMUL = false;
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bool HasVPCLMULQDQ = false;
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/// Target has Galois Field Arithmetic instructions
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bool HasGFNI = false;
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/// Target has 3-operand fused multiply-add
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bool HasFMA = false;
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/// Target has 4-operand fused multiply-add
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bool HasFMA4 = false;
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/// Target has XOP instructions
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bool HasXOP = false;
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/// Target has TBM instructions.
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bool HasTBM = false;
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/// Target has LWP instructions
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bool HasLWP = false;
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/// True if the processor has the MOVBE instruction.
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bool HasMOVBE = false;
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/// True if the processor has the RDRAND instruction.
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bool HasRDRAND = false;
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/// Processor has 16-bit floating point conversion instructions.
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bool HasF16C = false;
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/// Processor has FS/GS base insturctions.
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bool HasFSGSBase = false;
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/// Processor has LZCNT instruction.
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bool HasLZCNT = false;
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/// Processor has BMI1 instructions.
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bool HasBMI = false;
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/// Processor has BMI2 instructions.
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bool HasBMI2 = false;
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/// Processor has VBMI instructions.
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bool HasVBMI = false;
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/// Processor has VBMI2 instructions.
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bool HasVBMI2 = false;
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/// Processor has Integer Fused Multiply Add
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bool HasIFMA = false;
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/// Processor has RTM instructions.
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bool HasRTM = false;
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/// Processor has ADX instructions.
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bool HasADX = false;
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/// Processor has SHA instructions.
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bool HasSHA = false;
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/// Processor has PRFCHW instructions.
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bool HasPRFCHW = false;
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/// Processor has RDSEED instructions.
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bool HasRDSEED = false;
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/// Processor has LAHF/SAHF instructions in 64-bit mode.
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bool HasLAHFSAHF64 = false;
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/// Processor has MONITORX/MWAITX instructions.
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bool HasMWAITX = false;
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/// Processor has Cache Line Zero instruction
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bool HasCLZERO = false;
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/// Processor has Cache Line Demote instruction
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bool HasCLDEMOTE = false;
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/// Processor has MOVDIRI instruction (direct store integer).
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bool HasMOVDIRI = false;
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/// Processor has MOVDIR64B instruction (direct store 64 bytes).
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bool HasMOVDIR64B = false;
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/// Processor has ptwrite instruction.
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bool HasPTWRITE = false;
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/// Processor has Prefetch with intent to Write instruction
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bool HasPREFETCHWT1 = false;
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/// True if SHLD instructions are slow.
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bool IsSHLDSlow = false;
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/// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
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// PMULUDQ.
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bool IsPMULLDSlow = false;
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/// True if the PMADDWD instruction is slow compared to PMULLD.
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bool IsPMADDWDSlow = false;
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/// True if unaligned memory accesses of 16-bytes are slow.
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bool IsUnalignedMem16Slow = false;
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/// True if unaligned memory accesses of 32-bytes are slow.
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bool IsUnalignedMem32Slow = false;
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/// True if SSE operations can have unaligned memory operands.
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/// This may require setting a configuration bit in the processor.
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bool HasSSEUnalignedMem = false;
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/// True if this processor has the CMPXCHG16B instruction;
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/// this is true for most x86-64 chips, but not the first AMD chips.
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bool HasCX16 = false;
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/// True if the LEA instruction should be used for adjusting
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/// the stack pointer. This is an optimization for Intel Atom processors.
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bool UseLeaForSP = false;
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/// True if POPCNT instruction has a false dependency on the destination register.
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bool HasPOPCNTFalseDeps = false;
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/// True if LZCNT/TZCNT instructions have a false dependency on the destination register.
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bool HasLZCNTFalseDeps = false;
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/// True if an SBB instruction with same source register is recognized as
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/// having no dependency on that register.
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bool HasSBBDepBreaking = false;
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/// True if its preferable to combine to a single cross-lane shuffle
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/// using a variable mask over multiple fixed shuffles.
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bool HasFastVariableCrossLaneShuffle = false;
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/// True if its preferable to combine to a single per-lane shuffle
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/// using a variable mask over multiple fixed shuffles.
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bool HasFastVariablePerLaneShuffle = false;
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/// True if vzeroupper instructions should be inserted after code that uses
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/// ymm or zmm registers.
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bool InsertVZEROUPPER = false;
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/// True if there is no performance penalty for writing NOPs with up to
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/// 7 bytes.
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bool HasFast7ByteNOP = false;
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/// True if there is no performance penalty for writing NOPs with up to
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/// 11 bytes.
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bool HasFast11ByteNOP = false;
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/// True if there is no performance penalty for writing NOPs with up to
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/// 15 bytes.
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bool HasFast15ByteNOP = false;
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/// True if gather is reasonably fast. This is true for Skylake client and
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/// all AVX-512 CPUs.
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bool HasFastGather = false;
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/// True if hardware SQRTSS instruction is at least as fast (latency) as
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/// RSQRTSS followed by a Newton-Raphson iteration.
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bool HasFastScalarFSQRT = false;
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/// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
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/// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
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bool HasFastVectorFSQRT = false;
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/// True if 8-bit divisions are significantly faster than
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/// 32-bit divisions and should be used when possible.
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bool HasSlowDivide32 = false;
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/// True if 32-bit divides are significantly faster than
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/// 64-bit divisions and should be used when possible.
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bool HasSlowDivide64 = false;
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/// True if LZCNT instruction is fast.
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bool HasFastLZCNT = false;
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/// True if SHLD based rotate is fast.
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bool HasFastSHLDRotate = false;
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/// True if the processor supports macrofusion.
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bool HasMacroFusion = false;
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/// True if the processor supports branch fusion.
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bool HasBranchFusion = false;
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/// True if the processor has enhanced REP MOVSB/STOSB.
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bool HasERMSB = false;
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/// True if the processor has fast short REP MOV.
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bool HasFSRM = false;
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/// True if the short functions should be padded to prevent
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/// a stall when returning too early.
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bool PadShortFunctions = false;
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/// True if two memory operand instructions should use a temporary register
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/// instead.
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bool SlowTwoMemOps = false;
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/// True if the LEA instruction inputs have to be ready at address generation
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/// (AG) time.
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bool LeaUsesAG = false;
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/// True if the LEA instruction with certain arguments is slow
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bool SlowLEA = false;
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/// True if the LEA instruction has all three source operands: base, index,
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/// and offset or if the LEA instruction uses base and index registers where
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/// the base is EBP, RBP,or R13
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bool Slow3OpsLEA = false;
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/// True if INC and DEC instructions are slow when writing to flags
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bool SlowIncDec = false;
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/// Processor has AVX-512 PreFetch Instructions
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bool HasPFI = false;
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/// Processor has AVX-512 Exponential and Reciprocal Instructions
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bool HasERI = false;
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/// Processor has AVX-512 Conflict Detection Instructions
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bool HasCDI = false;
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/// Processor has AVX-512 population count Instructions
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bool HasVPOPCNTDQ = false;
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/// Processor has AVX-512 Doubleword and Quadword instructions
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bool HasDQI = false;
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/// Processor has AVX-512 Byte and Word instructions
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bool HasBWI = false;
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||||
|
||||
/// Processor has AVX-512 Vector Length eXtenstions
|
||||
bool HasVLX = false;
|
||||
|
||||
/// Processor has AVX-512 16 bit floating-point extenstions
|
||||
bool HasFP16 = false;
|
||||
|
||||
/// Processor has PKU extenstions
|
||||
bool HasPKU = false;
|
||||
|
||||
/// Processor has AVX-512 Vector Neural Network Instructions
|
||||
bool HasVNNI = false;
|
||||
|
||||
/// Processor has AVX Vector Neural Network Instructions
|
||||
bool HasAVXVNNI = false;
|
||||
|
||||
/// Processor has AVX-512 bfloat16 floating-point extensions
|
||||
bool HasBF16 = false;
|
||||
|
||||
/// Processor supports ENQCMD instructions
|
||||
bool HasENQCMD = false;
|
||||
|
||||
/// Processor has AVX-512 Bit Algorithms instructions
|
||||
bool HasBITALG = false;
|
||||
|
||||
/// Processor has AVX-512 vp2intersect instructions
|
||||
bool HasVP2INTERSECT = false;
|
||||
|
||||
/// Processor supports CET SHSTK - Control-Flow Enforcement Technology
|
||||
/// using Shadow Stack
|
||||
bool HasSHSTK = false;
|
||||
|
||||
/// Processor supports Invalidate Process-Context Identifier
|
||||
bool HasINVPCID = false;
|
||||
|
||||
/// Processor has Software Guard Extensions
|
||||
bool HasSGX = false;
|
||||
|
||||
/// Processor supports Flush Cache Line instruction
|
||||
bool HasCLFLUSHOPT = false;
|
||||
|
||||
/// Processor supports Cache Line Write Back instruction
|
||||
bool HasCLWB = false;
|
||||
|
||||
/// Processor supports Write Back No Invalidate instruction
|
||||
bool HasWBNOINVD = false;
|
||||
|
||||
/// Processor support RDPID instruction
|
||||
bool HasRDPID = false;
|
||||
|
||||
/// Processor supports WaitPKG instructions
|
||||
bool HasWAITPKG = false;
|
||||
|
||||
/// Processor supports PCONFIG instruction
|
||||
bool HasPCONFIG = false;
|
||||
|
||||
/// Processor support key locker instructions
|
||||
bool HasKL = false;
|
||||
|
||||
/// Processor support key locker wide instructions
|
||||
bool HasWIDEKL = false;
|
||||
|
||||
/// Processor supports HRESET instruction
|
||||
bool HasHRESET = false;
|
||||
|
||||
/// Processor supports SERIALIZE instruction
|
||||
bool HasSERIALIZE = false;
|
||||
|
||||
/// Processor supports TSXLDTRK instruction
|
||||
bool HasTSXLDTRK = false;
|
||||
|
||||
/// Processor has AMX support
|
||||
bool HasAMXTILE = false;
|
||||
bool HasAMXBF16 = false;
|
||||
bool HasAMXINT8 = false;
|
||||
|
||||
/// Processor supports User Level Interrupt instructions
|
||||
bool HasUINTR = false;
|
||||
|
||||
/// Enable SSE4.2 CRC32 instruction (Used when SSE4.2 is supported but
|
||||
/// function is GPR only)
|
||||
bool HasCRC32 = false;
|
||||
|
||||
/// Processor has a single uop BEXTR implementation.
|
||||
bool HasFastBEXTR = false;
|
||||
|
||||
/// Try harder to combine to horizontal vector ops if they are fast.
|
||||
bool HasFastHorizontalOps = false;
|
||||
|
||||
/// Prefer a left/right scalar logical shifts pair over a shift+and pair.
|
||||
bool HasFastScalarShiftMasks = false;
|
||||
|
||||
/// Prefer a left/right vector logical shifts pair over a shift+and pair.
|
||||
bool HasFastVectorShiftMasks = false;
|
||||
|
||||
/// Prefer a movbe over a single-use load + bswap / single-use bswap + store.
|
||||
bool HasFastMOVBE = false;
|
||||
|
||||
/// Use a retpoline thunk rather than indirect calls to block speculative
|
||||
/// execution.
|
||||
bool UseRetpolineIndirectCalls = false;
|
||||
|
||||
/// Use a retpoline thunk or remove any indirect branch to block speculative
|
||||
/// execution.
|
||||
bool UseRetpolineIndirectBranches = false;
|
||||
|
||||
/// Deprecated flag, query `UseRetpolineIndirectCalls` and
|
||||
/// `UseRetpolineIndirectBranches` instead.
|
||||
bool DeprecatedUseRetpoline = false;
|
||||
|
||||
/// When using a retpoline thunk, call an externally provided thunk rather
|
||||
/// than emitting one inside the compiler.
|
||||
bool UseRetpolineExternalThunk = false;
|
||||
|
||||
/// Prevent generation of indirect call/branch instructions from memory,
|
||||
/// and force all indirect call/branch instructions from a register to be
|
||||
/// preceded by an LFENCE. Also decompose RET instructions into a
|
||||
/// POP+LFENCE+JMP sequence.
|
||||
bool UseLVIControlFlowIntegrity = false;
|
||||
|
||||
/// Enable Speculative Execution Side Effect Suppression
|
||||
bool UseSpeculativeExecutionSideEffectSuppression = false;
|
||||
|
||||
/// Insert LFENCE instructions to prevent data speculatively injected into
|
||||
/// loads from being used maliciously.
|
||||
bool UseLVILoadHardening = false;
|
||||
|
||||
/// Use an instruction sequence for taking the address of a global that allows
|
||||
/// a memory tag in the upper address bits.
|
||||
bool AllowTaggedGlobals = false;
|
||||
|
||||
/// Use software floating point for code generation.
|
||||
bool UseSoftFloat = false;
|
||||
|
||||
#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
|
||||
bool ATTRIBUTE = DEFAULT;
|
||||
#include "X86GenSubtargetInfo.inc"
|
||||
/// The minimum alignment known to hold of the stack frame on
|
||||
/// entry to the function and which must be maintained by every function.
|
||||
Align stackAlignment = Align(4);
|
||||
|
|
@ -490,21 +83,6 @@ class X86Subtarget final : public X86GenSubtargetInfo {
|
|||
// FIXME: this is a known good value for Yonah. How about others?
|
||||
unsigned MaxInlineSizeThreshold = 128;
|
||||
|
||||
/// Indicates target prefers 128 bit instructions.
|
||||
bool Prefer128Bit = false;
|
||||
|
||||
/// Indicates target prefers 256 bit instructions.
|
||||
bool Prefer256Bit = false;
|
||||
|
||||
/// Indicates target prefers AVX512 mask registers.
|
||||
bool PreferMaskRegisters = false;
|
||||
|
||||
/// Use Silvermont specific arithmetic costs.
|
||||
bool UseSLMArithCosts = false;
|
||||
|
||||
/// Use Goldmont specific floating point div/sqrt costs.
|
||||
bool UseGLMDivSqrtCosts = false;
|
||||
|
||||
/// What processor and OS we're targeting.
|
||||
Triple TargetTriple;
|
||||
|
||||
|
|
@ -514,7 +92,6 @@ class X86Subtarget final : public X86GenSubtargetInfo {
|
|||
std::unique_ptr<RegisterBankInfo> RegBankInfo;
|
||||
std::unique_ptr<InstructionSelector> InstSelector;
|
||||
|
||||
private:
|
||||
/// Override the stack alignment.
|
||||
MaybeAlign StackAlignOverride;
|
||||
|
||||
|
|
@ -528,15 +105,6 @@ private:
|
|||
/// Required vector width from function attribute.
|
||||
unsigned RequiredVectorWidth;
|
||||
|
||||
/// True if compiling for 64-bit, false for 16-bit or 32-bit.
|
||||
bool Is64Bit = false;
|
||||
|
||||
/// True if compiling for 32-bit, false for 16-bit or 64-bit.
|
||||
bool Is32Bit = false;
|
||||
|
||||
/// True if compiling for 16-bit, false for 32-bit or 64-bit.
|
||||
bool Is16Bit = false;
|
||||
|
||||
X86SelectionDAGInfo TSInfo;
|
||||
// Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
|
||||
// X86TargetLowering needs.
|
||||
|
|
@ -602,18 +170,10 @@ private:
|
|||
void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
|
||||
|
||||
public:
|
||||
/// Is this x86_64? (disregarding specific ABI / programming model)
|
||||
bool is64Bit() const {
|
||||
return Is64Bit;
|
||||
}
|
||||
|
||||
bool is32Bit() const {
|
||||
return Is32Bit;
|
||||
}
|
||||
|
||||
bool is16Bit() const {
|
||||
return Is16Bit;
|
||||
}
|
||||
#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
|
||||
bool GETTER() const { return ATTRIBUTE; }
|
||||
#include "X86GenSubtargetInfo.inc"
|
||||
|
||||
/// Is this x86_64 with the ILP32 programming model (x32 ABI)?
|
||||
bool isTarget64BitILP32() const {
|
||||
|
|
@ -628,16 +188,11 @@ public:
|
|||
PICStyles::Style getPICStyle() const { return PICStyle; }
|
||||
void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
|
||||
|
||||
bool hasX87() const { return HasX87; }
|
||||
bool hasCX8() const { return HasCX8; }
|
||||
bool hasCX16() const { return HasCX16; }
|
||||
bool canUseCMPXCHG8B() const { return hasCX8(); }
|
||||
bool canUseCMPXCHG16B() const {
|
||||
// CX16 is just the CPUID bit, instruction requires 64-bit mode too.
|
||||
return hasCX16() && is64Bit();
|
||||
}
|
||||
bool hasNOPL() const { return HasNOPL; }
|
||||
bool hasCMOV() const { return HasCMOV; }
|
||||
// SSE codegen depends on cmovs, and all SSE1+ processors support them.
|
||||
// All 64-bit processors support cmov.
|
||||
bool canUseCMOV() const { return hasCMOV() || hasSSE1() || is64Bit(); }
|
||||
|
|
@ -651,44 +206,10 @@ public:
|
|||
bool hasAVX2() const { return X86SSELevel >= AVX2; }
|
||||
bool hasAVX512() const { return X86SSELevel >= AVX512; }
|
||||
bool hasInt256() const { return hasAVX2(); }
|
||||
bool hasSSE4A() const { return HasSSE4A; }
|
||||
bool hasMMX() const { return X863DNowLevel >= MMX; }
|
||||
bool hasThreeDNow() const { return X863DNowLevel >= ThreeDNow; }
|
||||
bool hasThreeDNowA() const { return X863DNowLevel >= ThreeDNowA; }
|
||||
bool hasPOPCNT() const { return HasPOPCNT; }
|
||||
bool hasAES() const { return HasAES; }
|
||||
bool hasVAES() const { return HasVAES; }
|
||||
bool hasFXSR() const { return HasFXSR; }
|
||||
bool hasXSAVE() const { return HasXSAVE; }
|
||||
bool hasXSAVEOPT() const { return HasXSAVEOPT; }
|
||||
bool hasXSAVEC() const { return HasXSAVEC; }
|
||||
bool hasXSAVES() const { return HasXSAVES; }
|
||||
bool hasPCLMUL() const { return HasPCLMUL; }
|
||||
bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
|
||||
bool hasGFNI() const { return HasGFNI; }
|
||||
// Prefer FMA4 to FMA - its better for commutation/memory folding and
|
||||
// has equal or better performance on all supported targets.
|
||||
bool hasFMA() const { return HasFMA; }
|
||||
bool hasFMA4() const { return HasFMA4; }
|
||||
bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
|
||||
bool hasXOP() const { return HasXOP; }
|
||||
bool hasTBM() const { return HasTBM; }
|
||||
bool hasLWP() const { return HasLWP; }
|
||||
bool hasMOVBE() const { return HasMOVBE; }
|
||||
bool hasRDRAND() const { return HasRDRAND; }
|
||||
bool hasF16C() const { return HasF16C; }
|
||||
bool hasFSGSBase() const { return HasFSGSBase; }
|
||||
bool hasLZCNT() const { return HasLZCNT; }
|
||||
bool hasBMI() const { return HasBMI; }
|
||||
bool hasBMI2() const { return HasBMI2; }
|
||||
bool hasVBMI() const { return HasVBMI; }
|
||||
bool hasVBMI2() const { return HasVBMI2; }
|
||||
bool hasIFMA() const { return HasIFMA; }
|
||||
bool hasRTM() const { return HasRTM; }
|
||||
bool hasADX() const { return HasADX; }
|
||||
bool hasSHA() const { return HasSHA; }
|
||||
bool hasPRFCHW() const { return HasPRFCHW; }
|
||||
bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
|
||||
bool hasPrefetchW() const {
|
||||
// The PREFETCHW instruction was added with 3DNow but later CPUs gave it
|
||||
// its own CPUID bit as part of deprecating 3DNow. Intel eventually added
|
||||
|
|
@ -702,94 +223,7 @@ public:
|
|||
// 3dnow.
|
||||
return hasSSE1() || (hasPRFCHW() && !hasThreeDNow()) || hasPREFETCHWT1();
|
||||
}
|
||||
bool hasRDSEED() const { return HasRDSEED; }
|
||||
bool hasLAHFSAHF() const { return HasLAHFSAHF64; }
|
||||
bool canUseLAHFSAHF() const { return hasLAHFSAHF() || !is64Bit(); }
|
||||
bool hasMWAITX() const { return HasMWAITX; }
|
||||
bool hasCLZERO() const { return HasCLZERO; }
|
||||
bool hasCLDEMOTE() const { return HasCLDEMOTE; }
|
||||
bool hasMOVDIRI() const { return HasMOVDIRI; }
|
||||
bool hasMOVDIR64B() const { return HasMOVDIR64B; }
|
||||
bool hasPTWRITE() const { return HasPTWRITE; }
|
||||
bool isSHLDSlow() const { return IsSHLDSlow; }
|
||||
bool isPMULLDSlow() const { return IsPMULLDSlow; }
|
||||
bool isPMADDWDSlow() const { return IsPMADDWDSlow; }
|
||||
bool isUnalignedMem16Slow() const { return IsUnalignedMem16Slow; }
|
||||
bool isUnalignedMem32Slow() const { return IsUnalignedMem32Slow; }
|
||||
bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
|
||||
bool useLeaForSP() const { return UseLeaForSP; }
|
||||
bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; }
|
||||
bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; }
|
||||
bool hasSBBDepBreaking() const { return HasSBBDepBreaking; }
|
||||
bool hasFastVariableCrossLaneShuffle() const {
|
||||
return HasFastVariableCrossLaneShuffle;
|
||||
}
|
||||
bool hasFastVariablePerLaneShuffle() const {
|
||||
return HasFastVariablePerLaneShuffle;
|
||||
}
|
||||
bool insertVZEROUPPER() const { return InsertVZEROUPPER; }
|
||||
bool hasFastGather() const { return HasFastGather; }
|
||||
bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
|
||||
bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
|
||||
bool hasFastLZCNT() const { return HasFastLZCNT; }
|
||||
bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
|
||||
bool hasFastBEXTR() const { return HasFastBEXTR; }
|
||||
bool hasFastHorizontalOps() const { return HasFastHorizontalOps; }
|
||||
bool hasFastScalarShiftMasks() const { return HasFastScalarShiftMasks; }
|
||||
bool hasFastVectorShiftMasks() const { return HasFastVectorShiftMasks; }
|
||||
bool hasFastMOVBE() const { return HasFastMOVBE; }
|
||||
bool hasMacroFusion() const { return HasMacroFusion; }
|
||||
bool hasBranchFusion() const { return HasBranchFusion; }
|
||||
bool hasERMSB() const { return HasERMSB; }
|
||||
bool hasFSRM() const { return HasFSRM; }
|
||||
bool hasSlowDivide32() const { return HasSlowDivide32; }
|
||||
bool hasSlowDivide64() const { return HasSlowDivide64; }
|
||||
bool padShortFunctions() const { return PadShortFunctions; }
|
||||
bool slowTwoMemOps() const { return SlowTwoMemOps; }
|
||||
bool leaUsesAG() const { return LeaUsesAG; }
|
||||
bool slowLEA() const { return SlowLEA; }
|
||||
bool slow3OpsLEA() const { return Slow3OpsLEA; }
|
||||
bool slowIncDec() const { return SlowIncDec; }
|
||||
bool hasCDI() const { return HasCDI; }
|
||||
bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
|
||||
bool hasPFI() const { return HasPFI; }
|
||||
bool hasERI() const { return HasERI; }
|
||||
bool hasDQI() const { return HasDQI; }
|
||||
bool hasBWI() const { return HasBWI; }
|
||||
bool hasVLX() const { return HasVLX; }
|
||||
bool hasFP16() const { return HasFP16; }
|
||||
bool hasPKU() const { return HasPKU; }
|
||||
bool hasVNNI() const { return HasVNNI; }
|
||||
bool hasBF16() const { return HasBF16; }
|
||||
bool hasVP2INTERSECT() const { return HasVP2INTERSECT; }
|
||||
bool hasBITALG() const { return HasBITALG; }
|
||||
bool hasSHSTK() const { return HasSHSTK; }
|
||||
bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
|
||||
bool hasCLWB() const { return HasCLWB; }
|
||||
bool hasWBNOINVD() const { return HasWBNOINVD; }
|
||||
bool hasRDPID() const { return HasRDPID; }
|
||||
bool hasWAITPKG() const { return HasWAITPKG; }
|
||||
bool hasPCONFIG() const { return HasPCONFIG; }
|
||||
bool hasSGX() const { return HasSGX; }
|
||||
bool hasINVPCID() const { return HasINVPCID; }
|
||||
bool hasENQCMD() const { return HasENQCMD; }
|
||||
bool hasKL() const { return HasKL; }
|
||||
bool hasWIDEKL() const { return HasWIDEKL; }
|
||||
bool hasHRESET() const { return HasHRESET; }
|
||||
bool hasSERIALIZE() const { return HasSERIALIZE; }
|
||||
bool hasTSXLDTRK() const { return HasTSXLDTRK; }
|
||||
bool hasUINTR() const { return HasUINTR; }
|
||||
bool hasCRC32() const { return HasCRC32; }
|
||||
bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
|
||||
bool useRetpolineIndirectBranches() const {
|
||||
return UseRetpolineIndirectBranches;
|
||||
}
|
||||
bool hasAVXVNNI() const { return HasAVXVNNI; }
|
||||
bool hasAMXTILE() const { return HasAMXTILE; }
|
||||
bool hasAMXBF16() const { return HasAMXBF16; }
|
||||
bool hasAMXINT8() const { return HasAMXINT8; }
|
||||
bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
|
||||
|
||||
bool canUseLAHFSAHF() const { return hasLAHFSAHF64() || !is64Bit(); }
|
||||
// These are generic getters that OR together all of the thunk types
|
||||
// supported by the subtarget. Therefore useIndirectThunk*() will return true
|
||||
// if any respective thunk feature is enabled.
|
||||
|
|
@ -800,16 +234,6 @@ public:
|
|||
return useRetpolineIndirectBranches() || useLVIControlFlowIntegrity();
|
||||
}
|
||||
|
||||
bool preferMaskRegisters() const { return PreferMaskRegisters; }
|
||||
bool useSLMArithCosts() const { return UseSLMArithCosts; }
|
||||
bool useGLMDivSqrtCosts() const { return UseGLMDivSqrtCosts; }
|
||||
bool useLVIControlFlowIntegrity() const { return UseLVIControlFlowIntegrity; }
|
||||
bool allowTaggedGlobals() const { return AllowTaggedGlobals; }
|
||||
bool useLVILoadHardening() const { return UseLVILoadHardening; }
|
||||
bool useSpeculativeExecutionSideEffectSuppression() const {
|
||||
return UseSpeculativeExecutionSideEffectSuppression;
|
||||
}
|
||||
|
||||
unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
|
||||
unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
|
||||
|
||||
|
|
@ -836,10 +260,6 @@ public:
|
|||
|
||||
bool isXRaySupported() const override { return is64Bit(); }
|
||||
|
||||
/// TODO: to be removed later and replaced with suitable properties
|
||||
bool isAtom() const { return IsAtom; }
|
||||
bool useSoftFloat() const { return UseSoftFloat; }
|
||||
|
||||
/// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
|
||||
/// no-sse2). There isn't any reason to disable it if the target processor
|
||||
/// supports it.
|
||||
|
|
|
|||
Loading…
Reference in New Issue