[AArch64][GlobalISel] Add isel support for a couple vector exts/truncs

Add support for

- v4s16 <-> v4s32
- v2s64 <-> v2s32

And update tests that use them to show that we generate the correct
instructions.

Differential Revision: https://reviews.llvm.org/D57832

llvm-svn: 353732

llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp

@@ -274,9 +274,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
 
   // FP conversions
   getActionDefinitionsBuilder(G_FPTRUNC).legalFor(
-      {{s16, s32}, {s16, s64}, {s32, s64}});
+      {{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}});
   getActionDefinitionsBuilder(G_FPEXT).legalFor(
-      {{s32, s16}, {s64, s16}, {s64, s32}});
+      {{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}});
 
   // Conversions
   getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})

llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir

@@ -67,6 +67,48 @@ body:             |
     $s0 = COPY %1(s32)
 ...
 
+---
+name:            fptrunc_v4s16_v4s32_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $d0
+    ; CHECK-LABEL: name: fptrunc_v4s16_v4s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK: [[FCVTNv4i16:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
+    ; CHECK: $d0 = COPY [[FCVTNv4i16]]
+    %0(<4 x s32>) = COPY $q0
+    %1(<4 x s16>) = G_FPTRUNC %0
+    $d0 = COPY %1(<4 x s16>)
+...
+
+---
+name:            fptrunc_v2s32_v2s64_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $q0
+    ; CHECK-LABEL: name: fptrunc_v2s32_v2s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK: [[FCVTNv2i32:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]]
+    ; CHECK: $d0 = COPY [[FCVTNv2i32]]
+    %0(<2 x s64>) = COPY $q0
+    %1(<2 x s32>) = G_FPTRUNC %0
+    $d0 = COPY %1(<2 x s32>)
+...
+
 ---
 name:            fpext_s32_s16_fpr
 legalized:       true
@@ -133,6 +175,48 @@ body:             |
     $d0 = COPY %1(s64)
 ...
 
+---
+name:            fpext_v4s32_v4s16_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $d0
+    ; CHECK-LABEL: name: fpext_v4s32_v4s16_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK: [[FCVTLv4i16:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
+    ; CHECK: $q0 = COPY [[FCVTLv4i16]]
+    %0(<4 x s16>) = COPY $d0
+    %1(<4 x s32>) = G_FPEXT %0
+    $q0 = COPY %1(<4 x s32>)
+...
+
+---
+name:            fpext_v2s64_v2s32_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $d0
+    ; CHECK-LABEL: name: fpext_v2s64_v2s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK: [[FCVTLv2i32:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
+    ; CHECK: $q0 = COPY [[FCVTLv2i32]]
+    %0(<2 x s32>) = COPY $d0
+    %1(<2 x s64>) = G_FPEXT %0
+    $q0 = COPY %1(<2 x s64>)
+...
+
 ---
 name:            sitofp_s32_s32_fpr
 legalized:       true

llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll

@@ -1,39 +1,61 @@
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
 ; RUN: llc < %s -O0 -fast-isel -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* \
+; RUN:          -mtriple=arm64-eabi -aarch64-neon-syntax=apple \
+; RUN:          | FileCheck %s --check-prefixes=GISEL,FALLBACK
 
+; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_f64_f32)
+; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_f64_f32)
 define <2 x double> @test_vcvt_f64_f32(<2 x float> %x) nounwind readnone ssp {
 ; CHECK-LABEL: test_vcvt_f64_f32:
+; GISEL-LABEL: test_vcvt_f64_f32:
   %vcvt1.i = fpext <2 x float> %x to <2 x double>
 ; CHECK: fcvtl	v0.2d, v0.2s
+; GISEL: fcvtl	v0.2d, v0.2s
   ret <2 x double> %vcvt1.i
 ; CHECK: ret
+; GISEL: ret
 }
 
+; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_high_f64_f32)
+; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_high_f64_f32)
 define <2 x double> @test_vcvt_high_f64_f32(<4 x float> %x) nounwind readnone ssp {
 ; CHECK-LABEL: test_vcvt_high_f64_f32:
+; GISEL-LABEL: test_vcvt_high_f64_f32:
   %cvt_in = shufflevector <4 x float> %x, <4 x float> undef, <2 x i32> <i32 2, i32 3>
   %vcvt1.i = fpext <2 x float> %cvt_in to <2 x double>
 ; CHECK: fcvtl2	v0.2d, v0.4s
+; GISEL: fcvtl2	v0.2d, v0.4s
   ret <2 x double> %vcvt1.i
 ; CHECK: ret
+; GISEL: ret
 }
 
+; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_f32_f64)
+; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_f32_f64)
 define <2 x float> @test_vcvt_f32_f64(<2 x double> %v) nounwind readnone ssp {
 ; CHECK-LABEL: test_vcvt_f32_f64:
+; GISEL-LABEL: test_vcvt_f32_f64:
   %vcvt1.i = fptrunc <2 x double> %v to <2 x float>
 ; CHECK: fcvtn
+; GISEL: fcvtn
   ret <2 x float> %vcvt1.i
 ; CHECK: ret
+; GISEL: ret
 }
 
+; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_high_f32_f64)
+; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_high_f32_f64)
 define <4 x float> @test_vcvt_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp {
 ; CHECK-LABEL: test_vcvt_high_f32_f64:
-
+; GISEL-LABEL: test_vcvt_high_f32_f64:
   %cvt = fptrunc <2 x double> %v to <2 x float>
   %vcvt2.i = shufflevector <2 x float> %x, <2 x float> %cvt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 ; CHECK: fcvtn2
+; GISEL: fcvtn2
   ret <4 x float> %vcvt2.i
 ; CHECK: ret
+; GISEL: ret
 }
 
 define <2 x float> @test_vcvtx_f32_f64(<2 x double> %v) nounwind readnone ssp {