forked from OSchip/llvm-project
[ImplicitNullChecks] Hoist trivial depdendencies if possible
When trying to convert a loading instruction into a FAULTING_LOAD, we
sometimes face code like this:
if %R10 is not null:
%R9<def> = MOV32ri Immediate
%R9<def, tied> = AND32rm %R9, 0x20(%R10)
else:
goto TRAP
In these cases we would like to use the AND32rm instruction as the
faulting operation by hoisting the "depedency" def-ing %R9 also above
the control flow, transforming the program into:
%R9<def> = MOV32ri Immediate
%R9<def, tied> = FAULTING_LOAD_OP(AND32rm %R9, 0x20(%R10), FailPath: TRAP)
This change teaches ImplicitNullChecks to do the above, when safe.
llvm-svn: 273501
This commit is contained in:
Sanjoy Das
parent
590e85b575
commit
e57bf680ec
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@ -28,6 +28,7 @@
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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@ -75,14 +76,19 @@ class ImplicitNullChecks : public MachineFunctionPass {
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// The block branched to if the pointer is null.
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MachineBasicBlock *NullSucc;
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// If this is non-null, then MemOperation has a dependency on on this
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// instruction; and it needs to be hoisted to execute before MemOperation.
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MachineInstr *OnlyDependency;
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public:
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explicit NullCheck(MachineInstr *memOperation, MachineInstr *checkOperation,
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MachineBasicBlock *checkBlock,
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MachineBasicBlock *notNullSucc,
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MachineBasicBlock *nullSucc)
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MachineBasicBlock *nullSucc,
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MachineInstr *onlyDependency)
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: MemOperation(memOperation), CheckOperation(checkOperation),
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CheckBlock(checkBlock), NotNullSucc(notNullSucc), NullSucc(nullSucc) {
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}
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CheckBlock(checkBlock), NotNullSucc(notNullSucc), NullSucc(nullSucc),
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OnlyDependency(onlyDependency) {}
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MachineInstr *getMemOperation() const { return MemOperation; }
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@ -93,10 +99,13 @@ class ImplicitNullChecks : public MachineFunctionPass {
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MachineBasicBlock *getNotNullSucc() const { return NotNullSucc; }
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MachineBasicBlock *getNullSucc() const { return NullSucc; }
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MachineInstr *getOnlyDependency() const { return OnlyDependency; }
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};
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const TargetInstrInfo *TII = nullptr;
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const TargetRegisterInfo *TRI = nullptr;
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AliasAnalysis *AA = nullptr;
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MachineModuleInfo *MMI = nullptr;
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bool analyzeBlockForNullChecks(MachineBasicBlock &MBB,
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@ -113,6 +122,10 @@ public:
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<AAResultsWrapperPass>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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@ -126,14 +139,22 @@ public:
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/// machine instruction can be re-ordered from after the machine instructions
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/// seen so far to before them.
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class HazardDetector {
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DenseSet<unsigned> RegDefs;
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static MachineInstr *getUnknownMI() {
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return DenseMapInfo<MachineInstr *>::getTombstoneKey();
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}
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// Maps physical registers to the instruction defining them. If there has
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// been more than one def of an specific register, that register is mapped to
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// getUnknownMI().
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DenseMap<unsigned, MachineInstr *> RegDefs;
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DenseSet<unsigned> RegUses;
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const TargetRegisterInfo &TRI;
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bool hasSeenClobber;
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AliasAnalysis &AA;
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public:
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explicit HazardDetector(const TargetRegisterInfo &TRI) :
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TRI(TRI), hasSeenClobber(false) {}
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explicit HazardDetector(const TargetRegisterInfo &TRI, AliasAnalysis &AA)
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: TRI(TRI), hasSeenClobber(false), AA(AA) {}
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/// \brief Make a note of \p MI for later queries to isSafeToHoist.
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///
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@ -141,8 +162,10 @@ public:
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void rememberInstruction(MachineInstr *MI);
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/// \brief Return true if it is safe to hoist \p MI from after all the
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/// instructions seen so far (via rememberInstruction) to before it.
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bool isSafeToHoist(MachineInstr *MI);
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/// instructions seen so far (via rememberInstruction) to before it. If \p MI
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/// has one and only one transitive dependency, set \p Dependency to that
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/// instruction. If there are more dependencies, return false.
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bool isSafeToHoist(MachineInstr *MI, MachineInstr *&Dependency);
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/// \brief Return true if this instance of HazardDetector has been clobbered
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/// (i.e. has no more useful information).
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@ -181,15 +204,23 @@ void HazardDetector::rememberInstruction(MachineInstr *MI) {
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if (!MO.isReg() || !MO.getReg())
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continue;
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if (MO.isDef())
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RegDefs.insert(MO.getReg());
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else
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if (MO.isDef()) {
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auto It = RegDefs.find(MO.getReg());
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if (It == RegDefs.end())
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RegDefs.insert({MO.getReg(), MI});
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else {
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assert(It->second && "Found null MI?");
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It->second = getUnknownMI();
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}
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} else
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RegUses.insert(MO.getReg());
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}
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}
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bool HazardDetector::isSafeToHoist(MachineInstr *MI) {
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bool HazardDetector::isSafeToHoist(MachineInstr *MI,
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MachineInstr *&Dependency) {
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assert(!isClobbered() && "isSafeToHoist cannot do anything useful!");
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Dependency = nullptr;
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// Right now we don't want to worry about LLVM's memory model. This can be
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// made more precise later.
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@ -199,9 +230,54 @@ bool HazardDetector::isSafeToHoist(MachineInstr *MI) {
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for (auto &MO : MI->operands()) {
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if (MO.isReg() && MO.getReg()) {
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for (unsigned Reg : RegDefs)
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if (TRI.regsOverlap(Reg, MO.getReg()))
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return false; // We found a write-after-write or read-after-write
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for (auto &RegDef : RegDefs) {
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unsigned Reg = RegDef.first;
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MachineInstr *MI = RegDef.second;
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if (!TRI.regsOverlap(Reg, MO.getReg()))
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continue;
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// We found a write-after-write or read-after-write, see if the
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// instruction causing this dependency can be hoisted too.
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if (MI == getUnknownMI())
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// We don't have precise dependency information.
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return false;
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if (Dependency) {
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if (Dependency == MI)
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continue;
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// We already have one dependency, and we can track only one.
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return false;
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}
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// Now check if MI is actually a dependency that can be hoisted.
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// We don't want to track transitive dependencies. We already know that
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// MI is the only instruction that defines Reg, but we need to be sure
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// that it does not use any registers that have been defined (trivially
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// checked below by ensuring that there are no register uses), and that
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// it is the only def for every register it defines (otherwise we could
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// violate a write after write hazard).
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auto IsMIOperandSafe = [&](MachineOperand &MO) {
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if (!MO.isReg() || !MO.getReg())
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return true;
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if (MO.isUse())
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return false;
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assert((!MO.isDef() || RegDefs.count(MO.getReg())) &&
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"All defs must be tracked in RegDefs by now!");
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return !MO.isDef() || RegDefs.find(MO.getReg())->second == MI;
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};
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if (!all_of(MI->operands(), IsMIOperandSafe))
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return false;
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// Now check for speculation safety:
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bool SawStore = true;
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if (!MI->isSafeToMove(&AA, SawStore) || MI->mayLoad())
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return false;
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Dependency = MI;
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}
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if (MO.isDef())
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for (unsigned Reg : RegUses)
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@ -217,6 +293,7 @@ bool ImplicitNullChecks::runOnMachineFunction(MachineFunction &MF) {
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TII = MF.getSubtarget().getInstrInfo();
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TRI = MF.getRegInfo().getTargetRegisterInfo();
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MMI = &MF.getMMI();
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AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
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SmallVector<NullCheck, 16> NullCheckList;
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@ -229,6 +306,16 @@ bool ImplicitNullChecks::runOnMachineFunction(MachineFunction &MF) {
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return !NullCheckList.empty();
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}
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// Return true if any register aliasing \p Reg is live-in into \p MBB.
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static bool AnyAliasLiveIn(const TargetRegisterInfo *TRI,
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MachineBasicBlock *MBB, unsigned Reg) {
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for (MCRegAliasIterator AR(Reg, TRI, /*IncludeSelf*/ true); AR.isValid();
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++AR)
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if (MBB->isLiveIn(*AR))
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return true;
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return false;
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}
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/// Analyze MBB to check if its terminating branch can be turned into an
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/// implicit null check. If yes, append a description of the said null check to
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/// NullCheckList and return true, else return false.
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@ -330,20 +417,56 @@ bool ImplicitNullChecks::analyzeBlockForNullChecks(
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unsigned PointerReg = MBP.LHS.getReg();
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HazardDetector HD(*TRI);
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HazardDetector HD(*TRI, *AA);
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for (auto MII = NotNullSucc->begin(), MIE = NotNullSucc->end(); MII != MIE;
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++MII) {
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MachineInstr *MI = &*MII;
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unsigned BaseReg;
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int64_t Offset;
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MachineInstr *Dependency = nullptr;
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if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
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if (MI->mayLoad() && !MI->isPredicable() && BaseReg == PointerReg &&
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Offset < PageSize && MI->getDesc().getNumDefs() <= 1 &&
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HD.isSafeToHoist(MI)) {
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NullCheckList.emplace_back(MI, MBP.ConditionDef, &MBB, NotNullSucc,
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NullSucc);
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return true;
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HD.isSafeToHoist(MI, Dependency)) {
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auto DependencyOperandIsOk = [&](MachineOperand &MO) {
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assert(!(MO.isReg() && MO.isUse()) &&
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"No transitive dependendencies please!");
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if (!MO.isReg() || !MO.getReg() || !MO.isDef())
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return true;
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// Make sure that we won't clobber any live ins to the sibling block
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// by hoisting Dependency. For instance, we can't hoist INST to
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// before the null check (even if it safe, and does not violate any
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// dependencies in the non_null_block) if %rdx is live in to
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// _null_block.
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//
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// test %rcx, %rcx
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// je _null_block
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// _non_null_block:
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// %rdx<def> = INST
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// ...
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if (AnyAliasLiveIn(TRI, NullSucc, MO.getReg()))
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return false;
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// Make sure Dependency isn't re-defining the base register. Then we
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// won't get the memory operation on the address we want.
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if (TRI->regsOverlap(MO.getReg(), BaseReg))
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return false;
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return true;
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};
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bool DependencyOperandsAreOk =
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!Dependency ||
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all_of(Dependency->operands(), DependencyOperandIsOk);
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if (DependencyOperandsAreOk) {
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NullCheckList.emplace_back(MI, MBP.ConditionDef, &MBB, NotNullSucc,
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NullSucc, Dependency);
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return true;
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}
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}
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HD.rememberInstruction(MI);
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@ -399,6 +522,11 @@ void ImplicitNullChecks::rewriteNullChecks(
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(void)BranchesRemoved;
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assert(BranchesRemoved > 0 && "expected at least one branch!");
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if (auto *DepMI = NC.getOnlyDependency()) {
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DepMI->removeFromParent();
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NC.getCheckBlock()->insert(NC.getCheckBlock()->end(), DepMI);
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}
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// Insert a faulting load where the conditional branch was originally. We
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// check earlier ensures that this bit of code motion is legal. We do not
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// touch the successors list for any basic block since we haven't changed
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@ -418,6 +546,16 @@ void ImplicitNullChecks::rewriteNullChecks(
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continue;
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MBB->addLiveIn(Reg);
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}
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if (auto *DepMI = NC.getOnlyDependency()) {
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for (auto &MO : DepMI->operands()) {
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if (!MO.isReg() || !MO.getReg() || !MO.isDef())
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continue;
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if (!NC.getNotNullSucc()->isLiveIn(MO.getReg()))
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NC.getNotNullSucc()->addLiveIn(MO.getReg());
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}
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}
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NC.getMemOperation()->eraseFromParent();
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NC.getCheckOperation()->eraseFromParent();
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@ -433,5 +571,6 @@ char ImplicitNullChecks::ID = 0;
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char &llvm::ImplicitNullChecksID = ImplicitNullChecks::ID;
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INITIALIZE_PASS_BEGIN(ImplicitNullChecks, "implicit-null-checks",
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"Implicit null checks", false, false)
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INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
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INITIALIZE_PASS_END(ImplicitNullChecks, "implicit-null-checks",
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"Implicit null checks", false, false)
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@ -0,0 +1,266 @@
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# RUN: llc -run-pass implicit-null-checks -mtriple=x86_64-apple-macosx -o /dev/null %s 2>&1 | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx"
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;; Positive test
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define i32 @imp_null_check_with_bitwise_op_0(i32* %x, i32 %val) {
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entry:
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br i1 undef, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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br i1 undef, label %ret_100, label %ret_200
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ret_100:
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ret i32 100
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ret_200:
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ret i32 200
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}
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;; Negative test. The regalloc is such that we cannot hoist the
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;; instruction materializing 2200000 into %eax
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define i32 @imp_null_check_with_bitwise_op_1(i32* %x, i32 %val, i32* %ptr) {
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entry:
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br i1 undef, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 undef
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not_null:
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br i1 undef, label %ret_100, label %ret_200
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ret_100:
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ret i32 100
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ret_200:
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ret i32 200
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}
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;; Negative test: IR is identical to
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;; @imp_null_check_with_bitwise_op_0 but MIR differs.
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define i32 @imp_null_check_with_bitwise_op_2(i32* %x, i32 %val) {
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entry:
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br i1 undef, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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br i1 undef, label %ret_100, label %ret_200
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ret_100:
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ret i32 100
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ret_200:
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ret i32 200
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}
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;; Negative test: IR is identical to
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;; @imp_null_check_with_bitwise_op_0 but MIR differs.
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define i32 @imp_null_check_with_bitwise_op_3(i32* %x, i32 %val) {
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entry:
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br i1 undef, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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br i1 undef, label %ret_100, label %ret_200
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ret_100:
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ret i32 100
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ret_200:
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ret i32 200
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}
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!0 = !{}
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...
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---
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name: imp_null_check_with_bitwise_op_0
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# CHECK-LABEL: name: imp_null_check_with_bitwise_op_0
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alignment: 4
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allVRegsAllocated: true
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tracksRegLiveness: true
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tracksSubRegLiveness: false
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liveins:
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- { reg: '%rdi' }
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- { reg: '%esi' }
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# CHECK: bb.0.entry:
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# CHECK: %eax = MOV32ri 2200000
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# CHECK-NEXT: %eax = FAULTING_LOAD_OP %bb.3.is_null, 196, killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
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# CHECK-NEXT: JMP_1 %bb.1.not_null
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body: |
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bb.0.entry:
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successors: %bb.3.is_null, %bb.1.not_null
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liveins: %esi, %rdi
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TEST64rr %rdi, %rdi, implicit-def %eflags
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JE_1 %bb.3.is_null, implicit %eflags
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bb.1.not_null:
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successors: %bb.4.ret_100, %bb.2.ret_200
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liveins: %esi, %rdi
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%eax = MOV32ri 2200000
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%eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
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CMP32rr killed %eax, killed %esi, implicit-def %eflags
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JE_1 %bb.4.ret_100, implicit %eflags
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bb.2.ret_200:
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%eax = MOV32ri 200
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RET 0, %eax
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bb.3.is_null:
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%eax = MOV32ri 42
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RET 0, %eax
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bb.4.ret_100:
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%eax = MOV32ri 100
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RET 0, %eax
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...
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---
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name: imp_null_check_with_bitwise_op_1
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alignment: 4
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allVRegsAllocated: true
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isSSA: false
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||||
tracksRegLiveness: true
|
||||
tracksSubRegLiveness: false
|
||||
liveins:
|
||||
- { reg: '%rdi' }
|
||||
- { reg: '%esi' }
|
||||
- { reg: '%rdx' }
|
||||
# CHECK: bb.0.entry:
|
||||
# CHECK: %eax = MOV32rm killed %rdx, 1, _, 0, _ :: (volatile load 4 from %ir.ptr)
|
||||
# CHECK-NEXT: TEST64rr %rdi, %rdi, implicit-def %eflags
|
||||
# CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags
|
||||
|
||||
body: |
|
||||
bb.0.entry:
|
||||
successors: %bb.3.is_null, %bb.1.not_null
|
||||
liveins: %esi, %rdi, %rdx
|
||||
|
||||
%eax = MOV32rm killed %rdx, 1, _, 0, _ :: (volatile load 4 from %ir.ptr)
|
||||
TEST64rr %rdi, %rdi, implicit-def %eflags
|
||||
JE_1 %bb.3.is_null, implicit %eflags
|
||||
|
||||
bb.1.not_null:
|
||||
successors: %bb.4.ret_100, %bb.2.ret_200
|
||||
liveins: %esi, %rdi
|
||||
|
||||
%eax = MOV32ri 2200000
|
||||
%eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
|
||||
CMP32rr killed %eax, killed %esi, implicit-def %eflags
|
||||
JE_1 %bb.4.ret_100, implicit %eflags
|
||||
|
||||
bb.2.ret_200:
|
||||
successors: %bb.3.is_null
|
||||
|
||||
%eax = MOV32ri 200
|
||||
|
||||
bb.3.is_null:
|
||||
liveins: %eax, %ah, %al, %ax, %bh, %bl, %bp, %bpl, %bx, %eax, %ebp, %ebx, %rax, %rbp, %rbx, %r12, %r13, %r14, %r15, %r12b, %r13b, %r14b, %r15b, %r12d, %r13d, %r14d, %r15d, %r12w, %r13w, %r14w, %r15w
|
||||
|
||||
RET 0, %eax
|
||||
|
||||
bb.4.ret_100:
|
||||
%eax = MOV32ri 100
|
||||
RET 0, %eax
|
||||
|
||||
...
|
||||
---
|
||||
name: imp_null_check_with_bitwise_op_2
|
||||
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_2
|
||||
alignment: 4
|
||||
allVRegsAllocated: true
|
||||
tracksRegLiveness: true
|
||||
tracksSubRegLiveness: false
|
||||
liveins:
|
||||
- { reg: '%rdi' }
|
||||
- { reg: '%esi' }
|
||||
# CHECK: bb.0.entry:
|
||||
# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags
|
||||
# CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags
|
||||
|
||||
body: |
|
||||
bb.0.entry:
|
||||
successors: %bb.3.is_null, %bb.1.not_null
|
||||
liveins: %esi, %rdi
|
||||
|
||||
TEST64rr %rdi, %rdi, implicit-def %eflags
|
||||
JE_1 %bb.3.is_null, implicit %eflags
|
||||
|
||||
bb.1.not_null:
|
||||
successors: %bb.4.ret_100, %bb.2.ret_200
|
||||
liveins: %esi, %rdi
|
||||
|
||||
%eax = MOV32ri 2200000
|
||||
%eax = ADD32ri killed %eax, 100, implicit-def dead %eflags
|
||||
%eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
|
||||
CMP32rr killed %eax, killed %esi, implicit-def %eflags
|
||||
JE_1 %bb.4.ret_100, implicit %eflags
|
||||
|
||||
bb.2.ret_200:
|
||||
%eax = MOV32ri 200
|
||||
RET 0, %eax
|
||||
|
||||
bb.3.is_null:
|
||||
%eax = MOV32ri 42
|
||||
RET 0, %eax
|
||||
|
||||
bb.4.ret_100:
|
||||
%eax = MOV32ri 100
|
||||
RET 0, %eax
|
||||
|
||||
...
|
||||
---
|
||||
name: imp_null_check_with_bitwise_op_3
|
||||
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_3
|
||||
alignment: 4
|
||||
allVRegsAllocated: true
|
||||
tracksRegLiveness: true
|
||||
tracksSubRegLiveness: false
|
||||
liveins:
|
||||
- { reg: '%rdi' }
|
||||
- { reg: '%rsi' }
|
||||
# CHECK: bb.0.entry:
|
||||
# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags
|
||||
# CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags
|
||||
|
||||
body: |
|
||||
bb.0.entry:
|
||||
successors: %bb.3.is_null, %bb.1.not_null
|
||||
liveins: %rsi, %rdi
|
||||
|
||||
TEST64rr %rdi, %rdi, implicit-def %eflags
|
||||
JE_1 %bb.3.is_null, implicit %eflags
|
||||
|
||||
bb.1.not_null:
|
||||
successors: %bb.4.ret_100, %bb.2.ret_200
|
||||
liveins: %rsi, %rdi
|
||||
|
||||
%rdi = MOV64ri 5000
|
||||
%rdi = AND64rm killed %rdi, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
|
||||
CMP64rr killed %rdi, killed %rsi, implicit-def %eflags
|
||||
JE_1 %bb.4.ret_100, implicit %eflags
|
||||
|
||||
bb.2.ret_200:
|
||||
%eax = MOV32ri 200
|
||||
RET 0, %eax
|
||||
|
||||
bb.3.is_null:
|
||||
%eax = MOV32ri 42
|
||||
RET 0, %eax
|
||||
|
||||
bb.4.ret_100:
|
||||
%eax = MOV32ri 100
|
||||
RET 0, %eax
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue